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authorIgor Nabirushkin <inabirushkin@nvidia.com>2018-02-18 15:39:19 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-02-19 11:00:01 -0500
commit29c8cdd7ad2fefa85ccb36b6b39eeae01a8af868 (patch)
tree5ebef4e9a481d7980431756b3bbbedb59b1b43ed /include/linux
parentcc6c95a3be593d6c211852c1a831e4199110d527 (diff)
misc: tegra-profiler: force to use cntvct
- Add a parameter to force use of CNTVCT register for timestamps. - Always verify the profiled process in case when "sampling" flag is enabled. Bug 2063579 Change-Id: Ia7a6d7e797b2d4c9d3eac7827adece638d9cf3ab Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1660718 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Dmitry Antipov <dantipov@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/tegra_profiler.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h
index c5de07bf7..d101ccc1a 100644
--- a/include/linux/tegra_profiler.h
+++ b/include/linux/tegra_profiler.h
@@ -20,7 +20,7 @@
20#include <linux/ioctl.h> 20#include <linux/ioctl.h>
21 21
22#define QUADD_SAMPLES_VERSION 42 22#define QUADD_SAMPLES_VERSION 42
23#define QUADD_IO_VERSION 23 23#define QUADD_IO_VERSION 24
24 24
25#define QUADD_IO_VERSION_DYNAMIC_RB 5 25#define QUADD_IO_VERSION_DYNAMIC_RB 5
26#define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6 26#define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
@@ -41,6 +41,7 @@
41#define QUADD_IO_VERSION_CB_POWER_OF_2 21 41#define QUADD_IO_VERSION_CB_POWER_OF_2 21
42#define QUADD_IO_VERSION_RAW_EVENTS 22 42#define QUADD_IO_VERSION_RAW_EVENTS 22
43#define QUADD_IO_VERSION_SAMPLING_MODE 23 43#define QUADD_IO_VERSION_SAMPLING_MODE 23
44#define QUADD_IO_VERSION_FORCE_ARCH_TIMER 24
44 45
45#define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17 46#define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
46#define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18 47#define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
@@ -417,6 +418,7 @@ enum {
417#define QUADD_PARAM_EXTRA_BT_DWARF (1 << 7) 418#define QUADD_PARAM_EXTRA_BT_DWARF (1 << 7)
418#define QUADD_PARAM_EXTRA_PER_PMU_SETUP (1 << 8) 419#define QUADD_PARAM_EXTRA_PER_PMU_SETUP (1 << 8)
419#define QUADD_PARAM_EXTRA_SAMPLING (1 << 9) 420#define QUADD_PARAM_EXTRA_SAMPLING (1 << 9)
421#define QUADD_PARAM_EXTRA_FORCE_ARCH_TIMER (1 << 10)
420 422
421enum { 423enum {
422 QUADD_EVENT_TYPE_RAW = 0, 424 QUADD_EVENT_TYPE_RAW = 0,
@@ -495,6 +497,7 @@ enum {
495#define QUADD_COMM_CAP_EXTRA_ARCH_TIMER (1 << 8) 497#define QUADD_COMM_CAP_EXTRA_ARCH_TIMER (1 << 8)
496#define QUADD_COMM_CAP_EXTRA_RB_MMAP_OP (1 << 9) 498#define QUADD_COMM_CAP_EXTRA_RB_MMAP_OP (1 << 9)
497#define QUADD_COMM_CAP_EXTRA_CPU_MASK (1 << 10) 499#define QUADD_COMM_CAP_EXTRA_CPU_MASK (1 << 10)
500#define QUADD_COMM_CAP_EXTRA_ARCH_TIMER_USR (1 << 11)
498 501
499struct quadd_comm_cap { 502struct quadd_comm_cap {
500 u32 pmu:1, 503 u32 pmu:1,