diff options
| author | Arto Merilainen <amerilainen@nvidia.com> | 2014-10-05 14:02:39 -0400 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:01 -0400 |
| commit | 020d4e034f134e6fcfd1d1611cd53ff87a5187b3 (patch) | |
| tree | 4a04e2dea7924a1dd3feee689d2d6a78b90723a8 /include/linux | |
| parent | 086b8bb33a89e518fbb2afc5333528941ac8cf54 (diff) | |
video: tegra: host: Reorganize mutex allocations
This patch reorganizes mutex allocations to match the current
hardware use model. In addition, this patch removes no-longer-used
syncpoint base allocations
Bug 200041935
Change-Id: Ie94c645af559fa25af4cab00914c6daaf002b315
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/nvhost.h | 30 |
1 files changed, 10 insertions, 20 deletions
diff --git a/include/linux/nvhost.h b/include/linux/nvhost.h index 67ddd0a45..59f6e89a5 100644 --- a/include/linux/nvhost.h +++ b/include/linux/nvhost.h | |||
| @@ -60,27 +60,17 @@ struct sync_pt; | |||
| 60 | #define NVSYNCPT_VBLANK0 (26) /* t20, t30, t114, t148 */ | 60 | #define NVSYNCPT_VBLANK0 (26) /* t20, t30, t114, t148 */ |
| 61 | #define NVSYNCPT_VBLANK1 (27) /* t20, t30, t114, t148 */ | 61 | #define NVSYNCPT_VBLANK1 (27) /* t20, t30, t114, t148 */ |
| 62 | 62 | ||
| 63 | #define NVWAITBASE_2D_0 (1) /* t20, t30, t114 */ | 63 | #define NVMODMUTEX_ISP_0 (1) /* t124, t132, t210 */ |
| 64 | #define NVWAITBASE_2D_1 (2) /* t20, t30, t114 */ | 64 | #define NVMODMUTEX_ISP_1 (2) /* t124, t132, t210 */ |
| 65 | #define NVWAITBASE_3D (3) /* t20, t30, t114 */ | 65 | #define NVMODMUTEX_NVJPG (3) /* t210 */ |
| 66 | #define NVWAITBASE_MPE (4) /* t20, t30 */ | 66 | #define NVMODMUTEX_NVDEC (4) /* t210 */ |
| 67 | #define NVWAITBASE_MSENC (4) /* t114, t148 */ | 67 | #define NVMODMUTEX_MSENC (5) /* t124, t132, t210 */ |
| 68 | #define NVWAITBASE_TSEC (5) /* t114, t148 */ | 68 | #define NVMODMUTEX_TSECA (6) /* t124, t132, t210 */ |
| 69 | 69 | #define NVMODMUTEX_TSECB (7) /* t124, t132, t210 */ | |
| 70 | #define NVMODMUTEX_2D_FULL (1) /* t20, t30, t114, t148 */ | 70 | #define NVMODMUTEX_VI (8) /* t124, t132, t210 */ |
| 71 | #define NVMODMUTEX_ISP_0 (1) /* t124 */ | ||
| 72 | #define NVMODMUTEX_2D_SIMPLE (2) /* t20, t30, t114, t148 */ | ||
| 73 | #define NVMODMUTEX_ISP_1 (2) /* t124 */ | ||
| 74 | #define NVMODMUTEX_2D_SB_A (3) /* t20, t30, t114, t148 */ | ||
| 75 | #define NVMODMUTEX_2D_SB_B (4) /* t20, t30, t114, t148 */ | ||
| 76 | #define NVMODMUTEX_3D (5) /* t20, t30, t114, t148 */ | ||
| 77 | #define NVMODMUTEX_DISPLAYA (6) /* t20, t30, t114, t148 */ | ||
| 78 | #define NVMODMUTEX_DISPLAYB (7) /* t20, t30, t114, t148 */ | ||
| 79 | #define NVMODMUTEX_VI (8) /* t20, t30, t114 */ | ||
| 80 | #define NVMODMUTEX_VI_0 (8) /* t148 */ | 71 | #define NVMODMUTEX_VI_0 (8) /* t148 */ |
| 81 | #define NVMODMUTEX_DSI (9) /* t20, t30, t114, t148 */ | 72 | #define NVMODMUTEX_VIC (10) /* t124, t132, t210 */ |
| 82 | #define NVMODMUTEX_VIC (10) /* t124 */ | 73 | #define NVMODMUTEX_VI_1 (11) /* t124, t132, t210 */ |
| 83 | #define NVMODMUTEX_VI_1 (11) /* t124 */ | ||
| 84 | 74 | ||
| 85 | enum nvhost_power_sysfs_attributes { | 75 | enum nvhost_power_sysfs_attributes { |
| 86 | NVHOST_POWER_SYSFS_ATTRIB_CLOCKGATE_DELAY = 0, | 76 | NVHOST_POWER_SYSFS_ATTRIB_CLOCKGATE_DELAY = 0, |