summaryrefslogtreecommitdiffstats
path: root/include/linux/tegra_profiler.h
diff options
context:
space:
mode:
authorIgor Nabirushkin <inabirushkin@nvidia.com>2018-04-17 09:20:12 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-18 11:43:24 -0400
commitc3c4e00a8ddfcb888f640fc2aec3b69f53eae515 (patch)
tree98907deec98a81a43c4fbc1cfc81becca7a992b8 /include/linux/tegra_profiler.h
parente224e866f8b4b814b19ec854b49510507f0a06ae (diff)
misc: tegra-profiler: sample multiple processes
- Sample multiple processes. Add a few new modes. - Fix possible crash in d_path() during multiple execs. Bug 2104957 Bug 2100416 Change-Id: Iab1568de9365e1c719b45c65f490bbd212995b69 Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1696670 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Dmitry Antipov <dantipov@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux/tegra_profiler.h')
-rw-r--r--include/linux/tegra_profiler.h68
1 files changed, 39 insertions, 29 deletions
diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h
index d101ccc1a..2b08a2f90 100644
--- a/include/linux/tegra_profiler.h
+++ b/include/linux/tegra_profiler.h
@@ -19,8 +19,8 @@
19 19
20#include <linux/ioctl.h> 20#include <linux/ioctl.h>
21 21
22#define QUADD_SAMPLES_VERSION 42 22#define QUADD_SAMPLES_VERSION 43
23#define QUADD_IO_VERSION 24 23#define QUADD_IO_VERSION 25
24 24
25#define QUADD_IO_VERSION_DYNAMIC_RB 5 25#define QUADD_IO_VERSION_DYNAMIC_RB 5
26#define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6 26#define QUADD_IO_VERSION_RB_MAX_FILL_COUNT 6
@@ -42,33 +42,35 @@
42#define QUADD_IO_VERSION_RAW_EVENTS 22 42#define QUADD_IO_VERSION_RAW_EVENTS 22
43#define QUADD_IO_VERSION_SAMPLING_MODE 23 43#define QUADD_IO_VERSION_SAMPLING_MODE 23
44#define QUADD_IO_VERSION_FORCE_ARCH_TIMER 24 44#define QUADD_IO_VERSION_FORCE_ARCH_TIMER 24
45 45#define QUADD_IO_VERSION_SAMPLE_ALL_TASKS 25
46#define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17 46
47#define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18 47#define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17
48#define QUADD_SAMPLE_VERSION_THREAD_STATE_FLD 19 48#define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18
49#define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22 49#define QUADD_SAMPLE_VERSION_THREAD_STATE_FLD 19
50#define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23 50#define QUADD_SAMPLE_VERSION_BT_UNWIND_TABLES 22
51#define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24 51#define QUADD_SAMPLE_VERSION_SUPPORT_IP64 23
52#define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25 52#define QUADD_SAMPLE_VERSION_SPECIAL_MMAP 24
53#define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE 26 53#define QUADD_SAMPLE_VERSION_UNWIND_MIXED 25
54#define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER 27 54#define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE 26
55#define QUADD_SAMPLE_VERSION_SCHED_SAMPLES 28 55#define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER 27
56#define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29 56#define QUADD_SAMPLE_VERSION_SCHED_SAMPLES 28
57#define QUADD_SAMPLE_VERSION_HDR_ARCH_TIMER 30 57#define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD 29
58#define QUADD_SAMPLE_VERSION_STACK_OFFSET 31 58#define QUADD_SAMPLE_VERSION_HDR_ARCH_TIMER 30
59#define QUADD_SAMPLE_VERSION_SCHED_TASK_STATE 32 59#define QUADD_SAMPLE_VERSION_STACK_OFFSET 31
60#define QUADD_SAMPLE_VERSION_URCS 33 60#define QUADD_SAMPLE_VERSION_SCHED_TASK_STATE 32
61#define QUADD_SAMPLE_VERSION_HOTPLUG 34 61#define QUADD_SAMPLE_VERSION_URCS 33
62#define QUADD_SAMPLE_VERSION_PER_CPU_SETUP 35 62#define QUADD_SAMPLE_VERSION_HOTPLUG 34
63#define QUADD_SAMPLE_VERSION_REPORT_TGID 36 63#define QUADD_SAMPLE_VERSION_PER_CPU_SETUP 35
64#define QUADD_SAMPLE_VERSION_MMAP_TS 37 64#define QUADD_SAMPLE_VERSION_REPORT_TGID 36
65#define QUADD_SAMPLE_VERSION_RAW_EVENTS 38 65#define QUADD_SAMPLE_VERSION_MMAP_TS 37
66#define QUADD_SAMPLE_VERSION_OVERHEAD_INFO 39 66#define QUADD_SAMPLE_VERSION_RAW_EVENTS 38
67#define QUADD_SAMPLE_VERSION_REPORT_VPID 40 67#define QUADD_SAMPLE_VERSION_OVERHEAD_INFO 39
68#define QUADD_SAMPLE_VERSION_SCHED_REPORT_VPID 41 68#define QUADD_SAMPLE_VERSION_REPORT_VPID 40
69#define QUADD_SAMPLE_VERSION_SAMPLING_MODE 42 69#define QUADD_SAMPLE_VERSION_SCHED_REPORT_VPID 41
70 70#define QUADD_SAMPLE_VERSION_SAMPLING_MODE 42
71#define QUADD_MMAP_HEADER_VERSION 1 71#define QUADD_SAMPLE_VERSION_SAMPLE_ALL_TASKS 43
72
73#define QUADD_MMAP_HEADER_VERSION 1
72 74
73#define QUADD_MAX_COUNTERS 32 75#define QUADD_MAX_COUNTERS 32
74#define QUADD_MAX_PROCESS 64 76#define QUADD_MAX_PROCESS 64
@@ -359,6 +361,10 @@ struct quadd_debug_data {
359#define QUADD_HDR_HAS_CPUID (1 << 6) 361#define QUADD_HDR_HAS_CPUID (1 << 6)
360#define QUADD_HDR_MODE_TRACE_ALL (1 << 7) 362#define QUADD_HDR_MODE_TRACE_ALL (1 << 7)
361#define QUADD_HDR_MODE_SAMPLING (1 << 8) 363#define QUADD_HDR_MODE_SAMPLING (1 << 8)
364#define QUADD_HDR_MODE_TRACING (1 << 9)
365#define QUADD_HDR_MODE_SAMPLE_ALL (1 << 10)
366#define QUADD_HDR_MODE_SAMPLE_TREE (1 << 11)
367#define QUADD_HDR_MODE_TRACE_TREE (1 << 12)
362 368
363struct quadd_header_data { 369struct quadd_header_data {
364 u16 magic; 370 u16 magic;
@@ -419,6 +425,10 @@ enum {
419#define QUADD_PARAM_EXTRA_PER_PMU_SETUP (1 << 8) 425#define QUADD_PARAM_EXTRA_PER_PMU_SETUP (1 << 8)
420#define QUADD_PARAM_EXTRA_SAMPLING (1 << 9) 426#define QUADD_PARAM_EXTRA_SAMPLING (1 << 9)
421#define QUADD_PARAM_EXTRA_FORCE_ARCH_TIMER (1 << 10) 427#define QUADD_PARAM_EXTRA_FORCE_ARCH_TIMER (1 << 10)
428#define QUADD_PARAM_EXTRA_SAMPLE_ALL_TASKS (1 << 11)
429#define QUADD_PARAM_EXTRA_SAMPLE_TREE (1 << 12)
430#define QUADD_PARAM_EXTRA_TRACING (1 << 13)
431#define QUADD_PARAM_EXTRA_TRACE_TREE (1 << 14)
422 432
423enum { 433enum {
424 QUADD_EVENT_TYPE_RAW = 0, 434 QUADD_EVENT_TYPE_RAW = 0,