diff options
| author | Igor Nabirushkin <inabirushkin@nvidia.com> | 2018-08-21 15:47:12 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-26 00:04:45 -0400 |
| commit | 98e0dc9922ae5d91c657c9eb34838d374b043212 (patch) | |
| tree | 1a48b73bb8f46ad8b24e075c2179b0204314640d /include/linux/tegra_profiler.h | |
| parent | 69e02bc5b7bfa8e0fc54e991dcb92634036e521d (diff) | |
misc: tegra-profiler: add kernel thread flag
- Add Kernel thread flag for Sched and Composite events.
- Minor changes in output structures.
Bug 2340122
JIRA DTSP-462
Change-Id: Ifcfa36930612cfc4d601fefd3b2386fcda797b75
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804055
Reviewed-by: Roman Rybalko <rrybalko@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux/tegra_profiler.h')
| -rw-r--r-- | include/linux/tegra_profiler.h | 90 |
1 files changed, 45 insertions, 45 deletions
diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h index c20b88b6f..08f898abe 100644 --- a/include/linux/tegra_profiler.h +++ b/include/linux/tegra_profiler.h | |||
| @@ -19,7 +19,7 @@ | |||
| 19 | 19 | ||
| 20 | #include <linux/ioctl.h> | 20 | #include <linux/ioctl.h> |
| 21 | 21 | ||
| 22 | #define QUADD_SAMPLES_VERSION 43 | 22 | #define QUADD_SAMPLES_VERSION 44 |
| 23 | #define QUADD_IO_VERSION 25 | 23 | #define QUADD_IO_VERSION 25 |
| 24 | 24 | ||
| 25 | #define QUADD_IO_VERSION_DYNAMIC_RB 5 | 25 | #define QUADD_IO_VERSION_DYNAMIC_RB 5 |
| @@ -69,6 +69,7 @@ | |||
| 69 | #define QUADD_SAMPLE_VERSION_SCHED_REPORT_VPID 41 | 69 | #define QUADD_SAMPLE_VERSION_SCHED_REPORT_VPID 41 |
| 70 | #define QUADD_SAMPLE_VERSION_SAMPLING_MODE 42 | 70 | #define QUADD_SAMPLE_VERSION_SAMPLING_MODE 42 |
| 71 | #define QUADD_SAMPLE_VERSION_SAMPLE_ALL_TASKS 43 | 71 | #define QUADD_SAMPLE_VERSION_SAMPLE_ALL_TASKS 43 |
| 72 | #define QUADD_SAMPLE_VERSION_KTHREAD_TSK_FLAG 44 | ||
| 72 | 73 | ||
| 73 | #define QUADD_MMAP_HEADER_VERSION 1 | 74 | #define QUADD_MMAP_HEADER_VERSION 1 |
| 74 | 75 | ||
| @@ -191,8 +192,6 @@ enum quadd_cpu_mode { | |||
| 191 | 192 | ||
| 192 | #pragma pack(push, 1) | 193 | #pragma pack(push, 1) |
| 193 | 194 | ||
| 194 | #define QUADD_SAMPLE_RES_URCS_ENABLED (1 << 0) | ||
| 195 | |||
| 196 | #define QUADD_SAMPLE_URC_MASK 0xff | 195 | #define QUADD_SAMPLE_URC_MASK 0xff |
| 197 | 196 | ||
| 198 | #define QUADD_SAMPLE_URC_SHIFT_FP 0 | 197 | #define QUADD_SAMPLE_URC_SHIFT_FP 0 |
| @@ -221,8 +220,6 @@ enum { | |||
| 221 | QUADD_URC_MAX, | 220 | QUADD_URC_MAX, |
| 222 | }; | 221 | }; |
| 223 | 222 | ||
| 224 | #define QUADD_SED_IP64 (1 << 0) | ||
| 225 | |||
| 226 | #define QUADD_SED_STACK_OFFSET_SHIFT 1 | 223 | #define QUADD_SED_STACK_OFFSET_SHIFT 1 |
| 227 | #define QUADD_SED_STACK_OFFSET_MASK (0xffff << QUADD_SED_STACK_OFFSET_SHIFT) | 224 | #define QUADD_SED_STACK_OFFSET_MASK (0xffff << QUADD_SED_STACK_OFFSET_SHIFT) |
| 228 | 225 | ||
| @@ -236,20 +233,24 @@ enum { | |||
| 236 | QUADD_UNW_TYPE_DWARF_DF, | 233 | QUADD_UNW_TYPE_DWARF_DF, |
| 237 | }; | 234 | }; |
| 238 | 235 | ||
| 236 | #define QUADD_SAMPLE_FLAG_USER_MODE (1 << 0) | ||
| 237 | #define QUADD_SAMPLE_FLAG_LP_MODE (1 << 1) | ||
| 238 | #define QUADD_SAMPLE_FLAG_THUMB_MODE (1 << 2) | ||
| 239 | #define QUADD_SAMPLE_FLAG_STATE (1 << 3) | ||
| 240 | #define QUADD_SAMPLE_FLAG_IN_INTERRUPT (1 << 4) | ||
| 241 | #define QUADD_SAMPLE_FLAG_IS_VPID (1 << 5) | ||
| 242 | #define QUADD_SAMPLE_FLAG_PF_KTHREAD (1 << 6) | ||
| 243 | #define QUADD_SAMPLE_FLAG_URCS (1 << 7) | ||
| 244 | #define QUADD_SAMPLE_FLAG_IP64 (1 << 8) | ||
| 245 | |||
| 239 | struct quadd_sample_data { | 246 | struct quadd_sample_data { |
| 240 | u64 ip; | 247 | u64 ip; |
| 241 | u32 pid; | 248 | u32 pid; |
| 242 | u32 tgid; | 249 | u32 tgid; |
| 243 | u64 time; | 250 | u64 time; |
| 244 | 251 | ||
| 245 | u16 cpu:6, | 252 | u8 cpu_id; |
| 246 | user_mode:1, | 253 | u32 flags; |
| 247 | lp_mode:1, | ||
| 248 | thumb_mode:1, | ||
| 249 | state:1, | ||
| 250 | in_interrupt:1, | ||
| 251 | is_vpid:1, | ||
| 252 | reserved:4; | ||
| 253 | 254 | ||
| 254 | u8 callchain_nr; | 255 | u8 callchain_nr; |
| 255 | u32 events_flags; | 256 | u32 events_flags; |
| @@ -300,23 +301,19 @@ struct quadd_additional_sample { | |||
| 300 | u16 extra_length; | 301 | u16 extra_length; |
| 301 | }; | 302 | }; |
| 302 | 303 | ||
| 303 | enum { | 304 | #define QUADD_SCHED_FLAG_LP_MODE (1 << 0) |
| 304 | QUADD_SCHED_IDX_TASK_STATE = 0, | 305 | #define QUADD_SCHED_FLAG_SCHED_IN (1 << 1) |
| 305 | QUADD_SCHED_IDX_RESERVED, | 306 | #define QUADD_SCHED_FLAG_IS_VPID (1 << 2) |
| 306 | }; | 307 | #define QUADD_SCHED_FLAG_PF_KTHREAD (1 << 3) |
| 307 | 308 | ||
| 308 | struct quadd_sched_data { | 309 | struct quadd_sched_data { |
| 309 | u32 pid; | 310 | u32 pid; |
| 310 | u32 tgid; | 311 | u32 tgid; |
| 311 | u64 time; | 312 | u64 time; |
| 312 | 313 | ||
| 313 | u32 cpu:6, | 314 | u8 cpu_id; |
| 314 | lp_mode:1, | 315 | u64 flags; |
| 315 | sched_in:1, | 316 | u16 task_state; |
| 316 | is_vpid:1, | ||
| 317 | reserved:23; | ||
| 318 | |||
| 319 | u32 data[2]; | ||
| 320 | }; | 317 | }; |
| 321 | 318 | ||
| 322 | enum { | 319 | enum { |
| @@ -352,31 +349,34 @@ struct quadd_debug_data { | |||
| 352 | 349 | ||
| 353 | #define QUADD_HEADER_MAGIC 0x1122 | 350 | #define QUADD_HEADER_MAGIC 0x1122 |
| 354 | 351 | ||
| 355 | #define QUADD_HDR_BT_FP (1 << 0) | 352 | #define QUADD_HDR_FLAG_BACKTRACE (1 << 0) |
| 356 | #define QUADD_HDR_BT_UT (1 << 1) | 353 | #define QUADD_HDR_FLAG_USE_FREQ (1 << 1) |
| 357 | #define QUADD_HDR_BT_UT_CE (1 << 2) | 354 | #define QUADD_HDR_FLAG_POWER_RATE (1 << 2) |
| 358 | #define QUADD_HDR_USE_ARCH_TIMER (1 << 3) | 355 | #define QUADD_HDR_FLAG_DEBUG_SAMPLES (1 << 3) |
| 359 | #define QUADD_HDR_STACK_OFFSET (1 << 4) | 356 | #define QUADD_HDR_FLAG_GET_MMAP (1 << 4) |
| 360 | #define QUADD_HDR_BT_DWARF (1 << 5) | 357 | #define QUADD_HDR_FLAG_BT_FP (1 << 5) |
| 361 | #define QUADD_HDR_HAS_CPUID (1 << 6) | 358 | #define QUADD_HDR_FLAG_BT_UT (1 << 6) |
| 362 | #define QUADD_HDR_MODE_TRACE_ALL (1 << 7) | 359 | #define QUADD_HDR_FLAG_BT_UT_CE (1 << 7) |
| 363 | #define QUADD_HDR_MODE_SAMPLING (1 << 8) | 360 | #define QUADD_HDR_FLAG_BT_DWARF (1 << 8) |
| 364 | #define QUADD_HDR_MODE_TRACING (1 << 9) | 361 | #define QUADD_HDR_FLAG_USE_ARCH_TIMER (1 << 9) |
| 365 | #define QUADD_HDR_MODE_SAMPLE_ALL (1 << 10) | 362 | #define QUADD_HDR_FLAG_STACK_OFFSET (1 << 10) |
| 366 | #define QUADD_HDR_MODE_SAMPLE_TREE (1 << 11) | 363 | #define QUADD_HDR_FLAG_HAS_CPUID (1 << 11) |
| 367 | #define QUADD_HDR_MODE_TRACE_TREE (1 << 12) | 364 | #define QUADD_HDR_FLAG_MODE_SAMPLING (1 << 12) |
| 365 | #define QUADD_HDR_FLAG_MODE_TRACING (1 << 13) | ||
| 366 | #define QUADD_HDR_FLAG_MODE_SAMPLE_ALL (1 << 14) | ||
| 367 | #define QUADD_HDR_FLAG_MODE_TRACE_ALL (1 << 15) | ||
| 368 | #define QUADD_HDR_FLAG_MODE_SAMPLE_TREE (1 << 16) | ||
| 369 | #define QUADD_HDR_FLAG_MODE_TRACE_TREE (1 << 17) | ||
| 368 | 370 | ||
| 369 | struct quadd_header_data { | 371 | struct quadd_header_data { |
| 370 | u16 magic; | 372 | u16 magic; |
| 371 | u16 version; | 373 | u64 time; |
| 372 | 374 | ||
| 373 | u32 backtrace:1, | 375 | u16 samples_version; |
| 374 | use_freq:1, | 376 | u16 io_version; |
| 375 | system_wide:1, | 377 | |
| 376 | power_rate:1, | 378 | u8 cpu_id; |
| 377 | debug_samples:1, | 379 | u64 flags; |
| 378 | get_mmap:1, | ||
| 379 | reserved:26; /* reserved fields for future extensions */ | ||
| 380 | 380 | ||
| 381 | u32 freq; | 381 | u32 freq; |
| 382 | u16 ma_freq; | 382 | u16 ma_freq; |
