EQOS: allow PHY read/write if MAC clks enabled

Issue: During system suspend, PHY framework is trying to
access the PHY registers even though the ethernet interface
is not up which inturn causing the bus errors since MAC clocks
not enabled.

Fix: Add MAC clocks enable check before accessing the PHY
registers through MDIO bus.

Bug 200576747

Change-Id: Ifa02cbfe06ecb030d894807775b12d6eb5236783
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: http://git-master.nvidia.com/r/c/linux-nvidia/+/2275637
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

0 files changed, 0 insertions, 0 deletions