diff options
| author | Rich Wiley <rwiley@nvidia.com> | 2015-08-27 20:06:43 -0400 |
|---|---|---|
| committer | Alexander Van Brunt <avanbrunt@nvidia.com> | 2015-09-30 19:17:51 -0400 |
| commit | e547da824fbbb56c8c4f35e3804b2af02b9751a1 (patch) | |
| tree | bb89d249995a181bfbb4fa2c1e976e8c112adc33 /include/linux/platform/tegra | |
| parent | 0ba1ba569f23b6d4d95ce8cf9187e780799e7496 (diff) | |
platform: tegra: mc: update t18x mc regs
Change-Id: Ibaff75194a9daddd1c332e6bc315344e3ea0426b
Signed-off-by: Rich Wiley <rwiley@nvidia.com>
Reviewed-on: http://git-master/r/790650
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-on: http://git-master/r/807107
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Diffstat (limited to 'include/linux/platform/tegra')
| -rw-r--r-- | include/linux/platform/tegra/mc-regs-t18x.h | 34 |
1 files changed, 21 insertions, 13 deletions
diff --git a/include/linux/platform/tegra/mc-regs-t18x.h b/include/linux/platform/tegra/mc-regs-t18x.h index e6f468249..7ec72c53e 100644 --- a/include/linux/platform/tegra/mc-regs-t18x.h +++ b/include/linux/platform/tegra/mc-regs-t18x.h | |||
| @@ -237,16 +237,16 @@ | |||
| 237 | #define MC_RING2_PTSA_RATE 0x440 | 237 | #define MC_RING2_PTSA_RATE 0x440 |
| 238 | #define MC_USBD_PTSA_RATE 0x530 | 238 | #define MC_USBD_PTSA_RATE 0x530 |
| 239 | #define MC_USBX_PTSA_MIN 0x528 | 239 | #define MC_USBX_PTSA_MIN 0x528 |
| 240 | #define MC_USBD_PTSA_MIN 0x534 | ||
| 241 | #define MC_APB_PTSA_MAX 0x4f0 | ||
| 242 | #define MC_JPG_PTSA_RATE 0x584 | 240 | #define MC_JPG_PTSA_RATE 0x584 |
| 241 | #define MC_APB_PTSA_MAX 0x4f0 | ||
| 242 | #define MC_USBD_PTSA_MIN 0x534 | ||
| 243 | #define MC_DIS_PTSA_MIN 0x420 | 243 | #define MC_DIS_PTSA_MIN 0x420 |
| 244 | #define MC_RING1_PTSA_MIN 0x480 | 244 | #define MC_RING1_PTSA_MIN 0x480 |
| 245 | #define MC_DIS_PTSA_MAX 0x424 | 245 | #define MC_DIS_PTSA_MAX 0x424 |
| 246 | #define MC_SD_PTSA_MAX 0x4d8 | 246 | #define MC_SD_PTSA_MAX 0x4d8 |
| 247 | #define MC_MSE_PTSA_RATE 0x4c4 | 247 | #define MC_MSE_PTSA_RATE 0x4c4 |
| 248 | #define MC_VICPC_PTSA_MIN 0x558 | ||
| 249 | #define MC_PCX_PTSA_MAX 0x4b4 | 248 | #define MC_PCX_PTSA_MAX 0x4b4 |
| 249 | #define MC_VICPC_PTSA_MIN 0x558 | ||
| 250 | #define MC_AONDMAPC_PTSA_MIN 0x784 | 250 | #define MC_AONDMAPC_PTSA_MIN 0x784 |
| 251 | #define MC_ISP_PTSA_RATE 0x4a0 | 251 | #define MC_ISP_PTSA_RATE 0x4a0 |
| 252 | #define MC_RING2_PTSA_MAX 0x448 | 252 | #define MC_RING2_PTSA_MAX 0x448 |
| @@ -255,9 +255,9 @@ | |||
| 255 | #define MC_HOST_PTSA_MIN 0x51c | 255 | #define MC_HOST_PTSA_MIN 0x51c |
| 256 | #define MC_SDM1_PTSA_RATE 0x640 | 256 | #define MC_SDM1_PTSA_RATE 0x640 |
| 257 | #define MC_MLL_MPCORER_PTSA_MAX 0x454 | 257 | #define MC_MLL_MPCORER_PTSA_MAX 0x454 |
| 258 | #define MC_NVD_PTSA_MAX 0x580 | ||
| 259 | #define MC_NIC_PTSA_MAX 0x740 | ||
| 260 | #define MC_SD_PTSA_MIN 0x4d4 | 258 | #define MC_SD_PTSA_MIN 0x4d4 |
| 259 | #define MC_NIC_PTSA_MAX 0x740 | ||
| 260 | #define MC_NVD_PTSA_MAX 0x580 | ||
| 261 | #define MC_RING1_PTSA_RATE 0x47c | 261 | #define MC_RING1_PTSA_RATE 0x47c |
| 262 | #define MC_JPG_PTSA_MIN 0x588 | 262 | #define MC_JPG_PTSA_MIN 0x588 |
| 263 | #define MC_AONPC_PTSA_MAX 0x77c | 263 | #define MC_AONPC_PTSA_MAX 0x77c |
| @@ -265,8 +265,8 @@ | |||
| 265 | #define MC_HDAPC_PTSA_MIN 0x62c | 265 | #define MC_HDAPC_PTSA_MIN 0x62c |
| 266 | #define MC_JPG_PTSA_MAX 0x58c | 266 | #define MC_JPG_PTSA_MAX 0x58c |
| 267 | #define MC_VE_PTSA_MAX 0x43c | 267 | #define MC_VE_PTSA_MAX 0x43c |
| 268 | #define MC_DFD_PTSA_MAX 0x63c | ||
| 269 | #define MC_UFSHCPC_PTSA_MAX 0x74c | 268 | #define MC_UFSHCPC_PTSA_MAX 0x74c |
| 269 | #define MC_DFD_PTSA_MAX 0x63c | ||
| 270 | #define MC_SCEDMAPC_PTSA_RATE 0x798 | 270 | #define MC_SCEDMAPC_PTSA_RATE 0x798 |
| 271 | #define MC_VICPC_PTSA_RATE 0x554 | 271 | #define MC_VICPC_PTSA_RATE 0x554 |
| 272 | #define MC_BPMPPC_PTSA_RATE 0x75c | 272 | #define MC_BPMPPC_PTSA_RATE 0x75c |
| @@ -277,8 +277,8 @@ | |||
| 277 | #define MC_SDM_PTSA_MAX 0x624 | 277 | #define MC_SDM_PTSA_MAX 0x624 |
| 278 | #define MC_NVD_PTSA_RATE 0x578 | 278 | #define MC_NVD_PTSA_RATE 0x578 |
| 279 | #define MC_MSE2_PTSA_MIN 0x7cc | 279 | #define MC_MSE2_PTSA_MIN 0x7cc |
| 280 | #define MC_SAX_PTSA_RATE 0x4b8 | ||
| 281 | #define MC_PCX_PTSA_MIN 0x4b0 | 280 | #define MC_PCX_PTSA_MIN 0x4b0 |
| 281 | #define MC_SAX_PTSA_RATE 0x4b8 | ||
| 282 | #define MC_APB_PTSA_MIN 0x4ec | 282 | #define MC_APB_PTSA_MIN 0x4ec |
| 283 | #define MC_SCEPC_PTSA_RATE 0x78c | 283 | #define MC_SCEPC_PTSA_RATE 0x78c |
| 284 | #define MC_EQOSPC_PTSA_MIN 0x754 | 284 | #define MC_EQOSPC_PTSA_MIN 0x754 |
| @@ -292,16 +292,16 @@ | |||
| 292 | #define MC_HDAPC_PTSA_RATE 0x628 | 292 | #define MC_HDAPC_PTSA_RATE 0x628 |
| 293 | #define MC_MLL_MPCORER_PTSA_MIN 0x450 | 293 | #define MC_MLL_MPCORER_PTSA_MIN 0x450 |
| 294 | #define MC_GK2_PTSA_MAX 0x618 | 294 | #define MC_GK2_PTSA_MAX 0x618 |
| 295 | #define MC_VICPC3_PTSA_RATE 0x7b0 | ||
| 296 | #define MC_SDM1_PTSA_MIN 0x730 | 295 | #define MC_SDM1_PTSA_MIN 0x730 |
| 296 | #define MC_VICPC3_PTSA_RATE 0x7b0 | ||
| 297 | #define MC_AUD_PTSA_MAX 0x550 | 297 | #define MC_AUD_PTSA_MAX 0x550 |
| 298 | #define MC_GK2_PTSA_RATE 0x610 | 298 | #define MC_GK2_PTSA_RATE 0x610 |
| 299 | #define MC_NVD3_PTSA_MAX 0x7c4 | 299 | #define MC_NVD3_PTSA_MAX 0x7c4 |
| 300 | #define MC_ISP_PTSA_MAX 0x4a8 | 300 | #define MC_ISP_PTSA_MAX 0x4a8 |
| 301 | #define MC_NVD_PTSA_MIN 0x57c | 301 | #define MC_NVD_PTSA_MIN 0x57c |
| 302 | #define MC_DFD_PTSA_MIN 0x638 | ||
| 303 | #define MC_UFSHCPC_PTSA_MIN 0x748 | 302 | #define MC_UFSHCPC_PTSA_MIN 0x748 |
| 304 | #define MC_FTOP_PTSA_RATE 0x50c | 303 | #define MC_FTOP_PTSA_RATE 0x50c |
| 304 | #define MC_DFD_PTSA_MIN 0x638 | ||
| 305 | #define MC_VICPC3_PTSA_MAX 0x7b8 | 305 | #define MC_VICPC3_PTSA_MAX 0x7b8 |
| 306 | #define MC_NVD3_PTSA_MIN 0x7c0 | 306 | #define MC_NVD3_PTSA_MIN 0x7c0 |
| 307 | #define MC_USBX_PTSA_MAX 0x52c | 307 | #define MC_USBX_PTSA_MAX 0x52c |
| @@ -312,13 +312,13 @@ | |||
| 312 | #define MC_BPMPDMAPC_PTSA_MAX 0x770 | 312 | #define MC_BPMPDMAPC_PTSA_MAX 0x770 |
| 313 | #define MC_FTOP_PTSA_MAX 0x514 | 313 | #define MC_FTOP_PTSA_MAX 0x514 |
| 314 | #define MC_HDAPC_PTSA_MAX 0x630 | 314 | #define MC_HDAPC_PTSA_MAX 0x630 |
| 315 | #define MC_BPMPDMAPC_PTSA_RATE 0x768 | ||
| 316 | #define MC_SD_PTSA_RATE 0x4d0 | 315 | #define MC_SD_PTSA_RATE 0x4d0 |
| 316 | #define MC_BPMPDMAPC_PTSA_RATE 0x768 | ||
| 317 | #define MC_DFD_PTSA_RATE 0x634 | 317 | #define MC_DFD_PTSA_RATE 0x634 |
| 318 | #define MC_SDM_PTSA_RATE 0x61c | 318 | #define MC_SDM_PTSA_RATE 0x61c |
| 319 | #define MC_FTOP_PTSA_MIN 0x510 | 319 | #define MC_FTOP_PTSA_MIN 0x510 |
| 320 | #define MC_APB_PTSA_RATE 0x4e8 | ||
| 321 | #define MC_SDM_PTSA_MIN 0x620 | 320 | #define MC_SDM_PTSA_MIN 0x620 |
| 321 | #define MC_APB_PTSA_RATE 0x4e8 | ||
| 322 | #define MC_RING2_PTSA_MIN 0x444 | 322 | #define MC_RING2_PTSA_MIN 0x444 |
| 323 | #define MC_UFSHCPC_PTSA_RATE 0x744 | 323 | #define MC_UFSHCPC_PTSA_RATE 0x744 |
| 324 | #define MC_BPMPPC_PTSA_MAX 0x764 | 324 | #define MC_BPMPPC_PTSA_MAX 0x764 |
| @@ -331,10 +331,10 @@ | |||
| 331 | #define MC_SAX_PTSA_MIN 0x4bc | 331 | #define MC_SAX_PTSA_MIN 0x4bc |
| 332 | #define MC_NIC_PTSA_RATE 0x738 | 332 | #define MC_NIC_PTSA_RATE 0x738 |
| 333 | #define MC_SCEDMAPC_PTSA_MAX 0x7a0 | 333 | #define MC_SCEDMAPC_PTSA_MAX 0x7a0 |
| 334 | #define MC_AONDMAPC_PTSA_RATE 0x780 | ||
| 335 | #define MC_ISP_PTSA_MIN 0x4a4 | 334 | #define MC_ISP_PTSA_MIN 0x4a4 |
| 336 | #define MC_HOST_PTSA_MAX 0x520 | 335 | #define MC_AONDMAPC_PTSA_RATE 0x780 |
| 337 | #define MC_SDM1_PTSA_MAX 0x734 | 336 | #define MC_SDM1_PTSA_MAX 0x734 |
| 337 | #define MC_HOST_PTSA_MAX 0x520 | ||
| 338 | #define MC_BPMPPC_PTSA_MIN 0x760 | 338 | #define MC_BPMPPC_PTSA_MIN 0x760 |
| 339 | #define MC_SAX_PTSA_MAX 0x4c0 | 339 | #define MC_SAX_PTSA_MAX 0x4c0 |
| 340 | #define MC_VE_PTSA_MIN 0x438 | 340 | #define MC_VE_PTSA_MIN 0x438 |
| @@ -1070,9 +1070,15 @@ | |||
| 1070 | #define MC_ECC_CFG 0x1884 | 1070 | #define MC_ECC_CFG 0x1884 |
| 1071 | #define MC_TR_BIT_CTL 0xed0 | 1071 | #define MC_TR_BIT_CTL 0xed0 |
| 1072 | #define MC_CH_INTSTATUS 0xe54 | 1072 | #define MC_CH_INTSTATUS 0xe54 |
| 1073 | #define MC_LATENCY_ALLOWANCE_WCAM 0xe5c | ||
| 1073 | #define MC_CFG_WCAM 0xe60 | 1074 | #define MC_CFG_WCAM 0xe60 |
| 1074 | #define MC_WCAM_ENCR_KEY_STATUS 0xe64 | 1075 | #define MC_WCAM_ENCR_KEY_STATUS 0xe64 |
| 1075 | #define MC_WCAM_STATE 0xeb0 | 1076 | #define MC_WCAM_STATE 0xeb0 |
| 1077 | #define MC_WCAM_IRQ_TEST 0xedc | ||
| 1078 | #define MC_WCAM_IRQ_P0_STATUS0 0xee0 | ||
| 1079 | #define MC_WCAM_IRQ_P0_STATUS1 0xee4 | ||
| 1080 | #define MC_WCAM_IRQ_P1_STATUS0 0xee8 | ||
| 1081 | #define MC_WCAM_IRQ_P1_STATUS1 0xeec | ||
| 1076 | #define MC_ROC_DMA_R_PTSA_MIN 0xe68 | 1082 | #define MC_ROC_DMA_R_PTSA_MIN 0xe68 |
| 1077 | #define MC_ROC_DMA_R_PTSA_MAX 0xe6c | 1083 | #define MC_ROC_DMA_R_PTSA_MAX 0xe6c |
| 1078 | #define MC_ROC_DMA_R_PTSA_RATE 0xe70 | 1084 | #define MC_ROC_DMA_R_PTSA_RATE 0xe70 |
| @@ -1089,6 +1095,8 @@ | |||
| 1089 | #define MC_RING1_RD_NB_PTSA_MAX 0xe9c | 1095 | #define MC_RING1_RD_NB_PTSA_MAX 0xe9c |
| 1090 | #define MC_RING1_RD_NB_PTSA_RATE 0xea0 | 1096 | #define MC_RING1_RD_NB_PTSA_RATE 0xea0 |
| 1091 | #define MC_FREE_BANK_QUEUES 0xea4 | 1097 | #define MC_FREE_BANK_QUEUES 0xea4 |
| 1098 | #define MC_RING0_MT_FIFO_CREDITS 0xea8 | ||
| 1099 | #define MC_LATENCY_ALLOWANCE_ROC_DMA_R_0 0xeac | ||
| 1092 | #define MC_MEM_SCRUBBER_ECC_ADDR 0xf18 | 1100 | #define MC_MEM_SCRUBBER_ECC_ADDR 0xf18 |
| 1093 | #define MC_MEM_SCRUBBER_ECC_REG_CTRL 0xf20 | 1101 | #define MC_MEM_SCRUBBER_ECC_REG_CTRL 0xf20 |
| 1094 | #define MC_CCITRX_ENABLE_CONFIG 0xf3c | 1102 | #define MC_CCITRX_ENABLE_CONFIG 0xf3c |
