diff options
| author | Deepak Nibade <dnibade@nvidia.com> | 2017-11-16 02:34:20 -0500 |
|---|---|---|
| committer | Deepak Nibade <dnibade@nvidia.com> | 2017-11-16 02:44:33 -0500 |
| commit | 7047764bbc20ff8d839b646ad31bb4a9f97a243a (patch) | |
| tree | 72b59a5a40da704fc346e1048223f1b2ae6cd778 /include/linux/platform/tegra | |
| parent | 44b9b64dbde264b648a7c8ef9c136f9012123ef5 (diff) | |
| parent | 276714cceccf291b9cc05d71fe98fe2098fbfe01 (diff) | |
Merge remote-tracking branch 'remotes/origin/dev/linux-t19x' into linux-nvidia
Bug 200363166
Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'include/linux/platform/tegra')
| -rw-r--r-- | include/linux/platform/tegra/carmel_ras.h | 159 | ||||
| -rw-r--r-- | include/linux/platform/tegra/mc-regs-t19x.h | 2071 | ||||
| -rw-r--r-- | include/linux/platform/tegra/tegra-cpu.h | 24 | ||||
| -rw-r--r-- | include/linux/platform/tegra/tegra_cbb.h | 344 |
4 files changed, 2598 insertions, 0 deletions
diff --git a/include/linux/platform/tegra/carmel_ras.h b/include/linux/platform/tegra/carmel_ras.h new file mode 100644 index 000000000..66176252e --- /dev/null +++ b/include/linux/platform/tegra/carmel_ras.h | |||
| @@ -0,0 +1,159 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/arm64_ras.h> | ||
| 15 | |||
| 16 | /* Error Records Per Core */ | ||
| 17 | /* ERR_CTLR bits for IFU */ | ||
| 18 | #define RAS_IFU_CTL_ITLB_SNP_ERR RAS_BIT(43) | ||
| 19 | #define RAS_IFU_CTL_MITGRP_ERR RAS_BIT(42) | ||
| 20 | #define RAS_IFU_CTL_IMQDP_ERR RAS_BIT(41) | ||
| 21 | #define RAS_IFU_CTL_L2UC_ERR RAS_BIT(40) | ||
| 22 | #define RAS_IFU_CTL_ICTPSNP_ERR RAS_BIT(38) | ||
| 23 | #define RAS_IFU_CTL_ICMHSNP_ERR RAS_BIT(37) | ||
| 24 | #define RAS_IFU_CTL_ITLBP_ERR RAS_BIT(36) | ||
| 25 | #define RAS_IFU_CTL_THERR_ERR RAS_BIT(35) | ||
| 26 | #define RAS_IFU_CTL_ICDP_ERR RAS_BIT(34) | ||
| 27 | #define RAS_IFU_CTL_ICTP_ERR RAS_BIT(33) | ||
| 28 | #define RAS_IFU_CTL_ICMH_ERR RAS_BIT(32) | ||
| 29 | |||
| 30 | /* ERR_CTLR bits for RET_JSR */ | ||
| 31 | #define ERR_CTL_RET_JSR_FRFP_ERR RAS_BIT(35) | ||
| 32 | #define ERR_CTL_RET_JSR_IRFP_ERR RAS_BIT(34) | ||
| 33 | #define ERR_CTL_RET_JSR_GB_ERR RAS_BIT(33) | ||
| 34 | #define ERR_CTL_RET_JSR_TO_ERR RAS_BIT(32) | ||
| 35 | |||
| 36 | /* ERR_CTLR bits for MTS_JSR */ | ||
| 37 | #define ERR_CTL_MTS_JSR_ERRUC_ERR RAS_BIT(32) | ||
| 38 | #define ERR_CTL_MTS_JSR_ERRC_ERR RAS_BIT(33) | ||
| 39 | #define ERR_CTL_MTS_JSR_NAFLL_ERR RAS_BIT(34) | ||
| 40 | #define ERR_CTL_MTS_JSR_CARVE_ERR RAS_BIT(35) | ||
| 41 | #define ERR_CTL_MTS_JSR_CRAB_ERR RAS_BIT(36) | ||
| 42 | #define ERR_CTL_MTS_JSR_MMIO_ERR RAS_BIT(37) | ||
| 43 | |||
| 44 | /* ERR_CTLR bits for LSD_1 */ | ||
| 45 | #define ERR_CTL_LSD1_CCTP_ERR RAS_BIT(32) | ||
| 46 | #define ERR_CTL_LSD1_MCMH_ERR RAS_BIT(33) | ||
| 47 | #define ERR_CTL_LSD1_CCMH_ERR RAS_BIT(34) | ||
| 48 | #define ERR_CTL_LSD1_MCDLP_ERR RAS_BIT(35) | ||
| 49 | #define ERR_CTL_LSD1_CCDLECC_S_ERR RAS_BIT(36) | ||
| 50 | #define ERR_CTL_LSD1_CCDLECC_D_ERR RAS_BIT(37) | ||
| 51 | #define ERR_CTL_LSD1_CCDSECC_S_ERR RAS_BIT(38) | ||
| 52 | #define ERR_CTL_LSD1_CCDSECC_D_ERR RAS_BIT(39) | ||
| 53 | #define ERR_CTL_LSD1_CCDEMLECC_ERR RAS_BIT(40) | ||
| 54 | |||
| 55 | /* ERR_CTLR bits for LSD_2 */ | ||
| 56 | #define ERR_CTL_LSD2_BTCCVPP_ERR RAS_BIT(32) | ||
| 57 | #define ERR_CTL_LSD2_BTCCPPP_ERR RAS_BIT(33) | ||
| 58 | #define ERR_CTL_LSD2_BTCCMH_ERR RAS_BIT(34) | ||
| 59 | #define ERR_CTL_LSD2_VRCDECC_S_ERR RAS_BIT(35) | ||
| 60 | #define ERR_CTL_LSD2_VRCDECC_D_ERR RAS_BIT(36) | ||
| 61 | #define ERR_CTL_LSD2_VRCDP_ERR RAS_BIT(37) | ||
| 62 | #define ERR_CTL_LSD2_MCDEP_ERR RAS_BIT(38) | ||
| 63 | #define ERR_CTL_LSD2_CCDEECC_S_ERR RAS_BIT(39) | ||
| 64 | #define ERR_CTL_LSD2_CCDEECC_D_ERR RAS_BIT(40) | ||
| 65 | #define ERR_CTL_LSD2_L2REQ_UNCORR_ERR RAS_BIT(41) | ||
| 66 | |||
| 67 | /* ERR_CTLR bits for LSD_3 */ | ||
| 68 | #define ERR_CTL_LSD3_L2TLBP_ERR RAS_BIT(32) | ||
| 69 | #define ERR_CTL_LSD3_LATENT_ERR RAS_BIT(63) | ||
| 70 | |||
| 71 | /* Error records per CCPLEX */ | ||
| 72 | /* ERR_CTLR bits for CMU:CCPMU or DPMU*/ | ||
| 73 | #define ERR_CTL_DPMU_DMCE_CRAB_ACC_ERR RAS_BIT(32) | ||
| 74 | #define ERR_CTL_DPMU_CRAB_ACC_ERR RAS_BIT(33) | ||
| 75 | #define ERR_CTL_DPMU_DMCE_UCODE_ERR RAS_BIT(35) | ||
| 76 | |||
| 77 | /* ERR_CTLR bits for SCF:IOB*/ | ||
| 78 | #define ERR_CTL_SCFIOB_REQ_PAR_ERR RAS_BIT(41) | ||
| 79 | #define ERR_CTL_SCFIOB_PUT_PAR_ERR RAS_BIT(40) | ||
| 80 | #define ERR_CTL_SCFIOB_PUT_CECC_ERR RAS_BIT(32) | ||
| 81 | #define ERR_CTL_SCFIOB_PUT_UECC_ERR RAS_BIT(39) | ||
| 82 | #define ERR_CTL_SCFIOB_EVP_ERR RAS_BIT(33) | ||
| 83 | #define ERR_CTL_SCFIOB_TBX_ERR RAS_BIT(34) | ||
| 84 | #define ERR_CTL_SCFIOB_CRI_ERR RAS_BIT(35) | ||
| 85 | #define ERR_CTL_SCFIOB_MMCRAB_ERR RAS_BIT(37) | ||
| 86 | #define ERR_CTL_SCFIOB_IHI_ERR RAS_BIT(36) | ||
| 87 | #define ERR_CTL_SCFIOB_CBB_ERR RAS_BIT(38) | ||
| 88 | |||
| 89 | /* ERR_CTLR bits for SCF:SNOC*/ | ||
| 90 | #define ERR_CTL_SCFSNOC_CPE_TO_ERR RAS_BIT(34) | ||
| 91 | #define ERR_CTL_SCFSNOC_CPE_RSP_ERR RAS_BIT(35) | ||
| 92 | #define ERR_CTL_SCFSNOC_CPE_REQ_ERR RAS_BIT(36) | ||
| 93 | #define ERR_CTL_SCFSNOC_DVMU_TO_ERR RAS_BIT(37) | ||
| 94 | #define ERR_CTL_SCFSNOC_DVMU_PAR_ERR RAS_BIT(38) | ||
| 95 | #define ERR_CTL_SCFSNOC_MISC_CECC_ERR RAS_BIT(32) | ||
| 96 | #define ERR_CTL_SCFSNOC_MISC_UECC_ERR RAS_BIT(39) | ||
| 97 | #define ERR_CTL_SCFSNOC_MISC_PAR_ERR RAS_BIT(40) | ||
| 98 | #define ERR_CTL_SCFSNOC_MISC_RSP_ERR RAS_BIT(41) | ||
| 99 | #define ERR_CTL_SCFSNOC_CARVEOUT_ERR RAS_BIT(33) | ||
| 100 | |||
| 101 | /* ERR_CTLR bits for CMU:CTU*/ | ||
| 102 | #define ERR_CTL_CMUCTU_TRCDMA_PAR_ERR RAS_BIT(32) | ||
| 103 | #define ERR_CTL_CMUCTU_MCF_PAR_ERR RAS_BIT(33) | ||
| 104 | #define ERR_CTL_CMUCTU_TRL_PAR_ERR RAS_BIT(34) | ||
| 105 | #define ERR_CTL_CMUCTU_CTU_DATA_PAR_ERR RAS_BIT(35) | ||
| 106 | #define ERR_CTL_CMUCTU_TAG_PAR_ERR RAS_BIT(36) | ||
| 107 | #define ERR_CTL_CMUCTU_CTU_SNP_ERR RAS_BIT(37) | ||
| 108 | #define ERR_CTL_CMUCTU_TRCDMA_REQ_ERR RAS_BIT(38) | ||
| 109 | |||
| 110 | /* ERR_CTLR bits for SCF:L3_* */ | ||
| 111 | #define ERR_CTL_SCFL3_ADR_ERR RAS_BIT(38) | ||
| 112 | #define ERR_CTL_SCFL3_PERR_ERR RAS_BIT(40) | ||
| 113 | #define ERR_CTL_SCFL3_UECC_ERR RAS_BIT(39) | ||
| 114 | #define ERR_CTL_SCFL3_CECC_ERR RAS_BIT(41) | ||
| 115 | #define ERR_CTL_SCFL3_MH_CAM_ERR RAS_BIT(37) | ||
| 116 | #define ERR_CTL_SCFL3_MH_TAG_ERR RAS_BIT(36) | ||
| 117 | #define ERR_CTL_SCFL3_UNSUPP_REQ_ERR RAS_BIT(35) | ||
| 118 | #define ERR_CTL_SCFL3_PROT_ERR RAS_BIT(34) | ||
| 119 | #define ERR_CTL_SCFL3_TO_ERR RAS_BIT(33) | ||
| 120 | |||
| 121 | /* ERR_CTLR bits for SCFCMU_CLOCKS */ | ||
| 122 | #define ERR_CTL_SCFCMU_LUT0_PAR_ERR RAS_BIT(32) | ||
| 123 | #define ERR_CTL_SCFCMU_LUT1_PAR_ERR RAS_BIT(33) | ||
| 124 | #define ERR_CTL_SCFCMU_ADC0_MON_ERR RAS_BIT(34) | ||
| 125 | #define ERR_CTL_SCFCMU_ADC1_MON_ERR RAS_BIT(35) | ||
| 126 | |||
| 127 | /* Error records per Core Cluster */ | ||
| 128 | /* ERR_CTLR bits for L2 */ | ||
| 129 | #define ERR_CTL_L2_MLD_ECCC_ERR RAS_BIT(32) | ||
| 130 | #define ERR_CTL_L2_URD_ECCC_ERR RAS_BIT(33) | ||
| 131 | #define ERR_CTL_L2_MLD_ECCUD_ERR RAS_BIT(34) | ||
| 132 | #define ERR_CTL_L2_MLD_ECCUC_ERR RAS_BIT(36) | ||
| 133 | #define ERR_CTL_L2_URD_ECCUC_ERR RAS_BIT(37) | ||
| 134 | #define ERR_CTL_L2_NTDP_ERR RAS_BIT(38) | ||
| 135 | #define ERR_CTL_L2_URDP RAS_BIT(39) | ||
| 136 | #define ERR_CTL_L2_MLTP_ERR RAS_BIT(40) | ||
| 137 | #define ERR_CTL_L2_NTTP_ERR RAS_BIT(41) | ||
| 138 | #define ERR_CTL_L2_URTP_ERR RAS_BIT(42) | ||
| 139 | #define ERR_CTL_L2_L2MH_ERR RAS_BIT(43) | ||
| 140 | #define ERR_CTL_L2_CORE02L2CP_ERR RAS_BIT(44) | ||
| 141 | #define ERR_CTL_L2_CORE12L2CP_ERR RAS_BIT(45) | ||
| 142 | #define ERR_CTL_L2_SCF2L2C_ECCC_ERR RAS_BIT(46) | ||
| 143 | #define ERR_CTL_L2_SCF2L2C_ECCU_ERR RAS_BIT(47) | ||
| 144 | #define ERR_CTL_L2_SCF2L2C_FILLDATAP_ERR RAS_BIT(48) | ||
| 145 | #define ERR_CTL_L2_SCF2L2C_ADVNOTP_ERR RAS_BIT(49) | ||
| 146 | #define ERR_CTL_L2_SCF2L2C_REQRSPP_ERR RAS_BIT(50) | ||
| 147 | #define ERR_CTL_L2_SCF2L2C_DECWTERR_ERR RAS_BIT(51) | ||
| 148 | #define ERR_CTL_L2_SCF2L2C_DECRDERR_ERR RAS_BIT(52) | ||
| 149 | #define ERR_CTL_L2_SCF2L2C_SLVWTERR_ERR RAS_BIT(53) | ||
| 150 | #define ERR_CTL_L2_SCF2L2C_SLVRDERR_ERR RAS_BIT(54) | ||
| 151 | #define ERR_CTL_L2_L2PCL_ERR RAS_BIT(55) | ||
| 152 | #define ERR_CTL_L2_URTTO_ERR RAS_BIT(56) | ||
| 153 | |||
| 154 | /* ERR_CTLR bits for MMU */ | ||
| 155 | #define ERR_CTL_MMU_ACPERR_ERR RAS_BIT(32) | ||
| 156 | #define ERR_CTL_MMU_WCPERR_ERR RAS_BIT(34) | ||
| 157 | |||
| 158 | /* ERR_CTLR bits for CLUSTER_CLOCKS */ | ||
| 159 | #define ERR_CTL_CC_FREQ_MON_ERR RAS_BIT(32) | ||
diff --git a/include/linux/platform/tegra/mc-regs-t19x.h b/include/linux/platform/tegra/mc-regs-t19x.h new file mode 100644 index 000000000..17ad19801 --- /dev/null +++ b/include/linux/platform/tegra/mc-regs-t19x.h | |||
| @@ -0,0 +1,2071 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2017, NVIDIA Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This software is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2, as published by the Free Software Foundation, and | ||
| 6 | * may be copied, distributed, and modified under those terms. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __MACH_TEGRA_MC_REGS_T19X_H__ | ||
| 15 | #define __MACH_TEGRA_MC_REGS_T19X_H__ | ||
| 16 | |||
| 17 | /* Auto generated. Do not edit. */ | ||
| 18 | #define MC_MCF_ORSPX_RDRSP 0x8004 | ||
| 19 | #define MC_MCF_ORSPX_WRRSP 0x8008 | ||
| 20 | #define MC_MCF_IRSPX_RDRSP_OPT 0x800c | ||
| 21 | #define MC_MCF_ORSPX_CLKEN_OVERRIDE 0x8010 | ||
| 22 | #define MC_MCF_IRSPX_CLKEN_OVERRIDE 0x8014 | ||
| 23 | #define MC_MCF_ORSPX_PM_FIFO_SRC_MATCH 0x8018 | ||
| 24 | #define MC_MCF_ORSPX_PM_FIFO_CONFIG 0x801c | ||
| 25 | #define MC_MCF_IRSPX_PM_FIFO_SRC_MATCH 0x8020 | ||
| 26 | #define MC_MCF_IREQX_VCARB_CONFIG 0x8100 | ||
| 27 | #define MC_MCF_OREQX_VCARB_CONFIG 0x8104 | ||
| 28 | #define MC_MCF_OREQX_LLARB_CONFIG 0x8108 | ||
| 29 | #define MC_MCF_IREQX_SRC_WEIGHT_0 0x810c | ||
| 30 | #define MC_MCF_IREQX_SRC_WEIGHT_1 0x8110 | ||
| 31 | #define MC_MCF_IREQX_CLKEN_OVERRIDE 0x8114 | ||
| 32 | #define MC_MCF_OREQX_CLKEN_OVERRIDE 0x8118 | ||
| 33 | #define MC_MCF_IREQX_PM_FIFO_SRC_MATCH0 0x8130 | ||
| 34 | #define MC_MCF_IREQX_PM_FIFO_SRC_MATCH1 0x8134 | ||
| 35 | #define MC_MCF_IREQX_PM_FIFO_SUM_MSK 0x8138 | ||
| 36 | #define MC_MCF_IREQX_PM_FIFO_SRC_MISC 0x813c | ||
| 37 | #define MC_MCF_OREQX_PM_FIFO_SRC_MATCH0 0x8140 | ||
| 38 | #define MC_MCF_OREQX_PM_FIFO_SRC_MATCH1 0x8144 | ||
| 39 | #define MC_MCF_OREQX_PM_FIFO_SUM_MSK 0x8148 | ||
| 40 | #define MC_MCF_OREQX_PM_FIFO_SRC_MISC 0x814c | ||
| 41 | #define MC_MCF_IREQX_HUB_FIFO_NISO 0x8200 | ||
| 42 | #define MC_MCF_IREQX_HUB_FIFO_SISO 0x8204 | ||
| 43 | #define MC_MCF_IREQX_HUB_FIFO_ISO 0x8208 | ||
| 44 | #define MC_MCF_IREQX_HUB_FIFO_TRANS_DONE 0x820c | ||
| 45 | #define MC_MCF_IREQX_HUB_FIFO_ORD_1 0x8214 | ||
| 46 | #define MC_MCF_IREQX_HUB_FIFO_ORD_2 0x8218 | ||
| 47 | #define MC_MCF_IREQX_HUB_FIFO_ORD_3 0x821c | ||
| 48 | #define MC_MCF_IREQX_HUB_FIFO_SHARED 0x8220 | ||
| 49 | #define MC_MCF_IREQX_NVL_FIFO_NISO 0x8224 | ||
| 50 | #define MC_MCF_IREQX_NVL_FIFO_SISO 0x8228 | ||
| 51 | #define MC_MCF_IREQX_NVL_FIFO_ISO 0x822c | ||
| 52 | #define MC_MCF_IREQX_NVL_FIFO_TRANS_DONE 0x8230 | ||
| 53 | #define MC_MCF_IREQX_NVL_FIFO_ORD_1 0x8238 | ||
| 54 | #define MC_MCF_IREQX_NVL_FIFO_ORD_2 0x823c | ||
| 55 | #define MC_MCF_IREQX_NVL_FIFO_ORD_3 0x8240 | ||
| 56 | #define MC_MCF_IREQX_NVL_FIFO_SHARED 0x8244 | ||
| 57 | #define MC_MCF_OREQX_MCF_FIFO_NISO 0x8248 | ||
| 58 | #define MC_MCF_OREQX_MCF_FIFO_SISO 0x824c | ||
| 59 | #define MC_MCF_OREQX_MCF_FIFO_ISO 0x8250 | ||
| 60 | #define MC_MCF_OREQX_MCF_FIFO_CPU_LL 0x8254 | ||
| 61 | #define MC_MCF_OREQX_MCF_FIFO_NISO_REMOTE 0x8258 | ||
| 62 | #define MC_MCF_OREQX_MCF_FIFO_SHARED 0x825c | ||
| 63 | #define MC_MCF_OREQX_SCF_FIFO_NISO 0x8260 | ||
| 64 | #define MC_MCF_OREQX_SCF_FIFO_SISO 0x8264 | ||
| 65 | #define MC_MCF_OREQX_SCF_FIFO_ISO 0x8268 | ||
| 66 | #define MC_MCF_OREQX_SCF_FIFO_CPU_LL 0x826c | ||
| 67 | #define MC_MCF_OREQX_SCF_FIFO_NISO_REMOTE 0x8270 | ||
| 68 | #define MC_MCF_OREQX_SCF_FIFO_SHARED 0x8274 | ||
| 69 | #define MC_MCF_OREQX_SCF_LLFIFO_CPU_LL 0x8278 | ||
| 70 | #define MC_MCF_SLICE_CFG 0x8300 | ||
| 71 | #define MC_MCF_SLICE_FL_NISO_LIMIT 0x8304 | ||
| 72 | #define MC_MCF_SLICE_FL_SISO_LIMIT 0x8308 | ||
| 73 | #define MC_MCF_SLICE_FL_ISO_LIMIT 0x830c | ||
| 74 | #define MC_MCF_SLICE_FL_TRANSDONE_LIMIT 0x8310 | ||
| 75 | #define MC_MCF_SLICE_FL_NISO_REMOTE_LIMIT 0x8314 | ||
| 76 | #define MC_MCF_SLICE_FL_ORD1_LIMIT 0x8318 | ||
| 77 | #define MC_MCF_SLICE_FL_ORD2_LIMIT 0x831c | ||
| 78 | #define MC_MCF_SLICE_FL_ORD3_LIMIT 0x8320 | ||
| 79 | #define MC_MCF_SLICE_CLKEN_OVERRIDE 0x8324 | ||
| 80 | #define MC_MSS_SYSRAM_INIT 0x8c00 | ||
| 81 | #define MC_MSS_SYSRAM_CLKEN_OVERRIDE 0x8c04 | ||
| 82 | #define MC_MSS_SBS_ASYNC 0x8f00 | ||
| 83 | #define MC_MSS_SBS_ARB 0x8f04 | ||
| 84 | #define MC_MSS_SBS_INTSTATUS 0x8f08 | ||
| 85 | #define MC_MSS_SBS_INTMASK 0x8f0c | ||
| 86 | #define MC_MSS_SBS_CLKEN_OVERRIDE 0x8f10 | ||
| 87 | #define MC_MSS_SBS_VC_LIMIT 0x8f14 | ||
| 88 | #define MC_REGIF_CONFIG 0xf80 | ||
| 89 | #define MC_REGIF_CONFIG_1 0xf8c | ||
| 90 | #define MC_REGIF_CONFIG_2 0x3700 | ||
| 91 | #define MC_REGIF_BROADCAST 0xf84 | ||
| 92 | #define MC_REGIF_BROADCAST_1 0xf88 | ||
| 93 | #define MC_REGIF_BROADCAST_2 0x3704 | ||
| 94 | #define MC_REGIF_UNICAST0 0xf90 | ||
| 95 | #define MC_REGIF_UNICAST0_1 0x1134 | ||
| 96 | #define MC_REGIF_UNICAST0_2 0x370c | ||
| 97 | #define MC_REGIF_UNICAST1 0xf94 | ||
| 98 | #define MC_REGIF_UNICAST1_1 0x1140 | ||
| 99 | #define MC_REGIF_UNICAST1_2 0x3710 | ||
| 100 | #define MC_REGIF_UNICAST2 0xf98 | ||
| 101 | #define MC_REGIF_UNICAST2_1 0x1144 | ||
| 102 | #define MC_REGIF_UNICAST2_2 0x3714 | ||
| 103 | #define MC_REGIF_UNICAST3 0xf9c | ||
| 104 | #define MC_REGIF_UNICAST3_1 0x1148 | ||
| 105 | #define MC_REGIF_UNICAST3_2 0x3718 | ||
| 106 | #define MC_REGIF_UNICAST4 0x1164 | ||
| 107 | #define MC_REGIF_UNICAST4_1 0x114c | ||
| 108 | #define MC_REGIF_UNICAST4_2 0x371c | ||
| 109 | #define MC_REGIF_UNICAST5 0x1168 | ||
| 110 | #define MC_REGIF_UNICAST5_1 0x1150 | ||
| 111 | #define MC_REGIF_UNICAST5_2 0x3720 | ||
| 112 | #define MC_REGIF_UNICAST6 0x116c | ||
| 113 | #define MC_REGIF_UNICAST6_1 0x1154 | ||
| 114 | #define MC_REGIF_UNICAST6_2 0x3724 | ||
| 115 | #define MC_REGIF_UNICAST7 0x1170 | ||
| 116 | #define MC_REGIF_UNICAST7_1 0x1160 | ||
| 117 | #define MC_REGIF_UNICAST7_2 0x3728 | ||
| 118 | #define MC_REGIF_UNICAST8 0x372c | ||
| 119 | #define MC_REGIF_UNICAST8_1 0x374c | ||
| 120 | #define MC_REGIF_UNICAST8_2 0x376c | ||
| 121 | #define MC_REGIF_UNICAST9 0x3730 | ||
| 122 | #define MC_REGIF_UNICAST9_1 0x3750 | ||
| 123 | #define MC_REGIF_UNICAST9_2 0x3770 | ||
| 124 | #define MC_REGIF_UNICAST10 0x3734 | ||
| 125 | #define MC_REGIF_UNICAST10_1 0x3754 | ||
| 126 | #define MC_REGIF_UNICAST10_2 0x3774 | ||
| 127 | #define MC_REGIF_UNICAST11 0x3738 | ||
| 128 | #define MC_REGIF_UNICAST11_1 0x3758 | ||
| 129 | #define MC_REGIF_UNICAST11_2 0x3778 | ||
| 130 | #define MC_REGIF_UNICAST12 0x373c | ||
| 131 | #define MC_REGIF_UNICAST12_1 0x375c | ||
| 132 | #define MC_REGIF_UNICAST12_2 0x377c | ||
| 133 | #define MC_REGIF_UNICAST13 0x3740 | ||
| 134 | #define MC_REGIF_UNICAST13_1 0x3760 | ||
| 135 | #define MC_REGIF_UNICAST13_2 0x3780 | ||
| 136 | #define MC_REGIF_UNICAST14 0x3744 | ||
| 137 | #define MC_REGIF_UNICAST14_1 0x3764 | ||
| 138 | #define MC_REGIF_UNICAST14_2 0x3784 | ||
| 139 | #define MC_REGIF_UNICAST15 0x3748 | ||
| 140 | #define MC_REGIF_UNICAST15_1 0x3768 | ||
| 141 | #define MC_REGIF_UNICAST15_2 0x3788 | ||
| 142 | #define MC_INTSTATUS 0x0 | ||
| 143 | #define MC_INTMASK 0x4 | ||
| 144 | #define MC_INTPRIORITY 0xec4 | ||
| 145 | #define MC_HUBC_INTSTATUS 0xf2c | ||
| 146 | #define MC_HUB_INTMASK 0xf50 | ||
| 147 | #define MC_HUB_INTPRIORITY 0xf54 | ||
| 148 | #define MC_HUB_INTSTATUS 0xf58 | ||
| 149 | #define MC_GLOBAL_INTSTATUS 0xf24 | ||
| 150 | #define MC_GLOBAL_CRITICAL_INTSTATUS 0xf28 | ||
| 151 | #define MC_GLOBAL_INTSTATUS_1 0x37e0 | ||
| 152 | #define MC_GLOBAL_CRITICAL_INTSTATUS_1 0x37e4 | ||
| 153 | #define MC_ERR_STATUS 0x8 | ||
| 154 | #define MC_ERR_ADR 0xc | ||
| 155 | #define MC_ERR_ADR_HI 0x11fc | ||
| 156 | #define MC_PCFIFO_CLIENT_CONFIG0 0xdd0 | ||
| 157 | #define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 | ||
| 158 | #define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 | ||
| 159 | #define MC_PCFIFO_CLIENT_CONFIG3 0xddc | ||
| 160 | #define MC_PCFIFO_CLIENT_CONFIG4 0xde0 | ||
| 161 | #define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 | ||
| 162 | #define MC_PCFIFO_CLIENT_CONFIG6 0xb90 | ||
| 163 | #define MC_PCFIFO_CLIENT_CONFIG7 0xacc | ||
| 164 | #define MC_EMEM_CFG 0x50 | ||
| 165 | #define MC_EMEM_ADR_CFG 0x54 | ||
| 166 | #define MC_EMEM_ADR_CFG_DEV0 0x58 | ||
| 167 | #define MC_EMEM_ADR_CFG_DEV1 0x5c | ||
| 168 | #define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8 | ||
| 169 | #define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60 | ||
| 170 | #define MC_EMEM_ADR_CFG_CHANNEL_MASK_1 0xdfc | ||
| 171 | #define MC_EMEM_ADR_CFG_CHANNEL_MASK_2 0xdf4 | ||
| 172 | #define MC_EMEM_ADR_CFG_CHANNEL_MASK_3 0xdf0 | ||
| 173 | #define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64 | ||
| 174 | #define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68 | ||
| 175 | #define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c | ||
| 176 | #define MC_SECURITY_CFG0 0x70 | ||
| 177 | #define MC_SECURITY_CFG1 0x74 | ||
| 178 | #define MC_SECURITY_CFG_REG_CTRL 0x154 | ||
| 179 | #define MC_SECURITY_CFG3 0x9bc | ||
| 180 | #define MC_SECURITY_RSV 0x7c | ||
| 181 | #define MC_EMEM_ARB_CFG 0x90 | ||
| 182 | #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 | ||
| 183 | #define MC_EMEM_ARB_TIMING_RCD 0x98 | ||
| 184 | #define MC_EMEM_ARB_TIMING_RP 0x9c | ||
| 185 | #define MC_EMEM_ARB_TIMING_RC 0xa0 | ||
| 186 | #define MC_EMEM_ARB_TIMING_RAS 0xa4 | ||
| 187 | #define MC_EMEM_ARB_TIMING_FAW 0xa8 | ||
| 188 | #define MC_EMEM_ARB_TIMING_RRD 0xac | ||
| 189 | #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 | ||
| 190 | #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 | ||
| 191 | #define MC_EMEM_ARB_TIMING_R2R 0xb8 | ||
| 192 | #define MC_EMEM_ARB_TIMING_W2W 0xbc | ||
| 193 | #define MC_EMEM_ARB_TIMING_R2W 0xc0 | ||
| 194 | #define MC_EMEM_ARB_TIMING_W2R 0xc4 | ||
| 195 | #define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 | ||
| 196 | #define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 | ||
| 197 | #define MC_EMEM_ARB_TIMING_PBR2PBR 0x6c8 | ||
| 198 | #define MC_EMEM_ARB_TIMING_PDEX 0x6cc | ||
| 199 | #define MC_EMEM_ARB_TIMING_SREX 0x6d0 | ||
| 200 | #define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 | ||
| 201 | #define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 | ||
| 202 | #define MC_EMEM_ARB_DA_TURNS 0xd0 | ||
| 203 | #define MC_EMEM_ARB_DA_COVERS 0xd4 | ||
| 204 | #define MC_EMEM_ARB_DA_HYSTERESIS 0x9fc | ||
| 205 | #define MC_EMEM_ARB_MISC0 0xd8 | ||
| 206 | #define MC_EMEM_ARB_MISC1 0xdc | ||
| 207 | #define MC_EMEM_ARB_MISC2 0xc8 | ||
| 208 | #define MC_EMEM_ARB_MISC3 0x23c | ||
| 209 | #define MC_EMEM_ARB_MISC4 0x240 | ||
| 210 | #define MC_EMEM_ARB_RING1_THROTTLE 0xe0 | ||
| 211 | #define MC_EMEM_ARB_RING3_THROTTLE 0xe4 | ||
| 212 | #define MC_EMEM_ARB_NISO_THROTTLE 0x6b0 | ||
| 213 | #define MC_EMEM_ARB_OVERRIDE 0xe8 | ||
| 214 | #define MC_EMEM_ARB_RSV 0xec | ||
| 215 | #define MC_CLKEN_OVERRIDE 0xf4 | ||
| 216 | #define MC_HUB_CLKEN_OVERRIDE 0xfa0 | ||
| 217 | #define MC_HUB_VCTHROTTLE_OVERRIDE 0xfa4 | ||
| 218 | #define MC_CLKEN_A1_OVERRIDE 0xcc | ||
| 219 | #define MC_TIMING_CONTROL_DBG 0xf8 | ||
| 220 | #define MC_TIMING_CONTROL 0xfc | ||
| 221 | #define MC_STAT_CONTROL 0x100 | ||
| 222 | #define MC_STAT_STATUS 0x104 | ||
| 223 | #define MC_STAT_EMC_CLOCK_LIMIT 0x108 | ||
| 224 | #define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c | ||
| 225 | #define MC_STAT_EMC_CLOCKS 0x110 | ||
| 226 | #define MC_STAT_EMC_CLOCKS_MSBS 0x114 | ||
| 227 | #define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118 | ||
| 228 | #define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158 | ||
| 229 | #define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c | ||
| 230 | #define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c | ||
| 231 | #define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20 | ||
| 232 | #define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24 | ||
| 233 | #define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198 | ||
| 234 | #define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8 | ||
| 235 | #define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c | ||
| 236 | #define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac | ||
| 237 | #define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28 | ||
| 238 | #define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c | ||
| 239 | #define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0 | ||
| 240 | #define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0 | ||
| 241 | #define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120 | ||
| 242 | #define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160 | ||
| 243 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128 | ||
| 244 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168 | ||
| 245 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c | ||
| 246 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c | ||
| 247 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130 | ||
| 248 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170 | ||
| 249 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134 | ||
| 250 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88 | ||
| 251 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_5 0xbc4 | ||
| 252 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_6 0xac4 | ||
| 253 | #define MC_STAT_EMC_FILTER_SET0_CLIENT_7 0xac8 | ||
| 254 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174 | ||
| 255 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c | ||
| 256 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_5 0xbc8 | ||
| 257 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_6 0xec8 | ||
| 258 | #define MC_STAT_EMC_FILTER_SET1_CLIENT_7 0xecc | ||
| 259 | #define MC_STAT_EMC_SET0_COUNT 0x138 | ||
| 260 | #define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c | ||
| 261 | #define MC_STAT_EMC_SET1_COUNT 0x178 | ||
| 262 | #define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c | ||
| 263 | #define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140 | ||
| 264 | #define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144 | ||
| 265 | #define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180 | ||
| 266 | #define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184 | ||
| 267 | #define MC_STAT_EMC_SET0_HISTO_COUNT 0x148 | ||
| 268 | #define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c | ||
| 269 | #define MC_STAT_EMC_SET1_HISTO_COUNT 0x188 | ||
| 270 | #define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c | ||
| 271 | #define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150 | ||
| 272 | #define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190 | ||
| 273 | #define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8 | ||
| 274 | #define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc | ||
| 275 | #define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8 | ||
| 276 | #define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc | ||
| 277 | #define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0 | ||
| 278 | #define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0 | ||
| 279 | #define MC_CIFLL_MISC0 0xf60 | ||
| 280 | #define MC_CIFLL_REDEADLINE0 0xf64 | ||
| 281 | #define MC_CIFLL_REDEADLINE1 0xf68 | ||
| 282 | #define MC_CIFLL_REQ_MT_FIFO_CREDITS 0xf6c | ||
| 283 | #define MC_CIFLL_WRDAT_MT_FIFO_CREDITS 0xf70 | ||
| 284 | #define MC_CLIENT_HOTRESET_CTRL 0x200 | ||
| 285 | #define MC_CLIENT_HOTRESET_CTRL_1 0x970 | ||
| 286 | #define MC_CLIENT_HOTRESET_CTRL_2 0x97c | ||
| 287 | #define MC_CLIENT_HOTRESET_STATUS 0x204 | ||
| 288 | #define MC_CLIENT_HOTRESET_STATUS_1 0x974 | ||
| 289 | #define MC_EMEM_ARB_ISOCHRONOUS_0 0x208 | ||
| 290 | #define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c | ||
| 291 | #define MC_EMEM_ARB_ISOCHRONOUS_2 0x210 | ||
| 292 | #define MC_EMEM_ARB_ISOCHRONOUS_3 0x214 | ||
| 293 | #define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94 | ||
| 294 | #define MC_EMEM_ARB_ISOCHRONOUS_5 0xba8 | ||
| 295 | #define MC_EMEM_ARB_ISOCHRONOUS_6 0xaac | ||
| 296 | #define MC_EMEM_ARB_ISOCHRONOUS_7 0xab0 | ||
| 297 | #define MC_EMEM_ARB_HYSTERESIS_0 0x218 | ||
| 298 | #define MC_EMEM_ARB_HYSTERESIS_1 0x21c | ||
| 299 | #define MC_EMEM_ARB_HYSTERESIS_2 0x220 | ||
| 300 | #define MC_EMEM_ARB_HYSTERESIS_3 0x224 | ||
| 301 | #define MC_EMEM_ARB_HYSTERESIS_4 0xb84 | ||
| 302 | #define MC_EMEM_ARB_HYSTERESIS_5 0xba4 | ||
| 303 | #define MC_EMEM_ARB_HYSTERESIS_6 0xef4 | ||
| 304 | #define MC_EMEM_ARB_HYSTERESIS_7 0xef8 | ||
| 305 | #define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0 | ||
| 306 | #define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4 | ||
| 307 | #define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8 | ||
| 308 | #define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc | ||
| 309 | #define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0 | ||
| 310 | #define MC_EMEM_ARB_DHYSTERESIS_5 0xbf0 | ||
| 311 | #define MC_EMEM_ARB_DHYSTERESIS_6 0x1d00 | ||
| 312 | #define MC_EMEM_ARB_DHYSTERESIS_7 0x1d04 | ||
| 313 | #define MC_EMEM_ARB_DHYST_CTRL 0xbcc | ||
| 314 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 | ||
| 315 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 | ||
| 316 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 | ||
| 317 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc | ||
| 318 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 | ||
| 319 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 | ||
| 320 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 | ||
| 321 | #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec | ||
| 322 | #define MC_RESERVED_RSV 0x3fc | ||
| 323 | #define MC_UFSHCPC2_EXTRA_SNAP_LEVELS 0x4844 | ||
| 324 | #define MC_BPMPPC_EXTRA_SNAP_LEVELS 0xa60 | ||
| 325 | #define MC_PVA1XA3_EXTRA_SNAP_LEVELS 0x4818 | ||
| 326 | #define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc | ||
| 327 | #define MC_MIU4_EXTRA_SNAP_LEVELS 0x4924 | ||
| 328 | #define MC_MIU6_EXTRA_SNAP_LEVELS 0x492c | ||
| 329 | #define MC_VICPC3_EXTRA_SNAP_LEVELS 0xa80 | ||
| 330 | #define MC_ISP2PC_EXTRA_SNAP_LEVELS 0x4910 | ||
| 331 | #define MC_USBD2_EXTRA_SNAP_LEVELS 0x484c | ||
| 332 | #define MC_PVA1XB_EXTRA_SNAP_LEVELS 0x481c | ||
| 333 | #define MC_PVA0XB3_EXTRA_SNAP_LEVELS 0x4810 | ||
| 334 | #define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c | ||
| 335 | #define MC_UFSHCPC_EXTRA_SNAP_LEVELS 0xa58 | ||
| 336 | #define MC_MSEA_EXTRA_SNAP_LEVELS 0x4900 | ||
| 337 | #define MC_USBX_EXTRA_SNAP_LEVELS 0x404 | ||
| 338 | #define MC_PCIE4XA_EXTRA_SNAP_LEVELS 0x4800 | ||
| 339 | #define MC_MSE2_EXTRA_SNAP_LEVELS 0xe08 | ||
| 340 | #define MC_PVA0XA3_EXTRA_SNAP_LEVELS 0x4808 | ||
| 341 | #define MC_PCIE4X_EXTRA_SNAP_LEVELS 0x4104 | ||
| 342 | #define MC_DLA1XA2_EXTRA_SNAP_LEVELS 0x482c | ||
| 343 | #define MC_MIU3_EXTRA_SNAP_LEVELS 0x3260 | ||
| 344 | #define MC_NVD2_EXTRA_SNAP_LEVELS 0xe00 | ||
| 345 | #define MC_USBD_EXTRA_SNAP_LEVELS 0xa18 | ||
| 346 | #define MC_PVA0XB2_EXTRA_SNAP_LEVELS 0x4834 | ||
| 347 | #define MC_RCEPC_EXTRA_SNAP_LEVELS 0xe20 | ||
| 348 | #define MC_MSE_EXTRA_SNAP_LEVELS 0x40c | ||
| 349 | #define MC_AUD_EXTRA_SNAP_LEVELS 0xa10 | ||
| 350 | #define MC_DLA0XA_EXTRA_SNAP_LEVELS 0xe10 | ||
| 351 | #define MC_PCIE0X2_EXTRA_SNAP_LEVELS 0x4914 | ||
| 352 | #define MC_DLA0XA2_EXTRA_SNAP_LEVELS 0x4828 | ||
| 353 | #define MC_PCIE0XA_EXTRA_SNAP_LEVELS 0x4118 | ||
| 354 | #define MC_PCIE1X_EXTRA_SNAP_LEVELS 0x3270 | ||
| 355 | #define MC_EQOSPC_EXTRA_SNAP_LEVELS 0xa5c | ||
| 356 | #define MC_MIU7_EXTRA_SNAP_LEVELS 0x4930 | ||
| 357 | #define MC_MIU1_EXTRA_SNAP_LEVELS 0x3258 | ||
| 358 | #define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48 | ||
| 359 | #define MC_DLA0FALPC_EXTRA_SNAP_LEVELS 0x3264 | ||
| 360 | #define MC_PVA1XB2_EXTRA_SNAP_LEVELS 0x483c | ||
| 361 | #define MC_PVA1XA_EXTRA_SNAP_LEVELS 0xe1c | ||
| 362 | #define MC_AONPC_EXTRA_SNAP_LEVELS 0xa68 | ||
| 363 | #define MC_SD_EXTRA_SNAP_LEVELS 0xa04 | ||
| 364 | #define MC_VE_EXTRA_SNAP_LEVELS 0x2d8 | ||
| 365 | #define MC_SCEPC_EXTRA_SNAP_LEVELS 0xa70 | ||
| 366 | #define MC_HOST_EXTRA_SNAP_LEVELS 0xa14 | ||
| 367 | #define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c | ||
| 368 | #define MC_DLA0XA3_EXTRA_SNAP_LEVELS 0x4110 | ||
| 369 | #define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac | ||
| 370 | #define MC_DLA1XA_EXTRA_SNAP_LEVELS 0xe14 | ||
| 371 | #define MC_PCIE0X_EXTRA_SNAP_LEVELS 0x326c | ||
| 372 | #define MC_PCIE5X_EXTRA_SNAP_LEVELS 0x4108 | ||
| 373 | #define MC_PVA0XC_EXTRA_SNAP_LEVELS 0x4814 | ||
| 374 | #define MC_MSE3_EXTRA_SNAP_LEVELS 0x3250 | ||
| 375 | #define MC_USBX2_EXTRA_SNAP_LEVELS 0x4848 | ||
| 376 | #define MC_PVA0XA_EXTRA_SNAP_LEVELS 0xe18 | ||
| 377 | #define MC_DLA1FALPC_EXTRA_SNAP_LEVELS 0x3268 | ||
| 378 | #define MC_DLA1XA3_EXTRA_SNAP_LEVELS 0x4114 | ||
| 379 | #define MC_PCIE5XA_EXTRA_SNAP_LEVELS 0x4804 | ||
| 380 | #define MC_MIU5_EXTRA_SNAP_LEVELS 0x4928 | ||
| 381 | #define MC_VICPC2_EXTRA_SNAP_LEVELS 0xa7c | ||
| 382 | #define MC_ISPPC_EXTRA_SNAP_LEVELS 0x490c | ||
| 383 | #define MC_PCIE1XA_EXTRA_SNAP_LEVELS 0x411c | ||
| 384 | #define MC_NVD6_EXTRA_SNAP_LEVELS 0x4920 | ||
| 385 | #define MC_SDM_EXTRA_SNAP_LEVELS 0xa44 | ||
| 386 | #define MC_APB_EXTRA_SNAP_LEVELS 0x2a4 | ||
| 387 | #define MC_ISP_EXTRA_SNAP_LEVELS 0xa08 | ||
| 388 | #define MC_MIU0_EXTRA_SNAP_LEVELS 0x3254 | ||
| 389 | #define MC_PCIE5X2_EXTRA_SNAP_LEVELS 0x4840 | ||
| 390 | #define MC_NIC_EXTRA_SNAP_LEVELS 0xa54 | ||
| 391 | #define MC_MIU2_EXTRA_SNAP_LEVELS 0x325c | ||
| 392 | #define MC_PVA0XB_EXTRA_SNAP_LEVELS 0x480c | ||
| 393 | #define MC_PVA1XB3_EXTRA_SNAP_LEVELS 0x4820 | ||
| 394 | #define MC_NVD3_EXTRA_SNAP_LEVELS 0xe04 | ||
| 395 | #define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0 | ||
| 396 | #define MC_MSEB1_EXTRA_SNAP_LEVELS 0x4908 | ||
| 397 | #define MC_MSEB_EXTRA_SNAP_LEVELS 0x4904 | ||
| 398 | #define MC_NVD4_EXTRA_SNAP_LEVELS 0x4918 | ||
| 399 | #define MC_PVA1XC_EXTRA_SNAP_LEVELS 0x4824 | ||
| 400 | #define MC_NVD_EXTRA_SNAP_LEVELS 0xa38 | ||
| 401 | #define MC_PVA1XA2_EXTRA_SNAP_LEVELS 0x4838 | ||
| 402 | #define MC_PVA0XA2_EXTRA_SNAP_LEVELS 0x4830 | ||
| 403 | #define MC_NVD5_EXTRA_SNAP_LEVELS 0x491c | ||
| 404 | #define MC_DIS2_EXTRA_SNAP_LEVELS 0xa84 | ||
| 405 | #define MC_VIDEO_PROTECT_BOM 0x648 | ||
| 406 | #define MC_VIDEO_PROTECT_SIZE_MB 0x64c | ||
| 407 | #define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978 | ||
| 408 | #define MC_VIDEO_PROTECT_REG_CTRL 0x650 | ||
| 409 | #define MC_ERR_VPR_STATUS 0x654 | ||
| 410 | #define MC_ERR_VPR_ADR 0x658 | ||
| 411 | #define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418 | ||
| 412 | #define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590 | ||
| 413 | #define MC_VIDEO_PROTECT_VPR_OVERRIDE2 0x594 | ||
| 414 | #define MC_EMEM_CFG_ACCESS_CTRL 0x664 | ||
| 415 | #define MC_TZ_SECURITY_CTRL 0x668 | ||
| 416 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS2 0x1988 | ||
| 417 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS6 0x1998 | ||
| 418 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS3 0x198c | ||
| 419 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS5 0x1994 | ||
| 420 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS0 0x1980 | ||
| 421 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS4 0x1990 | ||
| 422 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS1 0x1984 | ||
| 423 | #define MC_TZ_CARVEOUT_CLIENT_ACCESS7 0x199c | ||
| 424 | #define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c | ||
| 425 | #define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4 | ||
| 426 | #define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc | ||
| 427 | #define MC_EMEM_ARB_NISO_THROTTLE_MASK_3 0x3b00 | ||
| 428 | #define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8 | ||
| 429 | #define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80 | ||
| 430 | #define MC_EMEM_ARB_NISO_THROTTLE_MASK_2 0x3200 | ||
| 431 | #define MC_SEC_CARVEOUT_BOM 0x670 | ||
| 432 | #define MC_SEC_CARVEOUT_SIZE_MB 0x674 | ||
| 433 | #define MC_SEC_CARVEOUT_ADR_HI 0x9d4 | ||
| 434 | #define MC_SEC_CARVEOUT_REG_CTRL 0x678 | ||
| 435 | #define MC_ERR_SEC_STATUS 0x67c | ||
| 436 | #define MC_ERR_SEC_ADR 0x680 | ||
| 437 | #define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684 | ||
| 438 | #define MC_STUTTER_CONTROL 0x688 | ||
| 439 | #define MC_RESERVED_RSV_1 0x958 | ||
| 440 | #define MC_DVFS_PIPE_SELECT 0x95c | ||
| 441 | #define MC_SCEPC_PTSA_MIN 0x790 | ||
| 442 | #define MC_AUD_PTSA_MIN 0x54c | ||
| 443 | #define MC_MLL_MPCORER_PTSA_RATE 0x44c | ||
| 444 | #define MC_RING2_PTSA_RATE 0x440 | ||
| 445 | #define MC_USBD_PTSA_RATE 0x530 | ||
| 446 | #define MC_PCIE5X_PTSA_MAX 0x3350 | ||
| 447 | #define MC_ISPPC_PTSA_MIN 0x3a70 | ||
| 448 | #define MC_JPG_PTSA_RATE 0x584 | ||
| 449 | #define MC_APB_PTSA_MAX 0x4f0 | ||
| 450 | #define MC_PVA1XC_PTSA_RATE 0x3924 | ||
| 451 | #define MC_MIU7_PTSA_MAX 0x4b68 | ||
| 452 | #define MC_PVA0XB_PTSA_MIN 0x3558 | ||
| 453 | #define MC_DIS_PTSA_MIN 0x420 | ||
| 454 | #define MC_NVD2_PTSA_MIN 0x3a1c | ||
| 455 | #define MC_SD_PTSA_MAX 0x4d8 | ||
| 456 | #define MC_MSE_PTSA_RATE 0x4c4 | ||
| 457 | #define MC_MSE3_PTSA_MIN 0x3134 | ||
| 458 | #define MC_DLA0XA_PTSA_MIN 0x7e4 | ||
| 459 | #define MC_ISP_PTSA_RATE 0x4a0 | ||
| 460 | #define MC_MIU6_PTSA_MAX 0x4b5c | ||
| 461 | #define MC_UFSHCPC2_PTSA_RATE 0x3a24 | ||
| 462 | #define MC_PCIE5X2_PTSA_RATE 0x3a00 | ||
| 463 | #define MC_PVA0XB2_PTSA_MIN 0x3958 | ||
| 464 | #define MC_HOST_PTSA_MIN 0x51c | ||
| 465 | #define MC_DLA1XA3_PTSA_MIN 0x3370 | ||
| 466 | #define MC_MLL_MPCORER_PTSA_MAX 0x454 | ||
| 467 | #define MC_SD_PTSA_MIN 0x4d4 | ||
| 468 | #define MC_PVA1XB2_PTSA_MAX 0x3974 | ||
| 469 | #define MC_DLA0XA_PTSA_MAX 0x7e8 | ||
| 470 | #define MC_RING1_PTSA_RATE 0x47c | ||
| 471 | #define MC_NVD2_PTSA_RATE 0x3a18 | ||
| 472 | #define MC_PVA1XC_PTSA_MAX 0x392c | ||
| 473 | #define MC_DLA1FALPC_PTSA_MIN 0x3304 | ||
| 474 | #define MC_PCIE1XA_PTSA_MIN 0x3510 | ||
| 475 | #define MC_MIU1_PTSA_MAX 0x3150 | ||
| 476 | #define MC_MIU0_PTSA_RATE 0x313c | ||
| 477 | #define MC_JPG_PTSA_MAX 0x58c | ||
| 478 | #define MC_UFSHCPC_PTSA_MAX 0x74c | ||
| 479 | #define MC_NVD5_PTSA_MAX 0x4b2c | ||
| 480 | #define MC_VICPC2_PTSA_MIN 0x3a10 | ||
| 481 | #define MC_VICPC_PTSA_MAX 0x55c | ||
| 482 | #define MC_DLA1FALPC_PTSA_MAX 0x3308 | ||
| 483 | #define MC_NVD2_PTSA_MAX 0x3a20 | ||
| 484 | #define MC_NVD_PTSA_RATE 0x578 | ||
| 485 | #define MC_MIU1_PTSA_RATE 0x3148 | ||
| 486 | #define MC_SCEPC_PTSA_RATE 0x78c | ||
| 487 | #define MC_MIU3_PTSA_MIN 0x3164 | ||
| 488 | #define MC_EQOSPC_PTSA_MIN 0x754 | ||
| 489 | #define MC_PVA1XB3_PTSA_MAX 0x3920 | ||
| 490 | #define MC_PVA0XA2_PTSA_RATE 0x3948 | ||
| 491 | #define MC_EQOSPC_PTSA_RATE 0x750 | ||
| 492 | #define MC_USBX2_PTSA_MAX 0x3a38 | ||
| 493 | #define MC_VICPC3_PTSA_MIN 0x7b4 | ||
| 494 | #define MC_MLL_MPCORER_PTSA_MIN 0x450 | ||
| 495 | #define MC_ISP_PTSA_MAX 0x4a8 | ||
| 496 | #define MC_PCIE4XA_PTSA_MAX 0x3538 | ||
| 497 | #define MC_UFSHCPC_PTSA_MIN 0x748 | ||
| 498 | #define MC_PVA0XC_PTSA_MIN 0x3570 | ||
| 499 | #define MC_FTOP_PTSA_RATE 0x50c | ||
| 500 | #define MC_VICPC2_PTSA_MAX 0x3a14 | ||
| 501 | #define MC_PCIE4XA_PTSA_RATE 0x3530 | ||
| 502 | #define MC_DLA0XA2_PTSA_RATE 0x3930 | ||
| 503 | #define MC_NVD3_PTSA_MIN 0x7c0 | ||
| 504 | #define MC_PCIE5X2_PTSA_MIN 0x3a04 | ||
| 505 | #define MC_DLA0FALPC_PTSA_MAX 0x3174 | ||
| 506 | #define MC_MIU0_PTSA_MIN 0x3140 | ||
| 507 | #define MC_MIU2_PTSA_MAX 0x315c | ||
| 508 | #define MC_ISP2PC_PTSA_MIN 0x4b04 | ||
| 509 | #define MC_USBX_PTSA_MAX 0x52c | ||
| 510 | #define MC_USBD_PTSA_MAX 0x538 | ||
| 511 | #define MC_MIU5_PTSA_MIN 0x4b4c | ||
| 512 | #define MC_USBX_PTSA_RATE 0x524 | ||
| 513 | #define MC_PCIE0X_PTSA_MAX 0x3314 | ||
| 514 | #define MC_MSEA_PTSA_MIN 0x3a4c | ||
| 515 | #define MC_FTOP_PTSA_MAX 0x514 | ||
| 516 | #define MC_PVA0XA3_PTSA_MAX 0x3550 | ||
| 517 | #define MC_ISP2PC_PTSA_MAX 0x4b08 | ||
| 518 | #define MC_HDAPC_PTSA_MAX 0x630 | ||
| 519 | #define MC_SD_PTSA_RATE 0x4d0 | ||
| 520 | #define MC_MSEA_PTSA_MAX 0x3a50 | ||
| 521 | #define MC_PCIE1X_PTSA_MAX 0x3320 | ||
| 522 | #define MC_PCIE0X2_PTSA_MAX 0x4b14 | ||
| 523 | #define MC_PCIE5XA_PTSA_RATE 0x353c | ||
| 524 | #define MC_PVA0XA_PTSA_MIN 0x3104 | ||
| 525 | #define MC_FTOP_PTSA_MIN 0x510 | ||
| 526 | #define MC_DLA1XA3_PTSA_RATE 0x336c | ||
| 527 | #define MC_BPMPPC_PTSA_MAX 0x764 | ||
| 528 | #define MC_MSE_PTSA_MIN 0x4c8 | ||
| 529 | #define MC_PCIE0X2_PTSA_MIN 0x4b10 | ||
| 530 | #define MC_PVA0XB3_PTSA_RATE 0x3560 | ||
| 531 | #define MC_PVA0XA_PTSA_RATE 0x3100 | ||
| 532 | #define MC_NVD5_PTSA_MIN 0x4b28 | ||
| 533 | #define MC_VE_PTSA_RATE 0x434 | ||
| 534 | #define MC_DLA1XA2_PTSA_RATE 0x393c | ||
| 535 | #define MC_AONPC_PTSA_RATE 0x774 | ||
| 536 | #define MC_DLA0FALPC_PTSA_MIN 0x3170 | ||
| 537 | #define MC_MIU4_PTSA_RATE 0x4b3c | ||
| 538 | #define MC_MIU4_PTSA_MAX 0x4b44 | ||
| 539 | #define MC_SAX_PTSA_MIN 0x4bc | ||
| 540 | #define MC_PVA0XB2_PTSA_MAX 0x395c | ||
| 541 | #define MC_PVA0XA3_PTSA_MIN 0x354c | ||
| 542 | #define MC_ISP_PTSA_MIN 0x4a4 | ||
| 543 | #define MC_HOST_PTSA_MAX 0x520 | ||
| 544 | #define MC_BPMPPC_PTSA_MIN 0x760 | ||
| 545 | #define MC_PCIE1X_PTSA_RATE 0x3318 | ||
| 546 | #define MC_NVD6_PTSA_RATE 0x4b30 | ||
| 547 | #define MC_DLA0XA2_PTSA_MIN 0x3934 | ||
| 548 | #define MC_ISP2PC_PTSA_RATE 0x4b00 | ||
| 549 | #define MC_PVA0XB3_PTSA_MIN 0x3564 | ||
| 550 | #define MC_MSE3_PTSA_MAX 0x3138 | ||
| 551 | #define MC_NVD5_PTSA_RATE 0x4b24 | ||
| 552 | #define MC_MSEB1_PTSA_MIN 0x3a64 | ||
| 553 | #define MC_PVA0XB2_PTSA_RATE 0x3954 | ||
| 554 | #define MC_EQOSPC_PTSA_MAX 0x758 | ||
| 555 | #define MC_MSEB_PTSA_RATE 0x3a54 | ||
| 556 | #define MC_USBX_PTSA_MIN 0x528 | ||
| 557 | #define MC_PCIE4X_PTSA_RATE 0x333c | ||
| 558 | #define MC_USBD_PTSA_MIN 0x534 | ||
| 559 | #define MC_PCIE5X_PTSA_MIN 0x334c | ||
| 560 | #define MC_MIU3_PTSA_MAX 0x3168 | ||
| 561 | #define MC_DLA1FALPC_PTSA_RATE 0x3300 | ||
| 562 | #define MC_PVA1XB3_PTSA_RATE 0x3918 | ||
| 563 | #define MC_DLA1XA3_PTSA_MAX 0x3374 | ||
| 564 | #define MC_MIU1_PTSA_MIN 0x314c | ||
| 565 | #define MC_PCIE5XA_PTSA_MAX 0x3544 | ||
| 566 | #define MC_DLA0XA3_PTSA_MIN 0x3364 | ||
| 567 | #define MC_DIS_PTSA_MAX 0x424 | ||
| 568 | #define MC_RING1_PTSA_MIN 0x480 | ||
| 569 | #define MC_UFSHCPC2_PTSA_MAX 0x3a2c | ||
| 570 | #define MC_VICPC_PTSA_MIN 0x558 | ||
| 571 | #define MC_MSEB_PTSA_MAX 0x3a5c | ||
| 572 | #define MC_PVA0XB_PTSA_MAX 0x355c | ||
| 573 | #define MC_USBX2_PTSA_MIN 0x3a34 | ||
| 574 | #define MC_RING2_PTSA_MAX 0x448 | ||
| 575 | #define MC_AUD_PTSA_RATE 0x548 | ||
| 576 | #define MC_PCIE0XA_PTSA_MIN 0x3504 | ||
| 577 | #define MC_PCIE0XA_PTSA_RATE 0x3500 | ||
| 578 | #define MC_DLA1XA2_PTSA_MIN 0x3940 | ||
| 579 | #define MC_PVA1XB2_PTSA_RATE 0x396c | ||
| 580 | #define MC_RCEPC_PTSA_MIN 0x311c | ||
| 581 | #define MC_PVA1XA_PTSA_MIN 0x3110 | ||
| 582 | #define MC_DLA0XA3_PTSA_RATE 0x3360 | ||
| 583 | #define MC_NIC_PTSA_MAX 0x740 | ||
| 584 | #define MC_NVD_PTSA_MAX 0x580 | ||
| 585 | #define MC_MIU6_PTSA_MIN 0x4b58 | ||
| 586 | #define MC_PCIE0X_PTSA_RATE 0x330c | ||
| 587 | #define MC_AONPC_PTSA_MAX 0x77c | ||
| 588 | #define MC_JPG_PTSA_MIN 0x588 | ||
| 589 | #define MC_UFSHCPC2_PTSA_MIN 0x3a28 | ||
| 590 | #define MC_HDAPC_PTSA_MIN 0x62c | ||
| 591 | #define MC_DLA1XA_PTSA_MAX 0x7f4 | ||
| 592 | #define MC_MSE2_PTSA_MAX 0x7d0 | ||
| 593 | #define MC_NVD4_PTSA_MAX 0x4b20 | ||
| 594 | #define MC_PVA1XA_PTSA_MAX 0x3114 | ||
| 595 | #define MC_VE_PTSA_MAX 0x43c | ||
| 596 | #define MC_DLA0XA2_PTSA_MAX 0x3938 | ||
| 597 | #define MC_PVA0XB_PTSA_RATE 0x3554 | ||
| 598 | #define MC_MSEB1_PTSA_RATE 0x3a60 | ||
| 599 | #define MC_PVA0XC_PTSA_MAX 0x3574 | ||
| 600 | #define MC_VICPC_PTSA_RATE 0x554 | ||
| 601 | #define MC_BPMPPC_PTSA_RATE 0x75c | ||
| 602 | #define MC_ISPPC_PTSA_MAX 0x3a74 | ||
| 603 | #define MC_SCEPC_PTSA_MAX 0x794 | ||
| 604 | #define MC_DLA0XA_PTSA_RATE 0x7e0 | ||
| 605 | #define MC_DLA0XA3_PTSA_MAX 0x3368 | ||
| 606 | #define MC_MIU7_PTSA_RATE 0x4b60 | ||
| 607 | #define MC_PCIE4X_PTSA_MIN 0x3340 | ||
| 608 | #define MC_PCIE5X_PTSA_RATE 0x3348 | ||
| 609 | #define MC_SDM_PTSA_MAX 0x624 | ||
| 610 | #define MC_VICPC2_PTSA_RATE 0x3a0c | ||
| 611 | #define MC_PCIE5XA_PTSA_MIN 0x3540 | ||
| 612 | #define MC_NVD4_PTSA_RATE 0x4b18 | ||
| 613 | #define MC_PVA0XA_PTSA_MAX 0x3108 | ||
| 614 | #define MC_MSE2_PTSA_MIN 0x7cc | ||
| 615 | #define MC_USBD2_PTSA_MAX 0x3a44 | ||
| 616 | #define MC_SAX_PTSA_RATE 0x4b8 | ||
| 617 | #define MC_APB_PTSA_MIN 0x4ec | ||
| 618 | #define MC_ISPPC_PTSA_RATE 0x3a6c | ||
| 619 | #define MC_PVA1XA2_PTSA_RATE 0x3960 | ||
| 620 | #define MC_PCIE5X2_PTSA_MAX 0x3a08 | ||
| 621 | #define MC_PCIE4XA_PTSA_MIN 0x3534 | ||
| 622 | #define MC_RCEPC_PTSA_MAX 0x3120 | ||
| 623 | #define MC_PVA0XA3_PTSA_RATE 0x3548 | ||
| 624 | #define MC_AONPC_PTSA_MIN 0x778 | ||
| 625 | #define MC_PCIE0X2_PTSA_RATE 0x4b0c | ||
| 626 | #define MC_MSE3_PTSA_RATE 0x3130 | ||
| 627 | #define MC_RCEPC_PTSA_RATE 0x3118 | ||
| 628 | #define MC_RING1_PTSA_MAX 0x484 | ||
| 629 | #define MC_HDAPC_PTSA_RATE 0x628 | ||
| 630 | #define MC_MIU0_PTSA_MAX 0x3144 | ||
| 631 | #define MC_PVA1XB2_PTSA_MIN 0x3970 | ||
| 632 | #define MC_VICPC3_PTSA_RATE 0x7b0 | ||
| 633 | #define MC_AUD_PTSA_MAX 0x550 | ||
| 634 | #define MC_MIU2_PTSA_MIN 0x3158 | ||
| 635 | #define MC_NVD3_PTSA_MAX 0x7c4 | ||
| 636 | #define MC_MIU6_PTSA_RATE 0x4b54 | ||
| 637 | #define MC_NVD_PTSA_MIN 0x57c | ||
| 638 | #define MC_PVA0XA2_PTSA_MIN 0x394c | ||
| 639 | #define MC_VICPC3_PTSA_MAX 0x7b8 | ||
| 640 | #define MC_PVA1XA2_PTSA_MIN 0x3964 | ||
| 641 | #define MC_PVA0XB3_PTSA_MAX 0x3568 | ||
| 642 | #define MC_PVA1XA3_PTSA_RATE 0x3900 | ||
| 643 | #define MC_PCIE0X_PTSA_MIN 0x3310 | ||
| 644 | #define MC_PCIE1XA_PTSA_RATE 0x350c | ||
| 645 | #define MC_DIS_PTSA_RATE 0x41c | ||
| 646 | #define MC_USBX2_PTSA_RATE 0x3a30 | ||
| 647 | #define MC_DLA1XA_PTSA_MIN 0x7f0 | ||
| 648 | #define MC_PVA1XA3_PTSA_MAX 0x3908 | ||
| 649 | #define MC_PVA1XB_PTSA_RATE 0x390c | ||
| 650 | #define MC_DLA1XA2_PTSA_MAX 0x3944 | ||
| 651 | #define MC_MSEA_PTSA_RATE 0x3a48 | ||
| 652 | #define MC_MIU2_PTSA_RATE 0x3154 | ||
| 653 | #define MC_NVD6_PTSA_MAX 0x4b38 | ||
| 654 | #define MC_PCIE1XA_PTSA_MAX 0x3514 | ||
| 655 | #define MC_MIU3_PTSA_RATE 0x3160 | ||
| 656 | #define MC_MIU5_PTSA_MAX 0x4b50 | ||
| 657 | #define MC_SDM_PTSA_RATE 0x61c | ||
| 658 | #define MC_SDM_PTSA_MIN 0x620 | ||
| 659 | #define MC_APB_PTSA_RATE 0x4e8 | ||
| 660 | #define MC_RING2_PTSA_MIN 0x444 | ||
| 661 | #define MC_UFSHCPC_PTSA_RATE 0x744 | ||
| 662 | #define MC_PVA0XC_PTSA_RATE 0x356c | ||
| 663 | #define MC_MSE2_PTSA_RATE 0x7c8 | ||
| 664 | #define MC_PCIE0XA_PTSA_MAX 0x3508 | ||
| 665 | #define MC_MSEB_PTSA_MIN 0x3a58 | ||
| 666 | #define MC_PVA1XB_PTSA_MAX 0x3914 | ||
| 667 | #define MC_HOST_PTSA_RATE 0x518 | ||
| 668 | #define MC_NVD3_PTSA_RATE 0x7bc | ||
| 669 | #define MC_NVD6_PTSA_MIN 0x4b34 | ||
| 670 | #define MC_MIU5_PTSA_RATE 0x4b48 | ||
| 671 | #define MC_PVA1XB_PTSA_MIN 0x3910 | ||
| 672 | #define MC_PVA1XA_PTSA_RATE 0x310c | ||
| 673 | #define MC_MIU4_PTSA_MIN 0x4b40 | ||
| 674 | #define MC_NIC_PTSA_RATE 0x738 | ||
| 675 | #define MC_PVA1XB3_PTSA_MIN 0x391c | ||
| 676 | #define MC_NVD4_PTSA_MIN 0x4b1c | ||
| 677 | #define MC_SAX_PTSA_MAX 0x4c0 | ||
| 678 | #define MC_MIU7_PTSA_MIN 0x4b64 | ||
| 679 | #define MC_PVA1XA3_PTSA_MIN 0x3904 | ||
| 680 | #define MC_VE_PTSA_MIN 0x438 | ||
| 681 | #define MC_USBD2_PTSA_RATE 0x3a3c | ||
| 682 | #define MC_DLA1XA_PTSA_RATE 0x7ec | ||
| 683 | #define MC_PVA0XA2_PTSA_MAX 0x3950 | ||
| 684 | #define MC_DLA0FALPC_PTSA_RATE 0x316c | ||
| 685 | #define MC_MSE_PTSA_MAX 0x4cc | ||
| 686 | #define MC_PCIE4X_PTSA_MAX 0x3344 | ||
| 687 | #define MC_MSEB1_PTSA_MAX 0x3a68 | ||
| 688 | #define MC_USBD2_PTSA_MIN 0x3a40 | ||
| 689 | #define MC_PVA1XA2_PTSA_MAX 0x3968 | ||
| 690 | #define MC_PCIE1X_PTSA_MIN 0x331c | ||
| 691 | #define MC_NIC_PTSA_MIN 0x73c | ||
| 692 | #define MC_PVA1XC_PTSA_MIN 0x3928 | ||
| 693 | #define MC_PTSA_GRANT_DECREMENT 0x960 | ||
| 694 | #define MC_LATENCY_ALLOWANCE_AON_0 0x714 | ||
| 695 | #define MC_LATENCY_ALLOWANCE_NVENC_1 0x1050 | ||
| 696 | #define MC_LATENCY_ALLOWANCE_BPMP_0 0x70c | ||
| 697 | #define MC_LATENCY_ALLOWANCE_MIU0_0 0x1054 | ||
| 698 | #define MC_LATENCY_ALLOWANCE_NVDEC_1 0x72c | ||
| 699 | #define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 | ||
| 700 | #define MC_LATENCY_ALLOWANCE_NVENC_2 0x1a28 | ||
| 701 | #define MC_LATENCY_ALLOWANCE_SE_0 0x3e0 | ||
| 702 | #define MC_LATENCY_ALLOWANCE_PCIE2_0 0x1a04 | ||
| 703 | #define MC_LATENCY_ALLOWANCE_PCIE1_0 0x1a00 | ||
| 704 | #define MC_LATENCY_ALLOWANCE_DLA1_0 0x1028 | ||
| 705 | #define MC_LATENCY_ALLOWANCE_APEDMA_0 0x724 | ||
| 706 | #define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 | ||
| 707 | #define MC_LATENCY_ALLOWANCE_ISP3_0 0x1a14 | ||
| 708 | #define MC_LATENCY_ALLOWANCE_MIU2_0 0x105c | ||
| 709 | #define MC_LATENCY_ALLOWANCE_MIU5_0 0x1a38 | ||
| 710 | #define MC_LATENCY_ALLOWANCE_DLA0_2 0x1a18 | ||
| 711 | #define MC_LATENCY_ALLOWANCE_PCIE0_0 0x1064 | ||
| 712 | #define MC_LATENCY_ALLOWANCE_PVA0_2 0x1038 | ||
| 713 | #define MC_LATENCY_ALLOWANCE_MIU3_0 0x1060 | ||
| 714 | #define MC_LATENCY_ALLOWANCE_MIU1_0 0x1058 | ||
| 715 | #define MC_LATENCY_ALLOWANCE_DLA1_1 0x102c | ||
| 716 | #define MC_LATENCY_ALLOWANCE_PVA1_0 0x103c | ||
| 717 | #define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 | ||
| 718 | #define MC_LATENCY_ALLOWANCE_DLA0_1 0x1024 | ||
| 719 | #define MC_LATENCY_ALLOWANCE_DLA0_0 0x1020 | ||
| 720 | #define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4 | ||
| 721 | #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 | ||
| 722 | #define MC_LATENCY_ALLOWANCE_VI2_0 0x398 | ||
| 723 | #define MC_LATENCY_ALLOWANCE_MIU7_0 0x1a40 | ||
| 724 | #define MC_LATENCY_ALLOWANCE_SCEDMA_0 0x720 | ||
| 725 | #define MC_LATENCY_ALLOWANCE_PVA1_1 0x1040 | ||
| 726 | #define MC_LATENCY_ALLOWANCE_SATA_0 0x350 | ||
| 727 | #define MC_LATENCY_ALLOWANCE_AONDMA_0 0x718 | ||
| 728 | #define MC_LATENCY_ALLOWANCE_HC_0 0x310 | ||
| 729 | #define MC_LATENCY_ALLOWANCE_UFSHC_0 0x704 | ||
| 730 | #define MC_LATENCY_ALLOWANCE_NVDEC_2 0x1a30 | ||
| 731 | #define MC_LATENCY_ALLOWANCE_VIC_1 0x728 | ||
| 732 | #define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 | ||
| 733 | #define MC_LATENCY_ALLOWANCE_RCEDMA_0 0x104c | ||
| 734 | #define MC_LATENCY_ALLOWANCE_HDA_0 0x318 | ||
| 735 | #define MC_LATENCY_ALLOWANCE_BPMPDMA_0 0x710 | ||
| 736 | #define MC_LATENCY_ALLOWANCE_PCIE3_0 0x1a08 | ||
| 737 | #define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0 | ||
| 738 | #define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 | ||
| 739 | #define MC_LATENCY_ALLOWANCE_PVA0_3 0x1a1c | ||
| 740 | #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 | ||
| 741 | #define MC_LATENCY_ALLOWANCE_NVDISPLAY_0 0x708 | ||
| 742 | #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 | ||
| 743 | #define MC_LATENCY_ALLOWANCE_PVA1_3 0x1a20 | ||
| 744 | #define MC_LATENCY_ALLOWANCE_VIC_0 0x394 | ||
| 745 | #define MC_LATENCY_ALLOWANCE_PCIE4_0 0x1a0c | ||
| 746 | #define MC_LATENCY_ALLOWANCE_PVA1_2 0x1044 | ||
| 747 | #define MC_LATENCY_ALLOWANCE_EQOS_0 0x700 | ||
| 748 | #define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 | ||
| 749 | #define MC_LATENCY_ALLOWANCE_VIFAL_0 0x101c | ||
| 750 | #define MC_LATENCY_ALLOWANCE_PVA0_1 0x1034 | ||
| 751 | #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c | ||
| 752 | #define MC_LATENCY_ALLOWANCE_MIU4_0 0x1a34 | ||
| 753 | #define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0 | ||
| 754 | #define MC_LATENCY_ALLOWANCE_SCE_0 0x71c | ||
| 755 | #define MC_LATENCY_ALLOWANCE_APE_0 0x3dc | ||
| 756 | #define MC_LATENCY_ALLOWANCE_RCE_0 0x1048 | ||
| 757 | #define MC_LATENCY_ALLOWANCE_PVA0_0 0x1030 | ||
| 758 | #define MC_LATENCY_ALLOWANCE_PTC_0 0x34c | ||
| 759 | #define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec | ||
| 760 | #define MC_LATENCY_ALLOWANCE_PCIE5_0 0x1a10 | ||
| 761 | #define MC_LATENCY_ALLOWANCE_AXIS_0 0x3f8 | ||
| 762 | #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 | ||
| 763 | #define MC_LATENCY_ALLOWANCE_MIU6_0 0x1a3c | ||
| 764 | #define MC_LATENCY_ALLOWANCE_PCIE5_1 0x1a24 | ||
| 765 | #define MC_EMEM_ARB_OVERRIDE_1 0x968 | ||
| 766 | #define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984 | ||
| 767 | #define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988 | ||
| 768 | #define MC_EMEM_ARB_STATS_0 0x990 | ||
| 769 | #define MC_EMEM_ARB_STATS_1 0x994 | ||
| 770 | #define MC_MTS_CARVEOUT_BOM 0x9a0 | ||
| 771 | #define MC_MTS_CARVEOUT_SIZE_MB 0x9a4 | ||
| 772 | #define MC_MTS_CARVEOUT_ADR_HI 0x9a8 | ||
| 773 | #define MC_MTS_CARVEOUT_REG_CTRL 0x9ac | ||
| 774 | #define MC_ERR_MTS_STATUS 0x9b0 | ||
| 775 | #define MC_ERR_MTS_ADR 0x9b4 | ||
| 776 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS6 0x1918 | ||
| 777 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS4 0x1910 | ||
| 778 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS1 0x1904 | ||
| 779 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS5 0x1914 | ||
| 780 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS0 0x1900 | ||
| 781 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS7 0x191c | ||
| 782 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS3 0x190c | ||
| 783 | #define MC_MTS_CARVEOUT_CLIENT_ACCESS2 0x1908 | ||
| 784 | #define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 | ||
| 785 | #define MC_ERR_ROUTE_SANITY_ADR 0x9c4 | ||
| 786 | #define MC_IGPU_ACCESSIBLE_CARVEOUT_REG_CTRL 0x9c8 | ||
| 787 | #define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT_REG_CTRL 0x9cc | ||
| 788 | #define MC_IGPU_WPR_ACCESS_CTRL 0x9d8 | ||
| 789 | #define MC_IGPU_ACCESSIBLE_CARVEOUT1_BOM 0x560 | ||
| 790 | #define MC_IGPU_ACCESSIBLE_CARVEOUT1_SIZE 0x564 | ||
| 791 | #define MC_IGPU_ACCESSIBLE_CARVEOUT2_BOM 0x568 | ||
| 792 | #define MC_IGPU_ACCESSIBLE_CARVEOUT2_SIZE 0x56c | ||
| 793 | #define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT1_BOM 0x5a0 | ||
| 794 | #define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT1_SIZE 0x5a4 | ||
| 795 | #define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT2_BOM 0x5a8 | ||
| 796 | #define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT2_SIZE 0x5ac | ||
| 797 | #define MC_ECC_REGION0_SIZE 0x2b0c | ||
| 798 | #define MC_ECC_REGION0_CFG0 0x2b00 | ||
| 799 | #define MC_ECC_REGION3_BOM 0x2b34 | ||
| 800 | #define MC_ECC_REGION2_BOM 0x2b24 | ||
| 801 | #define MC_ECC_REGION1_SIZE 0x2b1c | ||
| 802 | #define MC_ECC_REGION1_BOM 0x2b14 | ||
| 803 | #define MC_ECC_REGION2_CFG0 0x2b20 | ||
| 804 | #define MC_ECC_REGION3_BOM_HI 0x2b38 | ||
| 805 | #define MC_ECC_REGION1_BOM_HI 0x2b18 | ||
| 806 | #define MC_ECC_REGION1_CFG0 0x2b10 | ||
| 807 | #define MC_ECC_REGION0_BOM_HI 0x2b08 | ||
| 808 | #define MC_ECC_REGION2_SIZE 0x2b2c | ||
| 809 | #define MC_ECC_REGION3_CFG0 0x2b30 | ||
| 810 | #define MC_ECC_REGION2_BOM_HI 0x2b28 | ||
| 811 | #define MC_ECC_REGION0_BOM 0x2b04 | ||
| 812 | #define MC_ECC_REGION3_SIZE 0x2b3c | ||
| 813 | #define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1 0xbfc | ||
| 814 | #define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 | ||
| 815 | #define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 | ||
| 816 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd78 | ||
| 817 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS6 0xc48 | ||
| 818 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS5 0xc44 | ||
| 819 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS7 0xca4 | ||
| 820 | #define MC_SECURITY_CARVEOUT4_CFG0 0xcf8 | ||
| 821 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS6 0xd90 | ||
| 822 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10 | ||
| 823 | #define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04 | ||
| 824 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28 | ||
| 825 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc34 | ||
| 826 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc90 | ||
| 827 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd20 | ||
| 828 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd74 | ||
| 829 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS5 0xc2c | ||
| 830 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc30 | ||
| 831 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS7 0xd8c | ||
| 832 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd80 | ||
| 833 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS5 0xccc | ||
| 834 | #define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4 | ||
| 835 | #define MC_SECURITY_CARVEOUT2_CFG0 0xc58 | ||
| 836 | #define MC_SECURITY_CARVEOUT1_CFG0 0xc08 | ||
| 837 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc88 | ||
| 838 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68 | ||
| 839 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS7 0xc4c | ||
| 840 | #define MC_SECURITY_CARVEOUT3_BOM 0xcac | ||
| 841 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70 | ||
| 842 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS5 0xd84 | ||
| 843 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS6 0xd40 | ||
| 844 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd7c | ||
| 845 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc80 | ||
| 846 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18 | ||
| 847 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS6 0xcf0 | ||
| 848 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS6 0xce8 | ||
| 849 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS5 0xd1c | ||
| 850 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc | ||
| 851 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc3c | ||
| 852 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc38 | ||
| 853 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0 | ||
| 854 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60 | ||
| 855 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS6 0xca0 | ||
| 856 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS7 0xc54 | ||
| 857 | #define MC_SECURITY_CARVEOUT3_CFG0 0xca8 | ||
| 858 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8 | ||
| 859 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc8c | ||
| 860 | #define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64 | ||
| 861 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS7 0xcec | ||
| 862 | #define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50 | ||
| 863 | #define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14 | ||
| 864 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14 | ||
| 865 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS7 0xd94 | ||
| 866 | #define MC_SECURITY_CARVEOUT1_BOM 0xc0c | ||
| 867 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS7 0xd3c | ||
| 868 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd30 | ||
| 869 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS7 0xd44 | ||
| 870 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68 | ||
| 871 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS6 0xd38 | ||
| 872 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58 | ||
| 873 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8 | ||
| 874 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS5 0xce4 | ||
| 875 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd28 | ||
| 876 | #define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4 | ||
| 877 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78 | ||
| 878 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS7 0xc9c | ||
| 879 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS7 0xcf4 | ||
| 880 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c | ||
| 881 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS6 0xd88 | ||
| 882 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18 | ||
| 883 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c | ||
| 884 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd2c | ||
| 885 | #define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0 | ||
| 886 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcdc | ||
| 887 | #define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60 | ||
| 888 | #define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00 | ||
| 889 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64 | ||
| 890 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xce0 | ||
| 891 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc84 | ||
| 892 | #define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54 | ||
| 893 | #define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS5 0xc94 | ||
| 894 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd24 | ||
| 895 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd8 | ||
| 896 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c | ||
| 897 | #define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS5 0xd6c | ||
| 898 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74 | ||
| 899 | #define MC_SECURITY_CARVEOUT5_CFG0 0xd48 | ||
| 900 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xcd0 | ||
| 901 | #define MC_SECURITY_CARVEOUT4_BOM 0xcfc | ||
| 902 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS6 0xc50 | ||
| 903 | #define MC_SECURITY_CARVEOUT2_BOM 0xc5c | ||
| 904 | #define MC_SECURITY_CARVEOUT5_BOM 0xd4c | ||
| 905 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24 | ||
| 906 | #define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd70 | ||
| 907 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS5 0xc7c | ||
| 908 | #define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd4 | ||
| 909 | #define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10 | ||
| 910 | #define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS5 0xd34 | ||
| 911 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS6 0xc98 | ||
| 912 | #define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20 | ||
| 913 | #define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc40 | ||
| 914 | #define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 | ||
| 915 | #define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c | ||
| 916 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS1 0x225c | ||
| 917 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS3 0x21c4 | ||
| 918 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS1 0x252c | ||
| 919 | #define MC_SECURITY_CARVEOUT12_CFG0 0x21e0 | ||
| 920 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS7 0x26d4 | ||
| 921 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS5 0x208c | ||
| 922 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS3 0x265c | ||
| 923 | #define MC_SECURITY_CARVEOUT9_BOM_HI 0x20f8 | ||
| 924 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS6 0x24a0 | ||
| 925 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS6 0x2090 | ||
| 926 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS6 0x2770 | ||
| 927 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS2 0x2170 | ||
| 928 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS0 0x2208 | ||
| 929 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS4 0x2678 | ||
| 930 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS0 0x2488 | ||
| 931 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS5 0x24ec | ||
| 932 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS7 0x2184 | ||
| 933 | #define MC_SECURITY_CARVEOUT15_CFG0 0x22d0 | ||
| 934 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS1 0x23d4 | ||
| 935 | #define MC_SECURITY_CARVEOUT7_SIZE_128KB 0x205c | ||
| 936 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS7 0x26dc | ||
| 937 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS2 0x2490 | ||
| 938 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS0 0x2380 | ||
| 939 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS5 0x23ac | ||
| 940 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS4 0x20c0 | ||
| 941 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS2 0x22e8 | ||
| 942 | #define MC_SECURITY_CARVEOUT16_CFG0 0x2320 | ||
| 943 | #define MC_SECURITY_CARVEOUT9_BOM 0x20f4 | ||
| 944 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS3 0x22b4 | ||
| 945 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS5 0x2254 | ||
| 946 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS0 0x2078 | ||
| 947 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS1 0x25cc | ||
| 948 | #define MC_SECURITY_CARVEOUT22_BOM_HI 0x2508 | ||
| 949 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS3 0x2354 | ||
| 950 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS5 0x2484 | ||
| 951 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS3 0x23dc | ||
| 952 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS2 0x2210 | ||
| 953 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS0 0x2438 | ||
| 954 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS6 0x2720 | ||
| 955 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS0 0x2290 | ||
| 956 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS6 0x2138 | ||
| 957 | #define MC_SECURITY_CARVEOUT8_SIZE_128KB 0x20ac | ||
| 958 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS3 0x260c | ||
| 959 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS1 0x25b4 | ||
| 960 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS3 0x2534 | ||
| 961 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS0 0x2668 | ||
| 962 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS2 0x2798 | ||
| 963 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS3 0x206c | ||
| 964 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS2 0x26a8 | ||
| 965 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS3 0x26c4 | ||
| 966 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS4 0x2430 | ||
| 967 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS7 0x218c | ||
| 968 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS4 0x2020 | ||
| 969 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS5 0x2394 | ||
| 970 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS6 0x2180 | ||
| 971 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS5 0x20dc | ||
| 972 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS5 0x23fc | ||
| 973 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS6 0x25e8 | ||
| 974 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS3 0x21ac | ||
| 975 | #define MC_SECURITY_CARVEOUT7_BOM 0x2054 | ||
| 976 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS3 0x2714 | ||
| 977 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS0 0x2060 | ||
| 978 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS3 0x2624 | ||
| 979 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS0 0x20c8 | ||
| 980 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS3 0x24cc | ||
| 981 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS2 0x2300 | ||
| 982 | #define MC_SECURITY_CARVEOUT17_CFG0 0x2370 | ||
| 983 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS5 0x22a4 | ||
| 984 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS4 0x2088 | ||
| 985 | #define MC_SECURITY_CARVEOUT29_SIZE_128KB 0x273c | ||
| 986 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS3 0x274c | ||
| 987 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS3 0x2674 | ||
| 988 | #define MC_SECURITY_CARVEOUT27_CFG0 0x2690 | ||
| 989 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS7 0x263c | ||
| 990 | #define MC_SECURITY_CARVEOUT16_SIZE_128KB 0x232c | ||
| 991 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS6 0x2810 | ||
| 992 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS1 0x207c | ||
| 993 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS7 0x27cc | ||
| 994 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS3 0x22ec | ||
| 995 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS1 0x261c | ||
| 996 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS0 0x25b0 | ||
| 997 | #define MC_SECURITY_CARVEOUT18_BOM 0x23c4 | ||
| 998 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS0 0x2528 | ||
| 999 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS1 0x248c | ||
| 1000 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS6 0x23b8 | ||
| 1001 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS0 0x2510 | ||
| 1002 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS3 0x2214 | ||
| 1003 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS2 0x21a8 | ||
| 1004 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS1 0x2604 | ||
| 1005 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS4 0x2340 | ||
| 1006 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS7 0x2274 | ||
| 1007 | #define MC_SECURITY_CARVEOUT29_CFG0 0x2730 | ||
| 1008 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS0 0x27a8 | ||
| 1009 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS6 0x2048 | ||
| 1010 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS4 0x22b8 | ||
| 1011 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS3 0x21fc | ||
| 1012 | #define MC_SECURITY_CARVEOUT11_CFG0 0x2190 | ||
| 1013 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS3 0x2764 | ||
| 1014 | #define MC_SECURITY_CARVEOUT8_CFG0 0x20a0 | ||
| 1015 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS2 0x2580 | ||
| 1016 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS5 0x2164 | ||
| 1017 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS4 0x2480 | ||
| 1018 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS4 0x2538 | ||
| 1019 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS5 0x2434 | ||
| 1020 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS2 0x2350 | ||
| 1021 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS4 0x24e8 | ||
| 1022 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS5 0x21b4 | ||
| 1023 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS4 0x23e0 | ||
| 1024 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS1 0x2334 | ||
| 1025 | #define MC_SECURITY_CARVEOUT28_BOM 0x26e4 | ||
| 1026 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS6 0x2630 | ||
| 1027 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS1 0x20b4 | ||
| 1028 | #define MC_SECURITY_CARVEOUT15_BOM 0x22d4 | ||
| 1029 | #define MC_SECURITY_CARVEOUT6_BOM 0x2004 | ||
| 1030 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS3 0x26ac | ||
| 1031 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS2 0x26c0 | ||
| 1032 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS3 0x201c | ||
| 1033 | #define MC_SECURITY_CARVEOUT10_BOM 0x2144 | ||
| 1034 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS2 0x2710 | ||
| 1035 | #define MC_SECURITY_CARVEOUT29_BOM_HI 0x2738 | ||
| 1036 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS0 0x2150 | ||
| 1037 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS7 0x2724 | ||
| 1038 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS7 0x2594 | ||
| 1039 | #define MC_SECURITY_CARVEOUT7_BOM_HI 0x2058 | ||
| 1040 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS6 0x2818 | ||
| 1041 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS4 0x2110 | ||
| 1042 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS5 0x2524 | ||
| 1043 | #define MC_SECURITY_CARVEOUT19_SIZE_128KB 0x241c | ||
| 1044 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS6 0x2040 | ||
| 1045 | #define MC_SECURITY_CARVEOUT18_SIZE_128KB 0x23cc | ||
| 1046 | #define MC_SECURITY_CARVEOUT10_CFG0 0x2140 | ||
| 1047 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS1 0x21bc | ||
| 1048 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS0 0x2168 | ||
| 1049 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS4 0x2308 | ||
| 1050 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS6 0x2638 | ||
| 1051 | #define MC_SECURITY_CARVEOUT6_BOM_HI 0x2008 | ||
| 1052 | #define MC_SECURITY_CARVEOUT15_SIZE_128KB 0x22dc | ||
| 1053 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS2 0x2670 | ||
| 1054 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS4 0x24d0 | ||
| 1055 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS2 0x24c8 | ||
| 1056 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS2 0x2478 | ||
| 1057 | #define MC_SECURITY_CARVEOUT19_CFG0 0x2410 | ||
| 1058 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS1 0x2014 | ||
| 1059 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS3 0x25bc | ||
| 1060 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS1 0x21f4 | ||
| 1061 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS2 0x2018 | ||
| 1062 | #define MC_SECURITY_CARVEOUT20_SIZE_128KB 0x246c | ||
| 1063 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS5 0x217c | ||
| 1064 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS1 0x2654 | ||
| 1065 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS0 0x2740 | ||
| 1066 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS1 0x22ac | ||
| 1067 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS3 0x23f4 | ||
| 1068 | #define MC_SECURITY_CARVEOUT27_BOM 0x2694 | ||
| 1069 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS6 0x22c0 | ||
| 1070 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS7 0x2224 | ||
| 1071 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS2 0x21c0 | ||
| 1072 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS7 0x222c | ||
| 1073 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS1 0x26bc | ||
| 1074 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS3 0x20d4 | ||
| 1075 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS1 0x234c | ||
| 1076 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS6 0x2450 | ||
| 1077 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS4 0x2390 | ||
| 1078 | #define MC_SECURITY_CARVEOUT19_BOM_HI 0x2418 | ||
| 1079 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS0 0x27e0 | ||
| 1080 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS4 0x26b0 | ||
| 1081 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS1 0x2794 | ||
| 1082 | #define MC_SECURITY_CARVEOUT11_BOM_HI 0x2198 | ||
| 1083 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS0 0x25c8 | ||
| 1084 | #define MC_SECURITY_CARVEOUT23_BOM 0x2554 | ||
| 1085 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS3 0x247c | ||
| 1086 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS0 0x2028 | ||
| 1087 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS0 0x2240 | ||
| 1088 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS0 0x2618 | ||
| 1089 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS3 0x24e4 | ||
| 1090 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS1 0x202c | ||
| 1091 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS7 0x2544 | ||
| 1092 | #define MC_SECURITY_CARVEOUT21_BOM_HI 0x24b8 | ||
| 1093 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS0 0x23e8 | ||
| 1094 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS4 0x2588 | ||
| 1095 | #define MC_SECURITY_CARVEOUT25_SIZE_128KB 0x25fc | ||
| 1096 | #define MC_SECURITY_CARVEOUT30_CFG0 0x2780 | ||
| 1097 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS7 0x209c | ||
| 1098 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS2 0x2338 | ||
| 1099 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS2 0x2030 | ||
| 1100 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS6 0x22c8 | ||
| 1101 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS0 0x2420 | ||
| 1102 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS4 0x2128 | ||
| 1103 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS5 0x2074 | ||
| 1104 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS5 0x2344 | ||
| 1105 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS1 0x22e4 | ||
| 1106 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS4 0x27f0 | ||
| 1107 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS0 0x22f8 | ||
| 1108 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS0 0x2650 | ||
| 1109 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS7 0x281c | ||
| 1110 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS6 0x23b0 | ||
| 1111 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS4 0x21b0 | ||
| 1112 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS2 0x2260 | ||
| 1113 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS5 0x2754 | ||
| 1114 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS6 0x2188 | ||
| 1115 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS4 0x2160 | ||
| 1116 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS5 0x2114 | ||
| 1117 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS1 0x266c | ||
| 1118 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS0 0x21b8 | ||
| 1119 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS2 0x20b8 | ||
| 1120 | #define MC_SECURITY_CARVEOUT28_BOM_HI 0x26e8 | ||
| 1121 | #define MC_SECURITY_CARVEOUT8_BOM_HI 0x20a8 | ||
| 1122 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS5 0x27f4 | ||
| 1123 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS2 0x2530 | ||
| 1124 | #define MC_SECURITY_CARVEOUT10_BOM_HI 0x2148 | ||
| 1125 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS6 0x2098 | ||
| 1126 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS5 0x24d4 | ||
| 1127 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS7 0x2044 | ||
| 1128 | #define MC_SECURITY_CARVEOUT23_BOM_HI 0x2558 | ||
| 1129 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS2 0x25b8 | ||
| 1130 | #define MC_SECURITY_CARVEOUT26_BOM_HI 0x2648 | ||
| 1131 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS0 0x2010 | ||
| 1132 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS2 0x2440 | ||
| 1133 | #define MC_SECURITY_CARVEOUT30_BOM 0x2784 | ||
| 1134 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS7 0x21dc | ||
| 1135 | #define MC_SECURITY_CARVEOUT18_CFG0 0x23c0 | ||
| 1136 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS7 0x2454 | ||
| 1137 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS5 0x2664 | ||
| 1138 | #define MC_SECURITY_CARVEOUT27_BOM_HI 0x2698 | ||
| 1139 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS1 0x24c4 | ||
| 1140 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS0 0x21f0 | ||
| 1141 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS4 0x23f8 | ||
| 1142 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS5 0x271c | ||
| 1143 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS2 0x22b0 | ||
| 1144 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS0 0x2560 | ||
| 1145 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS1 0x220c | ||
| 1146 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS6 0x2368 | ||
| 1147 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS4 0x2768 | ||
| 1148 | #define MC_SECURITY_CARVEOUT14_BOM 0x2284 | ||
| 1149 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS6 0x2408 | ||
| 1150 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS0 0x2790 | ||
| 1151 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS0 0x2348 | ||
| 1152 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS3 0x279c | ||
| 1153 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS6 0x2688 | ||
| 1154 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS3 0x238c | ||
| 1155 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS4 0x2610 | ||
| 1156 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS1 0x2424 | ||
| 1157 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS1 0x2474 | ||
| 1158 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS7 0x227c | ||
| 1159 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS7 0x23b4 | ||
| 1160 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS5 0x27bc | ||
| 1161 | #define MC_SECURITY_CARVEOUT17_BOM 0x2374 | ||
| 1162 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS6 0x20e8 | ||
| 1163 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS2 0x23d8 | ||
| 1164 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS3 0x229c | ||
| 1165 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS6 0x2540 | ||
| 1166 | #define MC_SECURITY_CARVEOUT20_BOM_HI 0x2468 | ||
| 1167 | #define MC_SECURITY_CARVEOUT21_SIZE_128KB 0x24bc | ||
| 1168 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS3 0x2584 | ||
| 1169 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS7 0x21d4 | ||
| 1170 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS3 0x2124 | ||
| 1171 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS3 0x2034 | ||
| 1172 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS5 0x262c | ||
| 1173 | #define MC_SECURITY_CARVEOUT25_BOM 0x25f4 | ||
| 1174 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS6 0x2130 | ||
| 1175 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS6 0x27c8 | ||
| 1176 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS5 0x203c | ||
| 1177 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS3 0x233c | ||
| 1178 | #define MC_SECURITY_CARVEOUT7_CFG0 0x2050 | ||
| 1179 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS1 0x243c | ||
| 1180 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS3 0x215c | ||
| 1181 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS5 0x25c4 | ||
| 1182 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS0 0x2758 | ||
| 1183 | #define MC_SECURITY_CARVEOUT15_BOM_HI 0x22d8 | ||
| 1184 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS2 0x2248 | ||
| 1185 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS5 0x221c | ||
| 1186 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS0 0x22e0 | ||
| 1187 | #define MC_SECURITY_CARVEOUT22_BOM 0x2504 | ||
| 1188 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS3 0x210c | ||
| 1189 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS6 0x24f0 | ||
| 1190 | #define MC_SECURITY_CARVEOUT9_CFG0 0x20f0 | ||
| 1191 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS2 0x2120 | ||
| 1192 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS1 0x2384 | ||
| 1193 | #define MC_SECURITY_CARVEOUT17_BOM_HI 0x2378 | ||
| 1194 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS4 0x2358 | ||
| 1195 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS4 0x2808 | ||
| 1196 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS0 0x24c0 | ||
| 1197 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS2 0x23a0 | ||
| 1198 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS6 0x2598 | ||
| 1199 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS1 0x239c | ||
| 1200 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS3 0x25d4 | ||
| 1201 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS5 0x267c | ||
| 1202 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS1 0x2064 | ||
| 1203 | #define MC_SECURITY_CARVEOUT27_SIZE_128KB 0x269c | ||
| 1204 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS0 0x26b8 | ||
| 1205 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS5 0x276c | ||
| 1206 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS4 0x2250 | ||
| 1207 | #define MC_SECURITY_CARVEOUT12_BOM_HI 0x21e8 | ||
| 1208 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS4 0x2718 | ||
| 1209 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS0 0x2470 | ||
| 1210 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS2 0x27e8 | ||
| 1211 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS6 0x24a8 | ||
| 1212 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS6 0x2220 | ||
| 1213 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS4 0x2628 | ||
| 1214 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS4 0x22a0 | ||
| 1215 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS4 0x2448 | ||
| 1216 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS1 0x20cc | ||
| 1217 | #define MC_SECURITY_CARVEOUT11_BOM 0x2194 | ||
| 1218 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS1 0x26f4 | ||
| 1219 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS6 0x2228 | ||
| 1220 | #define MC_SECURITY_CARVEOUT28_SIZE_128KB 0x26ec | ||
| 1221 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS7 0x213c | ||
| 1222 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS3 0x251c | ||
| 1223 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS4 0x2570 | ||
| 1224 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS4 0x2200 | ||
| 1225 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS5 0x253c | ||
| 1226 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS1 0x2744 | ||
| 1227 | #define MC_SECURITY_CARVEOUT13_SIZE_128KB 0x223c | ||
| 1228 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS0 0x2330 | ||
| 1229 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS2 0x24e0 | ||
| 1230 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS7 0x27c4 | ||
| 1231 | #define MC_SECURITY_CARVEOUT19_BOM 0x2414 | ||
| 1232 | #define MC_SECURITY_CARVEOUT23_SIZE_128KB 0x255c | ||
| 1233 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS0 0x2398 | ||
| 1234 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS5 0x20c4 | ||
| 1235 | #define MC_SECURITY_CARVEOUT23_CFG0 0x2550 | ||
| 1236 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS2 0x2568 | ||
| 1237 | #define MC_SECURITY_CARVEOUT12_SIZE_128KB 0x21ec | ||
| 1238 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS3 0x2444 | ||
| 1239 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS7 0x2684 | ||
| 1240 | #define MC_SECURITY_CARVEOUT30_BOM_HI 0x2788 | ||
| 1241 | #define MC_SECURITY_CARVEOUT13_BOM 0x2234 | ||
| 1242 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS1 0x2244 | ||
| 1243 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS5 0x26b4 | ||
| 1244 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS6 0x21d0 | ||
| 1245 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS7 0x24ac | ||
| 1246 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS3 0x2304 | ||
| 1247 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS7 0x245c | ||
| 1248 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS1 0x211c | ||
| 1249 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS3 0x27b4 | ||
| 1250 | #define MC_SECURITY_CARVEOUT24_BOM_HI 0x25a8 | ||
| 1251 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS2 0x25d0 | ||
| 1252 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS7 0x2404 | ||
| 1253 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS5 0x22f4 | ||
| 1254 | #define MC_SECURITY_CARVEOUT31_CFG0 0x27d0 | ||
| 1255 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS2 0x2108 | ||
| 1256 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS7 0x236c | ||
| 1257 | #define MC_SECURITY_CARVEOUT31_BOM 0x27d4 | ||
| 1258 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS0 0x2708 | ||
| 1259 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS5 0x258c | ||
| 1260 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS2 0x23f0 | ||
| 1261 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS4 0x20d8 | ||
| 1262 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS4 0x25c0 | ||
| 1263 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS5 0x226c | ||
| 1264 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS7 0x2634 | ||
| 1265 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS5 0x280c | ||
| 1266 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS0 0x20b0 | ||
| 1267 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS0 0x2600 | ||
| 1268 | #define MC_SECURITY_CARVEOUT24_CFG0 0x25a0 | ||
| 1269 | #define MC_SECURITY_CARVEOUT28_CFG0 0x26e0 | ||
| 1270 | #define MC_SECURITY_CARVEOUT24_SIZE_128KB 0x25ac | ||
| 1271 | #define MC_SECURITY_CARVEOUT6_CFG0 0x2000 | ||
| 1272 | #define MC_SECURITY_CARVEOUT21_BOM 0x24b4 | ||
| 1273 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS7 0x22cc | ||
| 1274 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS5 0x249c | ||
| 1275 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS7 0x272c | ||
| 1276 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS7 0x2774 | ||
| 1277 | #define MC_SECURITY_CARVEOUT14_BOM_HI 0x2288 | ||
| 1278 | #define MC_SECURITY_CARVEOUT9_SIZE_128KB 0x20fc | ||
| 1279 | #define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS7 0x24f4 | ||
| 1280 | #define MC_SECURITY_CARVEOUT20_BOM 0x2464 | ||
| 1281 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS5 0x21cc | ||
| 1282 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS1 0x2294 | ||
| 1283 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS2 0x2748 | ||
| 1284 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS4 0x2520 | ||
| 1285 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS7 0x2134 | ||
| 1286 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS6 0x2778 | ||
| 1287 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS1 0x21a4 | ||
| 1288 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS3 0x2174 | ||
| 1289 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS3 0x27ec | ||
| 1290 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS0 0x2258 | ||
| 1291 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS0 0x23d0 | ||
| 1292 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS0 0x26f0 | ||
| 1293 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS1 0x27ac | ||
| 1294 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS2 0x2760 | ||
| 1295 | #define MC_SECURITY_CARVEOUT30_SIZE_128KB 0x278c | ||
| 1296 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS2 0x2428 | ||
| 1297 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS1 0x22fc | ||
| 1298 | #define MC_SECURITY_CARVEOUT26_CFG0 0x2640 | ||
| 1299 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS1 0x270c | ||
| 1300 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS6 0x2458 | ||
| 1301 | #define MC_SECURITY_CARVEOUT31_SIZE_128KB 0x27dc | ||
| 1302 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS4 0x2660 | ||
| 1303 | #define MC_SECURITY_CARVEOUT14_SIZE_128KB 0x228c | ||
| 1304 | #define MC_SECURITY_CARVEOUT6_SIZE_128KB 0x200c | ||
| 1305 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS5 0x25dc | ||
| 1306 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS6 0x20e0 | ||
| 1307 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS6 0x2270 | ||
| 1308 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS2 0x2800 | ||
| 1309 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS7 0x20ec | ||
| 1310 | #define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS7 0x268c | ||
| 1311 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS5 0x26cc | ||
| 1312 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS4 0x27b8 | ||
| 1313 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS4 0x2700 | ||
| 1314 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS4 0x2498 | ||
| 1315 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS7 0x24fc | ||
| 1316 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS1 0x2564 | ||
| 1317 | #define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS3 0x224c | ||
| 1318 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS1 0x2104 | ||
| 1319 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS1 0x2514 | ||
| 1320 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS7 0x25e4 | ||
| 1321 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS7 0x277c | ||
| 1322 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS4 0x2070 | ||
| 1323 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS1 0x2154 | ||
| 1324 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS5 0x23e4 | ||
| 1325 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS2 0x2608 | ||
| 1326 | #define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS0 0x21a0 | ||
| 1327 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS3 0x256c | ||
| 1328 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS6 0x26d8 | ||
| 1329 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS7 0x2364 | ||
| 1330 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS4 0x2268 | ||
| 1331 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS4 0x22f0 | ||
| 1332 | #define MC_SECURITY_CARVEOUT24_BOM 0x25a4 | ||
| 1333 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS5 0x212c | ||
| 1334 | #define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS4 0x2218 | ||
| 1335 | #define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS2 0x27b0 | ||
| 1336 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS5 0x22bc | ||
| 1337 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS7 0x240c | ||
| 1338 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS2 0x21f8 | ||
| 1339 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS4 0x21c8 | ||
| 1340 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS3 0x26fc | ||
| 1341 | #define MC_SECURITY_CARVEOUT16_BOM 0x2324 | ||
| 1342 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS4 0x2178 | ||
| 1343 | #define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS2 0x20d0 | ||
| 1344 | #define MC_SECURITY_CARVEOUT18_BOM_HI 0x23c8 | ||
| 1345 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS3 0x2084 | ||
| 1346 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS0 0x24d8 | ||
| 1347 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS5 0x230c | ||
| 1348 | #define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS6 0x2728 | ||
| 1349 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS4 0x27a0 | ||
| 1350 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS7 0x2314 | ||
| 1351 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS2 0x2658 | ||
| 1352 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS6 0x26d0 | ||
| 1353 | #define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS5 0x235c | ||
| 1354 | #define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS3 0x242c | ||
| 1355 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS6 0x24f8 | ||
| 1356 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS5 0x27a4 | ||
| 1357 | #define MC_SECURITY_CARVEOUT29_BOM 0x2734 | ||
| 1358 | #define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS6 0x21d8 | ||
| 1359 | #define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS5 0x2614 | ||
| 1360 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS7 0x231c | ||
| 1361 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS1 0x257c | ||
| 1362 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS7 0x25ec | ||
| 1363 | #define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS6 0x25e0 | ||
| 1364 | #define MC_SECURITY_CARVEOUT13_BOM_HI 0x2238 | ||
| 1365 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS7 0x254c | ||
| 1366 | #define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS0 0x2118 | ||
| 1367 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS2 0x26f8 | ||
| 1368 | #define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS2 0x2388 | ||
| 1369 | #define MC_SECURITY_CARVEOUT21_CFG0 0x24b0 | ||
| 1370 | #define MC_SECURITY_CARVEOUT12_BOM 0x21e4 | ||
| 1371 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS0 0x26a0 | ||
| 1372 | #define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS5 0x2024 | ||
| 1373 | #define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS4 0x26c8 | ||
| 1374 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS3 0x23a4 | ||
| 1375 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS1 0x27e4 | ||
| 1376 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS2 0x2298 | ||
| 1377 | #define MC_SECURITY_CARVEOUT10_SIZE_128KB 0x214c | ||
| 1378 | #define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS2 0x2518 | ||
| 1379 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS6 0x2278 | ||
| 1380 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS7 0x259c | ||
| 1381 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS4 0x2038 | ||
| 1382 | #define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS7 0x24a4 | ||
| 1383 | #define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS0 0x2100 | ||
| 1384 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS7 0x23bc | ||
| 1385 | #define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS7 0x2814 | ||
| 1386 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS3 0x2804 | ||
| 1387 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS6 0x2590 | ||
| 1388 | #define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS0 0x2578 | ||
| 1389 | #define MC_SECURITY_CARVEOUT22_SIZE_128KB 0x250c | ||
| 1390 | #define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS4 0x25d8 | ||
| 1391 | #define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS1 0x26a4 | ||
| 1392 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS7 0x2094 | ||
| 1393 | #define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS2 0x2158 | ||
| 1394 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS0 0x27f8 | ||
| 1395 | #define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS2 0x2068 | ||
| 1396 | #define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS5 0x2574 | ||
| 1397 | #define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS7 0x204c | ||
| 1398 | #define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS5 0x2704 | ||
| 1399 | #define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS2 0x2080 | ||
| 1400 | #define MC_SECURITY_CARVEOUT11_SIZE_128KB 0x219c | ||
| 1401 | #define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS1 0x27fc | ||
| 1402 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS7 0x20e4 | ||
| 1403 | #define MC_SECURITY_CARVEOUT25_BOM_HI 0x25f8 | ||
| 1404 | #define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS6 0x2360 | ||
| 1405 | #define MC_SECURITY_CARVEOUT31_BOM_HI 0x27d8 | ||
| 1406 | #define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS1 0x23ec | ||
| 1407 | #define MC_SECURITY_CARVEOUT16_BOM_HI 0x2328 | ||
| 1408 | #define MC_SECURITY_CARVEOUT20_CFG0 0x2460 | ||
| 1409 | #define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS3 0x2494 | ||
| 1410 | #define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS1 0x24dc | ||
| 1411 | #define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS0 0x22a8 | ||
| 1412 | #define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS4 0x23a8 | ||
| 1413 | #define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS2 0x2620 | ||
| 1414 | #define MC_SECURITY_CARVEOUT25_CFG0 0x25f0 | ||
| 1415 | #define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS3 0x20bc | ||
| 1416 | #define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS3 0x2264 | ||
| 1417 | #define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS1 0x216c | ||
| 1418 | #define MC_SECURITY_CARVEOUT14_CFG0 0x2280 | ||
| 1419 | #define MC_SECURITY_CARVEOUT8_BOM 0x20a4 | ||
| 1420 | #define MC_SECURITY_CARVEOUT22_CFG0 0x2500 | ||
| 1421 | #define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS4 0x2750 | ||
| 1422 | #define MC_SECURITY_CARVEOUT26_SIZE_128KB 0x264c | ||
| 1423 | #define MC_SECURITY_CARVEOUT13_CFG0 0x2230 | ||
| 1424 | #define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS6 0x2548 | ||
| 1425 | #define MC_SECURITY_CARVEOUT26_BOM 0x2644 | ||
| 1426 | #define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS1 0x275c | ||
| 1427 | #define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS6 0x2680 | ||
| 1428 | #define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS6 0x27c0 | ||
| 1429 | #define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS5 0x2204 | ||
| 1430 | #define MC_SECURITY_CARVEOUT17_SIZE_128KB 0x237c | ||
| 1431 | #define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS5 0x244c | ||
| 1432 | #define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS7 0x22c4 | ||
| 1433 | #define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS6 0x2400 | ||
| 1434 | #define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS6 0x2310 | ||
| 1435 | #define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS6 0x2318 | ||
| 1436 | #define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 | ||
| 1437 | #define MC_DA_CONFIG0 0x9dc | ||
| 1438 | #define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 | ||
| 1439 | #define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 | ||
| 1440 | #define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dc | ||
| 1441 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 | ||
| 1442 | #define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 | ||
| 1443 | #define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAW 0x1504 | ||
| 1444 | #define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 | ||
| 1445 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRA 0x1680 | ||
| 1446 | #define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 | ||
| 1447 | #define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162c | ||
| 1448 | #define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 | ||
| 1449 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA1 0x1750 | ||
| 1450 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 | ||
| 1451 | #define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4 | ||
| 1452 | #define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4 | ||
| 1453 | #define MC_TBU_CLIENT_STEERING_CONFIG_RCEW 0x16a0 | ||
| 1454 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 | ||
| 1455 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4 | ||
| 1456 | #define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 | ||
| 1457 | #define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALR 0x122c | ||
| 1458 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 | ||
| 1459 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178c | ||
| 1460 | #define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW 0x126c | ||
| 1461 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 | ||
| 1462 | #define MC_TBU_CLIENT_STEERING_CONFIG_AXISR 0x1464 | ||
| 1463 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA0WRA 0x1608 | ||
| 1464 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bc | ||
| 1465 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU1W 0x154c | ||
| 1466 | #define MC_TBU_CLIENT_STEERING_CONFIG_SATAW 0x11ec | ||
| 1467 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W 0x1700 | ||
| 1468 | #define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 | ||
| 1469 | #define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTR 0x1254 | ||
| 1470 | #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 | ||
| 1471 | #define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 | ||
| 1472 | #define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAW 0x14b4 | ||
| 1473 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 | ||
| 1474 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB 0x1670 | ||
| 1475 | #define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 | ||
| 1476 | #define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW 0x125c | ||
| 1477 | #define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fc | ||
| 1478 | #define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 | ||
| 1479 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU6R 0x17f8 | ||
| 1480 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179c | ||
| 1481 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 | ||
| 1482 | #define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 | ||
| 1483 | #define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008 | ||
| 1484 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW 0x16f0 | ||
| 1485 | #define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 | ||
| 1486 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 | ||
| 1487 | #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4 | ||
| 1488 | #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 | ||
| 1489 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dc | ||
| 1490 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R 0x16c8 | ||
| 1491 | #define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAR 0x16a8 | ||
| 1492 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD1 0x1790 | ||
| 1493 | #define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRD 0x12a4 | ||
| 1494 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176c | ||
| 1495 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166c | ||
| 1496 | #define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 | ||
| 1497 | #define MC_TBU_CLIENT_STEERING_CONFIG_ISPWA 0x1234 | ||
| 1498 | #define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 | ||
| 1499 | #define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAW 0x16b0 | ||
| 1500 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AR 0x16e8 | ||
| 1501 | #define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 | ||
| 1502 | #define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ec | ||
| 1503 | #define MC_TBU_CLIENT_STEERING_CONFIG_VIW 0x1394 | ||
| 1504 | #define MC_TBU_CLIENT_STEERING_CONFIG_BPMPR 0x149c | ||
| 1505 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD 0x13c4 | ||
| 1506 | #define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4 | ||
| 1507 | #define MC_TBU_CLIENT_STEERING_CONFIG_EQOSR 0x1474 | ||
| 1508 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDC 0x1648 | ||
| 1509 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 | ||
| 1510 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164c | ||
| 1511 | #define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCR 0x1314 | ||
| 1512 | #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 | ||
| 1513 | #define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 | ||
| 1514 | #define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16cc | ||
| 1515 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU3R 0x1584 | ||
| 1516 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU6W 0x4c00 | ||
| 1517 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17cc | ||
| 1518 | #define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCW 0x148c | ||
| 1519 | #define MC_TBU_CLIENT_STEERING_CONFIG_AONR 0x14bc | ||
| 1520 | #define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010 | ||
| 1521 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU4W 0x15a0 | ||
| 1522 | #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 | ||
| 1523 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDC 0x1678 | ||
| 1524 | #define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 | ||
| 1525 | #define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158c | ||
| 1526 | #define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAW 0x14d4 | ||
| 1527 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 | ||
| 1528 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU2R 0x1574 | ||
| 1529 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU5R 0x17e8 | ||
| 1530 | #define MC_TBU_CLIENT_STEERING_CONFIG_SATAR 0x10fc | ||
| 1531 | #define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 | ||
| 1532 | #define MC_TBU_CLIENT_STEERING_CONFIG_SESRD 0x1404 | ||
| 1533 | #define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWAB 0x133c | ||
| 1534 | #define MC_TBU_CLIENT_STEERING_CONFIG_AXISW 0x146c | ||
| 1535 | #define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 | ||
| 1536 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA 0x1618 | ||
| 1537 | #define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWRB 0x143c | ||
| 1538 | #define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 | ||
| 1539 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 | ||
| 1540 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3R 0x16f8 | ||
| 1541 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU3W 0x1590 | ||
| 1542 | #define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 | ||
| 1543 | #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 | ||
| 1544 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4R 0x1708 | ||
| 1545 | #define MC_TBU_CLIENT_STEERING_CONFIG_PTCR 0x1004 | ||
| 1546 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA1 0x1758 | ||
| 1547 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 | ||
| 1548 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSWR 0x13cc | ||
| 1549 | #define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 | ||
| 1550 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALWRB 0x1630 | ||
| 1551 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 | ||
| 1552 | #define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228 | ||
| 1553 | #define MC_TBU_CLIENT_STEERING_CONFIG_SCEW 0x14e4 | ||
| 1554 | #define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWA 0x1324 | ||
| 1555 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W 0x16e0 | ||
| 1556 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175c | ||
| 1557 | #define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4 | ||
| 1558 | #define MC_TBU_CLIENT_STEERING_CONFIG_HDAR 0x10ac | ||
| 1559 | #define MC_TBU_CLIENT_STEERING_CONFIG_BPMPW 0x14a4 | ||
| 1560 | #define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPW 0x141c | ||
| 1561 | #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 | ||
| 1562 | #define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 | ||
| 1563 | #define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174c | ||
| 1564 | #define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 | ||
| 1565 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1R 0x16d8 | ||
| 1566 | #define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 | ||
| 1567 | #define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410 | ||
| 1568 | #define MC_TBU_CLIENT_STEERING_CONFIG_ETRW 0x142c | ||
| 1569 | #define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4 | ||
| 1570 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALRDB 0x1620 | ||
| 1571 | #define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 | ||
| 1572 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 | ||
| 1573 | #define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 | ||
| 1574 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALRDB 0x1600 | ||
| 1575 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU7W 0x1014 | ||
| 1576 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALWRB 0x1610 | ||
| 1577 | #define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 | ||
| 1578 | #define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170c | ||
| 1579 | #define MC_TBU_CLIENT_STEERING_CONFIG_VIFALR 0x15e8 | ||
| 1580 | #define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD 0x1364 | ||
| 1581 | #define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 | ||
| 1582 | #define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAR 0x14cc | ||
| 1583 | #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 | ||
| 1584 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA 0x1638 | ||
| 1585 | #define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 | ||
| 1586 | #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 | ||
| 1587 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA1 0x1770 | ||
| 1588 | #define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 | ||
| 1589 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU5W 0x17f0 | ||
| 1590 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD1 0x151c | ||
| 1591 | #define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4 | ||
| 1592 | #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 | ||
| 1593 | #define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD1 0x1514 | ||
| 1594 | #define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAR 0x14ac | ||
| 1595 | #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 | ||
| 1596 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 | ||
| 1597 | #define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161c | ||
| 1598 | #define MC_TBU_CLIENT_STEERING_CONFIG_SESWR 0x140c | ||
| 1599 | #define MC_TBU_CLIENT_STEERING_CONFIG_EQOSW 0x147c | ||
| 1600 | #define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 | ||
| 1601 | #define MC_TBU_CLIENT_STEERING_CONFIG_ETRR 0x1424 | ||
| 1602 | #define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169c | ||
| 1603 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 | ||
| 1604 | #define MC_TBU_CLIENT_STEERING_CONFIG_MPCORER 0x113c | ||
| 1605 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU0R 0x1534 | ||
| 1606 | #define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 | ||
| 1607 | #define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVR 0x1264 | ||
| 1608 | #define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4 | ||
| 1609 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSRD 0x13f4 | ||
| 1610 | #define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4 | ||
| 1611 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SWR 0x16c0 | ||
| 1612 | #define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 | ||
| 1613 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171c | ||
| 1614 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R1 0x1780 | ||
| 1615 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W 0x1720 | ||
| 1616 | #define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCW 0x1334 | ||
| 1617 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 | ||
| 1618 | #define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 | ||
| 1619 | #define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160c | ||
| 1620 | #define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ec | ||
| 1621 | #define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA1 0x1798 | ||
| 1622 | #define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fc | ||
| 1623 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA 0x15f8 | ||
| 1624 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB1 0x1768 | ||
| 1625 | #define MC_TBU_CLIENT_STEERING_CONFIG_APER 0x13d4 | ||
| 1626 | #define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA 0x1224 | ||
| 1627 | #define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fc | ||
| 1628 | #define MC_TBU_CLIENT_STEERING_CONFIG_DLA1WRA 0x1628 | ||
| 1629 | #define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 | ||
| 1630 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRC 0x1690 | ||
| 1631 | #define MC_TBU_CLIENT_STEERING_CONFIG_VICSWR 0x136c | ||
| 1632 | #define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165c | ||
| 1633 | #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 | ||
| 1634 | #define MC_TBU_CLIENT_STEERING_CONFIG_AONW 0x14c4 | ||
| 1635 | #define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAR 0x14ec | ||
| 1636 | #define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPR 0x1414 | ||
| 1637 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA 0x1668 | ||
| 1638 | #define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 | ||
| 1639 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU4R 0x1598 | ||
| 1640 | #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 | ||
| 1641 | #define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 | ||
| 1642 | #define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRA 0x1304 | ||
| 1643 | #define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWR 0x12ac | ||
| 1644 | #define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418 | ||
| 1645 | #define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRDB 0x1434 | ||
| 1646 | #define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594 | ||
| 1647 | #define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159c | ||
| 1648 | #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 | ||
| 1649 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRB 0x1658 | ||
| 1650 | #define MC_TBU_CLIENT_STEERING_CONFIG_RCER 0x1698 | ||
| 1651 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB1 0x1778 | ||
| 1652 | #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 | ||
| 1653 | #define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAR 0x14fc | ||
| 1654 | #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 | ||
| 1655 | #define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCR 0x1484 | ||
| 1656 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU7R 0x100c | ||
| 1657 | #define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 | ||
| 1658 | #define MC_TBU_CLIENT_STEERING_CONFIG_MPCOREW 0x11cc | ||
| 1659 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W 0x1710 | ||
| 1660 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R1 0x17a0 | ||
| 1661 | #define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 | ||
| 1662 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD1 0x1788 | ||
| 1663 | #define MC_TBU_CLIENT_STEERING_CONFIG_HOST1XDMAR 0x10b4 | ||
| 1664 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU2W 0x157c | ||
| 1665 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD1 0x17d8 | ||
| 1666 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRB 0x1688 | ||
| 1667 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W 0x16d0 | ||
| 1668 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 | ||
| 1669 | #define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 | ||
| 1670 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRA 0x1650 | ||
| 1671 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168c | ||
| 1672 | #define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4 | ||
| 1673 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU1R 0x1544 | ||
| 1674 | #define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 | ||
| 1675 | #define MC_TBU_CLIENT_STEERING_CONFIG_ISPWB 0x123c | ||
| 1676 | #define MC_TBU_CLIENT_STEERING_CONFIG_MIU0W 0x153c | ||
| 1677 | #define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 | ||
| 1678 | #define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16ac | ||
| 1679 | #define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R 0x1718 | ||
| 1680 | #define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 | ||
| 1681 | #define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 | ||
| 1682 | #define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 | ||
| 1683 | #define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRAB 0x131c | ||
| 1684 | #define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 | ||
| 1685 | #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 | ||
| 1686 | #define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177c | ||
| 1687 | #define MC_TBU_CLIENT_STEERING_CONFIG_SCER 0x14dc | ||
| 1688 | #define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163c | ||
| 1689 | #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 | ||
| 1690 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR1 0x150c | ||
| 1691 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSWR 0x115c | ||
| 1692 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSWR 0x13fc | ||
| 1693 | #define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167c | ||
| 1694 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA1 0x1760 | ||
| 1695 | #define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ec | ||
| 1696 | #define MC_TBU_CLIENT_STEERING_CONFIG_VIFALW 0x15f0 | ||
| 1697 | #define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAW 0x14f4 | ||
| 1698 | #define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 | ||
| 1699 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD 0x17d0 | ||
| 1700 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SWR 0x17e0 | ||
| 1701 | #define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 | ||
| 1702 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR 0x1494 | ||
| 1703 | #define MC_TBU_CLIENT_STEERING_CONFIG_HDAW 0x11ac | ||
| 1704 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD 0x10e4 | ||
| 1705 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB 0x1640 | ||
| 1706 | #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 | ||
| 1707 | #define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD 0x16b8 | ||
| 1708 | #define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 | ||
| 1709 | #define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 | ||
| 1710 | #define MC_TBU_CLIENT_STEERING_CONFIG_APEW 0x13dc | ||
| 1711 | #define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALW 0x1728 | ||
| 1712 | #define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 | ||
| 1713 | #define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRC 0x1660 | ||
| 1714 | #define MC_TBU_ADR_MASK_0 0x1800 | ||
| 1715 | #define MC_TBU_ADR_MASK_1 0x1804 | ||
| 1716 | #define MC_TBU_ADR_MASK_2 0x18bc | ||
| 1717 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_0 0x1808 | ||
| 1718 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_1 0x180c | ||
| 1719 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_2 0x1810 | ||
| 1720 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_3 0x1814 | ||
| 1721 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_4 0x1818 | ||
| 1722 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_5 0x181c | ||
| 1723 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_6 0x18b0 | ||
| 1724 | #define MC_CLIENT_TRAFFIC_TYPE_CONFIG_7 0x18b4 | ||
| 1725 | #define MC_MC_TBU_TRANSACTION_ATTR_CTRL 0x18b8 | ||
| 1726 | #define MC_CLIENT_ORDER_ID_27 0x2a6c | ||
| 1727 | #define MC_CLIENT_ORDER_ID_13 0x2a34 | ||
| 1728 | #define MC_CLIENT_ORDER_ID_9 0x2a24 | ||
| 1729 | #define MC_CLIENT_ORDER_ID_4 0x2a10 | ||
| 1730 | #define MC_CLIENT_ORDER_ID_10 0x2a28 | ||
| 1731 | #define MC_CLIENT_ORDER_ID_21 0x2a54 | ||
| 1732 | #define MC_CLIENT_ORDER_ID_26 0x2a68 | ||
| 1733 | #define MC_CLIENT_ORDER_ID_17 0x2a44 | ||
| 1734 | #define MC_CLIENT_ORDER_ID_15 0x2a3c | ||
| 1735 | #define MC_CLIENT_ORDER_ID_6 0x2a18 | ||
| 1736 | #define MC_CLIENT_ORDER_ID_30 0x2d00 | ||
| 1737 | #define MC_CLIENT_ORDER_ID_18 0x2a48 | ||
| 1738 | #define MC_CLIENT_ORDER_ID_5 0x2a14 | ||
| 1739 | #define MC_CLIENT_ORDER_ID_23 0x2a5c | ||
| 1740 | #define MC_CLIENT_ORDER_ID_29 0x2a74 | ||
| 1741 | #define MC_CLIENT_ORDER_ID_14 0x2a38 | ||
| 1742 | #define MC_CLIENT_ORDER_ID_24 0x2a60 | ||
| 1743 | #define MC_CLIENT_ORDER_ID_3 0x2a0c | ||
| 1744 | #define MC_CLIENT_ORDER_ID_19 0x2a4c | ||
| 1745 | #define MC_CLIENT_ORDER_ID_7 0x2a1c | ||
| 1746 | #define MC_CLIENT_ORDER_ID_0 0x2a00 | ||
| 1747 | #define MC_CLIENT_ORDER_ID_2 0x2a08 | ||
| 1748 | #define MC_CLIENT_ORDER_ID_16 0x2a40 | ||
| 1749 | #define MC_CLIENT_ORDER_ID_22 0x2a58 | ||
| 1750 | #define MC_CLIENT_ORDER_ID_12 0x2a30 | ||
| 1751 | #define MC_CLIENT_ORDER_ID_28 0x2a70 | ||
| 1752 | #define MC_CLIENT_ORDER_ID_31 0x2d04 | ||
| 1753 | #define MC_CLIENT_ORDER_ID_25 0x2a64 | ||
| 1754 | #define MC_CLIENT_ORDER_ID_20 0x2a50 | ||
| 1755 | #define MC_CLIENT_ORDER_ID_8 0x2a20 | ||
| 1756 | #define MC_HUB_PC_VC_ID_11 0x2aa4 | ||
| 1757 | #define MC_HUB_PC_VC_ID_12 0x2aa8 | ||
| 1758 | #define MC_HUB_PC_VC_ID_2 0x2a80 | ||
| 1759 | #define MC_HUB_PC_VC_ID_10 0x2aa0 | ||
| 1760 | #define MC_HUB_PC_VC_ID_6 0x2a90 | ||
| 1761 | #define MC_HUB_PC_VC_ID_13 0x2d78 | ||
| 1762 | #define MC_HUB_PC_VC_ID_1 0x2a7c | ||
| 1763 | #define MC_HUB_PC_VC_ID_7 0x2a94 | ||
| 1764 | #define MC_HUB_PC_VC_ID_0 0x2a78 | ||
| 1765 | #define MC_HUB_PC_VC_ID_9 0x2a9c | ||
| 1766 | #define MC_HUB_PC_VC_ID_5 0x2a8c | ||
| 1767 | #define MC_HUB_PC_VC_ID_3 0x2a84 | ||
| 1768 | #define MC_HUB_PC_VC_ID_8 0x2a98 | ||
| 1769 | #define MC_HUB_PC_VC_ID_14 0x2d7c | ||
| 1770 | #define MC_HUB_PC_VC_ID_4 0x2a88 | ||
| 1771 | #define MC_COALESCE_CTRL 0x2930 | ||
| 1772 | #define MC_CLIENT_COALESCE_CONFIG_0 0x2934 | ||
| 1773 | #define MC_CLIENT_COALESCE_CONFIG_1 0x2938 | ||
| 1774 | #define MC_CLIENT_COALESCE_CONFIG_2 0x293c | ||
| 1775 | #define MC_CLIENT_COALESCE_CONFIG_3 0x2940 | ||
| 1776 | #define MC_CLIENT_COALESCE_CONFIG_4 0x2944 | ||
| 1777 | #define MC_CLIENT_COALESCE_CONFIG_5 0x2948 | ||
| 1778 | #define MC_CLIENT_COALESCE_CONFIG_6 0x294c | ||
| 1779 | #define MC_CLIENT_COALESCE_CONFIG_7 0x2950 | ||
| 1780 | #define MC_HUB_VC_ARB_SEL 0x2954 | ||
| 1781 | #define MC_MC_SMMU_ARB_MAX_OUTSTANDING_NISO 0x2958 | ||
| 1782 | #define MC_MC_SMMU_ARB_MAX_OUTSTANDING_SISO 0x295c | ||
| 1783 | #define MC_MC_SMMU_ARB_MAX_OUTSTANDING_ISO 0x2960 | ||
| 1784 | #define MC_MC_SMMU_ARB_MAX_THROTTLE 0x2964 | ||
| 1785 | #define MC_MC_SMMU_PTC2H_REQ_MAPPING_OVERRIDE 0x296c | ||
| 1786 | #define MC_MC_SMMU_PTC2H_REQ_MAPPING 0x2970 | ||
| 1787 | #define MC_COALESCE_ERR_STATUS 0x3000 | ||
| 1788 | #define MC_COALESCE_ERR_ADR_HI 0x3004 | ||
| 1789 | #define MC_COALESCE_ERR_ADR 0x3008 | ||
| 1790 | #define MC_CLIENT_CCI_CAPABLE_0 0x1824 | ||
| 1791 | #define MC_CLIENT_CCI_CAPABLE_1 0x1828 | ||
| 1792 | #define MC_CLIENT_CCI_CAPABLE_2 0x182c | ||
| 1793 | #define MC_CLIENT_CCI_CAPABLE_3 0x1830 | ||
| 1794 | #define MC_CLIENT_CCI_CAPABLE_4 0x1834 | ||
| 1795 | #define MC_CLIENT_CCI_CAPABLE_5 0x1838 | ||
| 1796 | #define MC_CLIENT_CCI_CAPABLE_6 0x183c | ||
| 1797 | #define MC_CLIENT_CCI_CAPABLE_8 0x1c34 | ||
| 1798 | #define MC_CLIENT_CCI_CAPABLE_7 0x193c | ||
| 1799 | #define MC_MAX_OUTSTANDING_CCI 0x1840 | ||
| 1800 | #define MC_NV_CACHE_CONFIG 0x1844 | ||
| 1801 | #define MC_NV_CACHE_HUB_MASK 0x184c | ||
| 1802 | #define MC_SYSRAM_BOM 0x1850 | ||
| 1803 | #define MC_SYSRAM_TOM 0x1854 | ||
| 1804 | #define MC_SYSRAM_ADR_HI 0x1588 | ||
| 1805 | #define MC_SYSRAM_REG_CTRL 0x185c | ||
| 1806 | #define MC_MSSNVLINK_BOM 0x1860 | ||
| 1807 | #define MC_MSSNVLINK_TOM 0x1864 | ||
| 1808 | #define MC_MSSNVLINK_REG_CTRL 0x186c | ||
| 1809 | #define MC_SYNCPOINT_BOM 0x1870 | ||
| 1810 | #define MC_SYNCPOINT_TOM 0x1874 | ||
| 1811 | #define MC_SYNCPOINT_REG_CTRL 0x187c | ||
| 1812 | #define MC_ECC_CONTROL 0x1880 | ||
| 1813 | #define MC_MSSNVLINK_IGPU_LATENCY_ALLOWANCE 0x1890 | ||
| 1814 | #define MC_MSSNVLINK_DGPU_LATENCY_ALLOWANCE 0x1894 | ||
| 1815 | #define MC_CIFLL_NVLRHP_LATENCY_ALLOWANCE 0x189c | ||
| 1816 | #define MC_CLIENT_HOTRESET_STATUS_2 0x1898 | ||
| 1817 | #define MC_CFG_WCAM_GOB_REMAP 0xed4 | ||
| 1818 | #define MC_ECC_RAW_MODE_CONTROL 0xed8 | ||
| 1819 | #define MC_ECC_CFG 0x1884 | ||
| 1820 | #define MC_TR_BIT_CTL 0xed0 | ||
| 1821 | #define MC_CH_INTSTATUS 0xe54 | ||
| 1822 | #define MC_LATENCY_ALLOWANCE_WCAM 0xe5c | ||
| 1823 | #define MC_CFG_WCAM 0xe60 | ||
| 1824 | #define MC_WCAM_ENCR_KEY_STATUS 0xe64 | ||
| 1825 | #define MC_WCAM_STATE 0xeb0 | ||
| 1826 | #define MC_WCAM_IRQ_TEST 0xedc | ||
| 1827 | #define MC_WCAM_IRQ_P0_STATUS0 0xee0 | ||
| 1828 | #define MC_WCAM_IRQ_P0_STATUS1 0xee4 | ||
| 1829 | #define MC_WCAM_IRQ_P1_STATUS0 0xee8 | ||
| 1830 | #define MC_WCAM_IRQ_P1_STATUS1 0xeec | ||
| 1831 | #define MC_ROC_DMA_R_PTSA_MIN 0xe68 | ||
| 1832 | #define MC_ROC_DMA_R_PTSA_MAX 0xe6c | ||
| 1833 | #define MC_ROC_DMA_R_PTSA_RATE 0xe70 | ||
| 1834 | #define MC_RING1_WR_B_PTSA_MIN 0xe74 | ||
| 1835 | #define MC_RING1_WR_B_PTSA_MAX 0xe78 | ||
| 1836 | #define MC_RING1_WR_B_PTSA_RATE 0xe7c | ||
| 1837 | #define MC_RING1_WR_NB_PTSA_MIN 0xe80 | ||
| 1838 | #define MC_RING1_WR_NB_PTSA_MAX 0xe84 | ||
| 1839 | #define MC_RING1_WR_NB_PTSA_RATE 0xe88 | ||
| 1840 | #define MC_RING1_RD_B_PTSA_MIN 0xe8c | ||
| 1841 | #define MC_RING1_RD_B_PTSA_MAX 0xe90 | ||
| 1842 | #define MC_RING1_RD_B_PTSA_RATE 0xe94 | ||
| 1843 | #define MC_RING1_RD_NB_PTSA_MIN 0xe98 | ||
| 1844 | #define MC_RING1_RD_NB_PTSA_MAX 0xe9c | ||
| 1845 | #define MC_RING1_RD_NB_PTSA_RATE 0xea0 | ||
| 1846 | #define MC_FREE_BANK_QUEUES 0xea4 | ||
| 1847 | #define MC_RING0_MT_FIFO_CREDITS 0xea8 | ||
| 1848 | #define MC_LATENCY_ALLOWANCE_ROC_DMA_R_0 0xeac | ||
| 1849 | #define MC_LATENCY_ALLOWANCE_CIFLL_WR_0 0x1100 | ||
| 1850 | #define MC_CIFLL_NISO_PTSA_MIN 0x1104 | ||
| 1851 | #define MC_CIFLL_NISO_PTSA_MAX 0x1108 | ||
| 1852 | #define MC_CIFLL_NISO_PTSA_RATE 0x110c | ||
| 1853 | #define MC_CIFLL_SISO_PTSA_MIN 0x1110 | ||
| 1854 | #define MC_CIFLL_SISO_PTSA_MAX 0x1114 | ||
| 1855 | #define MC_CIFLL_SISO_PTSA_RATE 0x1118 | ||
| 1856 | #define MC_CIFLL_ISO_PTSA_MIN 0x111c | ||
| 1857 | #define MC_CIFLL_ISO_PTSA_MAX 0x1120 | ||
| 1858 | #define MC_CIFLL_ISO_PTSA_RATE 0x1124 | ||
| 1859 | #define MC_CIFLL_RING0X_PTSA_MIN 0x1128 | ||
| 1860 | #define MC_CIFLL_RING0X_PTSA_MAX 0x112c | ||
| 1861 | #define MC_CIFLL_RING0X_PTSA_RATE 0x1130 | ||
| 1862 | #define MC_CIFLL_CPU_RD_PRI_CTRL 0x1174 | ||
| 1863 | #define MC_MEM_SCRUBBER_ECC_ADDR 0xf18 | ||
| 1864 | #define MC_MEM_SCRUBBER_ECC_ADDR_HI 0xf1c | ||
| 1865 | #define MC_MEM_SCRUBBER_ECC_REG_CTRL 0xf20 | ||
| 1866 | #define MC_CONFIG_TSA_SINGLE_ARB_ENABLE 0xfe8 | ||
| 1867 | #define MC_DBB_RINGFENCE_CTRL 0xfec | ||
| 1868 | #define MC_DBB_RINGFENCE_STATUS 0xff0 | ||
| 1869 | #define MC_CCITRX_ENABLE_CONFIG 0xf3c | ||
| 1870 | #define MC_CCI_WR_LATENCY_ALLOWANCE_CONFIG 0xf40 | ||
| 1871 | #define MC_EMEM_ARB_THROTTLE_CFG 0xf44 | ||
| 1872 | #define MC_MSS_SYSRAM_EC_FEATURE 0x9000 | ||
| 1873 | #define MC_MSS_SYSRAM_EC_SWRESET 0x9004 | ||
| 1874 | #define MC_MSS_SYSRAM_EC_MISSIONERR_TYPE 0x9008 | ||
| 1875 | #define MC_MSS_SYSRAM_EC_CURRENT_COUNTER_VALUE 0x900c | ||
| 1876 | #define MC_MSS_SYSRAM_EC_MISSIONERR_USERVALUE 0x9010 | ||
| 1877 | #define MC_MSS_SYSRAM_EC_MISSIONERR_INDEX 0x9014 | ||
| 1878 | #define MC_MSS_SYSRAM_EC_CORRECTABLE_THRESHOLD 0x9018 | ||
| 1879 | #define MC_MSS_SYSRAM_EC_MISSIONERR_INJECT_UNLOCK 0x901c | ||
| 1880 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9030 | ||
| 1881 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_FORCE 0x9034 | ||
| 1882 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_STATUS 0x9038 | ||
| 1883 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_INJECT 0x903c | ||
| 1884 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_ENABLE 0x9040 | ||
| 1885 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_FORCE 0x9044 | ||
| 1886 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_STATUS 0x9048 | ||
| 1887 | #define MC_MSS_SYSRAM_EC_ERRSLICE0_COUNTER_RELOAD 0x9050 | ||
| 1888 | #define MC_TCU_WRAP_EC_FEATURE 0x9100 | ||
| 1889 | #define MC_TCU_WRAP_EC_SWRESET 0x9104 | ||
| 1890 | #define MC_TCU_WRAP_EC_MISSIONERR_TYPE 0x9108 | ||
| 1891 | #define MC_TCU_WRAP_EC_CURRENT_COUNTER_VALUE 0x910c | ||
| 1892 | #define MC_TCU_WRAP_EC_MISSIONERR_USERVALUE 0x9110 | ||
| 1893 | #define MC_TCU_WRAP_EC_MISSIONERR_INDEX 0x9114 | ||
| 1894 | #define MC_TCU_WRAP_EC_CORRECTABLE_THRESHOLD 0x9118 | ||
| 1895 | #define MC_TCU_WRAP_EC_MISSIONERR_INJECT_UNLOCK 0x911c | ||
| 1896 | #define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9130 | ||
| 1897 | #define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_FORCE 0x9134 | ||
| 1898 | #define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_STATUS 0x9138 | ||
| 1899 | #define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_INJECT 0x913c | ||
| 1900 | #define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_ENABLE 0x9140 | ||
| 1901 | #define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_FORCE 0x9144 | ||
| 1902 | #define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_STATUS 0x9148 | ||
| 1903 | #define MC_TCU_WRAP_EC_ERRSLICE0_COUNTER_RELOAD 0x9150 | ||
| 1904 | #define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9160 | ||
| 1905 | #define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_FORCE 0x9164 | ||
| 1906 | #define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_STATUS 0x9168 | ||
| 1907 | #define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_INJECT 0x916c | ||
| 1908 | #define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_ENABLE 0x9170 | ||
| 1909 | #define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_FORCE 0x9174 | ||
| 1910 | #define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_STATUS 0x9178 | ||
| 1911 | #define MC_TCU_WRAP_EC_ERRSLICE1_COUNTER_RELOAD 0x9180 | ||
| 1912 | #define MC_MSS_SBS_EC_FEATURE 0x9200 | ||
| 1913 | #define MC_MSS_SBS_EC_SWRESET 0x9204 | ||
| 1914 | #define MC_MSS_SBS_EC_MISSIONERR_TYPE 0x9208 | ||
| 1915 | #define MC_MSS_SBS_EC_CURRENT_COUNTER_VALUE 0x920c | ||
| 1916 | #define MC_MSS_SBS_EC_MISSIONERR_USERVALUE 0x9210 | ||
| 1917 | #define MC_MSS_SBS_EC_MISSIONERR_INDEX 0x9214 | ||
| 1918 | #define MC_MSS_SBS_EC_CORRECTABLE_THRESHOLD 0x9218 | ||
| 1919 | #define MC_MSS_SBS_EC_MISSIONERR_INJECT_UNLOCK 0x921c | ||
| 1920 | #define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9230 | ||
| 1921 | #define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_FORCE 0x9234 | ||
| 1922 | #define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_STATUS 0x9238 | ||
| 1923 | #define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_INJECT 0x923c | ||
| 1924 | #define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_ENABLE 0x9240 | ||
| 1925 | #define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_FORCE 0x9244 | ||
| 1926 | #define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_STATUS 0x9248 | ||
| 1927 | #define MC_MSS_SBS_EC_ERRSLICE0_COUNTER_RELOAD 0x9250 | ||
| 1928 | #define MC_MCF_SLICE_EC_FEATURE 0x9300 | ||
| 1929 | #define MC_MCF_SLICE_EC_SWRESET 0x9304 | ||
| 1930 | #define MC_MCF_SLICE_EC_MISSIONERR_TYPE 0x9308 | ||
| 1931 | #define MC_MCF_SLICE_EC_CURRENT_COUNTER_VALUE 0x930c | ||
| 1932 | #define MC_MCF_SLICE_EC_MISSIONERR_USERVALUE 0x9310 | ||
| 1933 | #define MC_MCF_SLICE_EC_MISSIONERR_INDEX 0x9314 | ||
| 1934 | #define MC_MCF_SLICE_EC_CORRECTABLE_THRESHOLD 0x9318 | ||
| 1935 | #define MC_MCF_SLICE_EC_MISSIONERR_INJECT_UNLOCK 0x931c | ||
| 1936 | #define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9330 | ||
| 1937 | #define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_FORCE 0x9334 | ||
| 1938 | #define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_STATUS 0x9338 | ||
| 1939 | #define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_INJECT 0x933c | ||
| 1940 | #define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_ENABLE 0x9340 | ||
| 1941 | #define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_FORCE 0x9344 | ||
| 1942 | #define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_STATUS 0x9348 | ||
| 1943 | #define MC_MCF_SLICE_EC_ERRSLICE0_COUNTER_RELOAD 0x9350 | ||
| 1944 | #define MC_MCF_IREQX_EC_FEATURE 0x9400 | ||
| 1945 | #define MC_MCF_IREQX_EC_SWRESET 0x9404 | ||
| 1946 | #define MC_MCF_IREQX_EC_MISSIONERR_TYPE 0x9408 | ||
| 1947 | #define MC_MCF_IREQX_EC_CURRENT_COUNTER_VALUE 0x940c | ||
| 1948 | #define MC_MCF_IREQX_EC_MISSIONERR_INDEX 0x9414 | ||
| 1949 | #define MC_MCF_IREQX_EC_CORRECTABLE_THRESHOLD 0x9418 | ||
| 1950 | #define MC_MCF_IREQX_EC_MISSIONERR_INJECT_UNLOCK 0x941c | ||
| 1951 | #define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9430 | ||
| 1952 | #define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9434 | ||
| 1953 | #define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9438 | ||
| 1954 | #define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_INJECT 0x943c | ||
| 1955 | #define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9440 | ||
| 1956 | #define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_FORCE 0x9444 | ||
| 1957 | #define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_STATUS 0x9448 | ||
| 1958 | #define MC_MCF_IREQX_EC_ERRSLICE0_COUNTER_RELOAD 0x9450 | ||
| 1959 | #define MC_MCF_IRSPX_EC_FEATURE 0x9500 | ||
| 1960 | #define MC_MCF_IRSPX_EC_SWRESET 0x9504 | ||
| 1961 | #define MC_MCF_IRSPX_EC_MISSIONERR_TYPE 0x9508 | ||
| 1962 | #define MC_MCF_IRSPX_EC_CURRENT_COUNTER_VALUE 0x950c | ||
| 1963 | #define MC_MCF_IRSPX_EC_MISSIONERR_USERVALUE 0x9510 | ||
| 1964 | #define MC_MCF_IRSPX_EC_MISSIONERR_INDEX 0x9514 | ||
| 1965 | #define MC_MCF_IRSPX_EC_CORRECTABLE_THRESHOLD 0x9518 | ||
| 1966 | #define MC_MCF_IRSPX_EC_MISSIONERR_INJECT_UNLOCK 0x951c | ||
| 1967 | #define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9530 | ||
| 1968 | #define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9534 | ||
| 1969 | #define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9538 | ||
| 1970 | #define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_INJECT 0x953c | ||
| 1971 | #define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9540 | ||
| 1972 | #define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_FORCE 0x9544 | ||
| 1973 | #define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_STATUS 0x9548 | ||
| 1974 | #define MC_MCF_IRSPX_EC_ERRSLICE0_COUNTER_RELOAD 0x9550 | ||
| 1975 | #define MC_MCF_OREQX_EC_FEATURE 0x9600 | ||
| 1976 | #define MC_MCF_OREQX_EC_SWRESET 0x9604 | ||
| 1977 | #define MC_MCF_OREQX_EC_MISSIONERR_TYPE 0x9608 | ||
| 1978 | #define MC_MCF_OREQX_EC_CURRENT_COUNTER_VALUE 0x960c | ||
| 1979 | #define MC_MCF_OREQX_EC_MISSIONERR_USERVALUE 0x9610 | ||
| 1980 | #define MC_MCF_OREQX_EC_MISSIONERR_INDEX 0x9614 | ||
| 1981 | #define MC_MCF_OREQX_EC_CORRECTABLE_THRESHOLD 0x9618 | ||
| 1982 | #define MC_MCF_OREQX_EC_MISSIONERR_INJECT_UNLOCK 0x961c | ||
| 1983 | #define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9630 | ||
| 1984 | #define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9634 | ||
| 1985 | #define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9638 | ||
| 1986 | #define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_INJECT 0x963c | ||
| 1987 | #define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9640 | ||
| 1988 | #define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_FORCE 0x9644 | ||
| 1989 | #define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_STATUS 0x9648 | ||
| 1990 | #define MC_MCF_OREQX_EC_ERRSLICE0_COUNTER_RELOAD 0x9650 | ||
| 1991 | #define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9660 | ||
| 1992 | #define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_FORCE 0x9664 | ||
| 1993 | #define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_STATUS 0x9668 | ||
| 1994 | #define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_INJECT 0x966c | ||
| 1995 | #define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_ENABLE 0x9670 | ||
| 1996 | #define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_FORCE 0x9674 | ||
| 1997 | #define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_STATUS 0x9678 | ||
| 1998 | #define MC_MCF_OREQX_EC_ERRSLICE1_COUNTER_RELOAD 0x9680 | ||
| 1999 | #define MC_MCF_ORSPX_EC_FEATURE 0x9700 | ||
| 2000 | #define MC_MCF_ORSPX_EC_SWRESET 0x9704 | ||
| 2001 | #define MC_MCF_ORSPX_EC_MISSIONERR_TYPE 0x9708 | ||
| 2002 | #define MC_MCF_ORSPX_EC_CURRENT_COUNTER_VALUE 0x970c | ||
| 2003 | #define MC_MCF_ORSPX_EC_MISSIONERR_INDEX 0x9714 | ||
| 2004 | #define MC_MCF_ORSPX_EC_CORRECTABLE_THRESHOLD 0x9718 | ||
| 2005 | #define MC_MCF_ORSPX_EC_MISSIONERR_INJECT_UNLOCK 0x971c | ||
| 2006 | #define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9730 | ||
| 2007 | #define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9734 | ||
| 2008 | #define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9738 | ||
| 2009 | #define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_INJECT 0x973c | ||
| 2010 | #define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9740 | ||
| 2011 | #define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_FORCE 0x9744 | ||
| 2012 | #define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_STATUS 0x9748 | ||
| 2013 | #define MC_MCF_ORSPX_EC_ERRSLICE0_COUNTER_RELOAD 0x9750 | ||
| 2014 | #define MC_CHANNEL_EC_FEATURE 0x9800 | ||
| 2015 | #define MC_CHANNEL_EC_SWRESET 0x9804 | ||
| 2016 | #define MC_CHANNEL_EC_MISSIONERR_TYPE 0x9808 | ||
| 2017 | #define MC_CHANNEL_EC_CURRENT_COUNTER_VALUE 0x980c | ||
| 2018 | #define MC_CHANNEL_EC_MISSIONERR_USERVALUE 0x9810 | ||
| 2019 | #define MC_CHANNEL_EC_MISSIONERR_INDEX 0x9814 | ||
| 2020 | #define MC_CHANNEL_EC_CORRECTABLE_THRESHOLD 0x9818 | ||
| 2021 | #define MC_CHANNEL_EC_MISSIONERR_INJECT_UNLOCK 0x981c | ||
| 2022 | #define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9830 | ||
| 2023 | #define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_FORCE 0x9834 | ||
| 2024 | #define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_STATUS 0x9838 | ||
| 2025 | #define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_INJECT 0x983c | ||
| 2026 | #define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_ENABLE 0x9840 | ||
| 2027 | #define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_FORCE 0x9844 | ||
| 2028 | #define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_STATUS 0x9848 | ||
| 2029 | #define MC_CHANNEL_EC_ERRSLICE0_COUNTER_RELOAD 0x9850 | ||
| 2030 | #define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9860 | ||
| 2031 | #define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_FORCE 0x9864 | ||
| 2032 | #define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_STATUS 0x9868 | ||
| 2033 | #define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_INJECT 0x986c | ||
| 2034 | #define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_ENABLE 0x9870 | ||
| 2035 | #define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_FORCE 0x9874 | ||
| 2036 | #define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_STATUS 0x9878 | ||
| 2037 | #define MC_CHANNEL_EC_ERRSLICE1_COUNTER_RELOAD 0x9880 | ||
| 2038 | #define MC_HUB_EC_FEATURE 0x9900 | ||
| 2039 | #define MC_HUB_EC_SWRESET 0x9904 | ||
| 2040 | #define MC_HUB_EC_MISSIONERR_TYPE 0x9908 | ||
| 2041 | #define MC_HUB_EC_CURRENT_COUNTER_VALUE 0x990c | ||
| 2042 | #define MC_HUB_EC_MISSIONERR_USERVALUE 0x9910 | ||
| 2043 | #define MC_HUB_EC_MISSIONERR_INDEX 0x9914 | ||
| 2044 | #define MC_HUB_EC_CORRECTABLE_THRESHOLD 0x9918 | ||
| 2045 | #define MC_HUB_EC_MISSIONERR_INJECT_UNLOCK 0x991c | ||
| 2046 | #define MC_HUB_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9930 | ||
| 2047 | #define MC_HUB_EC_ERRSLICE0_MISSIONERR_FORCE 0x9934 | ||
| 2048 | #define MC_HUB_EC_ERRSLICE0_MISSIONERR_STATUS 0x9938 | ||
| 2049 | #define MC_HUB_EC_ERRSLICE0_MISSIONERR_INJECT 0x993c | ||
| 2050 | #define MC_HUB_EC_ERRSLICE0_LATENTERR_ENABLE 0x9940 | ||
| 2051 | #define MC_HUB_EC_ERRSLICE0_LATENTERR_FORCE 0x9944 | ||
| 2052 | #define MC_HUB_EC_ERRSLICE0_LATENTERR_STATUS 0x9948 | ||
| 2053 | #define MC_HUB_EC_ERRSLICE0_COUNTER_RELOAD 0x9950 | ||
| 2054 | #define MC_HUBC_EC_FEATURE 0x9a00 | ||
| 2055 | #define MC_HUBC_EC_SWRESET 0x9a04 | ||
| 2056 | #define MC_HUBC_EC_MISSIONERR_TYPE 0x9a08 | ||
| 2057 | #define MC_HUBC_EC_CURRENT_COUNTER_VALUE 0x9a0c | ||
| 2058 | #define MC_HUBC_EC_MISSIONERR_USERVALUE 0x9a10 | ||
| 2059 | #define MC_HUBC_EC_MISSIONERR_INDEX 0x9a14 | ||
| 2060 | #define MC_HUBC_EC_CORRECTABLE_THRESHOLD 0x9a18 | ||
| 2061 | #define MC_HUBC_EC_MISSIONERR_INJECT_UNLOCK 0x9a1c | ||
| 2062 | #define MC_HUBC_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9a30 | ||
| 2063 | #define MC_HUBC_EC_ERRSLICE0_MISSIONERR_FORCE 0x9a34 | ||
| 2064 | #define MC_HUBC_EC_ERRSLICE0_MISSIONERR_STATUS 0x9a38 | ||
| 2065 | #define MC_HUBC_EC_ERRSLICE0_MISSIONERR_INJECT 0x9a3c | ||
| 2066 | #define MC_HUBC_EC_ERRSLICE0_LATENTERR_ENABLE 0x9a40 | ||
| 2067 | #define MC_HUBC_EC_ERRSLICE0_LATENTERR_FORCE 0x9a44 | ||
| 2068 | #define MC_HUBC_EC_ERRSLICE0_LATENTERR_STATUS 0x9a48 | ||
| 2069 | #define MC_HUBC_EC_ERRSLICE0_COUNTER_RELOAD 0x9a50 | ||
| 2070 | |||
| 2071 | #endif | ||
diff --git a/include/linux/platform/tegra/tegra-cpu.h b/include/linux/platform/tegra/tegra-cpu.h new file mode 100644 index 000000000..a85c4ab9a --- /dev/null +++ b/include/linux/platform/tegra/tegra-cpu.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/cputype.h> | ||
| 15 | #include <asm/cpu.h> | ||
| 16 | |||
| 17 | #define MIDR_CPU_MASK 0xFF0FFFF0 | ||
| 18 | #define MIDR_CPU_CARMEL 0x4E0F0040 | ||
| 19 | |||
| 20 | static inline u8 tegra_is_cpu_carmel(u8 cpu) | ||
| 21 | { | ||
| 22 | struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, cpu); | ||
| 23 | return ((cpuinfo->reg_midr & MIDR_CPU_MASK) == MIDR_CPU_CARMEL); | ||
| 24 | } | ||
diff --git a/include/linux/platform/tegra/tegra_cbb.h b/include/linux/platform/tegra/tegra_cbb.h new file mode 100644 index 000000000..d2c0072ee --- /dev/null +++ b/include/linux/platform/tegra/tegra_cbb.h | |||
| @@ -0,0 +1,344 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms and conditions of the GNU General Public License, | ||
| 6 | * version 2, as published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | |||
| 15 | #define OFF_ERRLOGGER_0_ID_COREID_0 0x00000000 | ||
| 16 | #define OFF_ERRLOGGER_0_ID_REVISIONID_0 0x00000004 | ||
| 17 | #define OFF_ERRLOGGER_0_FAULTEN_0 0x00000008 | ||
| 18 | #define OFF_ERRLOGGER_0_ERRVLD_0 0x0000000c | ||
| 19 | #define OFF_ERRLOGGER_0_ERRCLR_0 0x00000010 | ||
| 20 | #define OFF_ERRLOGGER_0_ERRLOG0_0 0x00000014 | ||
| 21 | #define OFF_ERRLOGGER_0_ERRLOG1_0 0x00000018 | ||
| 22 | #define OFF_ERRLOGGER_0_RESERVED_00_0 0x0000001c | ||
| 23 | #define OFF_ERRLOGGER_0_ERRLOG3_0 0x00000020 | ||
| 24 | #define OFF_ERRLOGGER_0_ERRLOG4_0 0x00000024 | ||
| 25 | #define OFF_ERRLOGGER_0_ERRLOG5_0 0x00000028 | ||
| 26 | #define OFF_ERRLOGGER_0_STALLEN_0 0x00000038 | ||
| 27 | |||
| 28 | #define OFF_ERRLOGGER_1_ID_COREID_0 0x00000080 | ||
| 29 | #define OFF_ERRLOGGER_1_ID_REVISIONID_0 0x00000084 | ||
| 30 | #define OFF_ERRLOGGER_1_FAULTEN_0 0x00000088 | ||
| 31 | #define OFF_ERRLOGGER_1_ERRVLD_0 0x0000008c | ||
| 32 | #define OFF_ERRLOGGER_1_ERRCLR_0 0x00000090 | ||
| 33 | #define OFF_ERRLOGGER_1_ERRLOG0_0 0x00000094 | ||
| 34 | #define OFF_ERRLOGGER_1_ERRLOG1_0 0x00000098 | ||
| 35 | #define OFF_ERRLOGGER_1_RESERVED_00_0 0x0000009c | ||
| 36 | #define OFF_ERRLOGGER_1_ERRLOG3_0 0x000000A0 | ||
| 37 | #define OFF_ERRLOGGER_1_ERRLOG4_0 0x000000A4 | ||
| 38 | #define OFF_ERRLOGGER_1_ERRLOG5_0 0x000000A8 | ||
| 39 | #define OFF_ERRLOGGER_1_STALLEN_0 0x000000b8 | ||
| 40 | |||
| 41 | #define OFF_ERRLOGGER_2_ID_COREID_0 0x00000100 | ||
| 42 | #define OFF_ERRLOGGER_2_ID_REVISIONID_0 0x00000104 | ||
| 43 | #define OFF_ERRLOGGER_2_FAULTEN_0 0x00000108 | ||
| 44 | #define OFF_ERRLOGGER_2_ERRVLD_0 0x0000010c | ||
| 45 | #define OFF_ERRLOGGER_2_ERRCLR_0 0x00000110 | ||
| 46 | #define OFF_ERRLOGGER_2_ERRLOG0_0 0x00000114 | ||
| 47 | #define OFF_ERRLOGGER_2_ERRLOG1_0 0x00000118 | ||
| 48 | #define OFF_ERRLOGGER_2_RESERVED_00_0 0x0000011c | ||
| 49 | #define OFF_ERRLOGGER_2_ERRLOG3_0 0x00000120 | ||
| 50 | #define OFF_ERRLOGGER_2_ERRLOG4_0 0x00000124 | ||
| 51 | #define OFF_ERRLOGGER_2_ERRLOG5_0 0x00000128 | ||
| 52 | #define OFF_ERRLOGGER_2_STALLEN_0 0x00000138 | ||
| 53 | |||
| 54 | |||
| 55 | #define CBBNOC_BIT(_bit_) (1ULL << (_bit_)) | ||
| 56 | #define CBBNOC_MASK(_msb_, _lsb_) \ | ||
| 57 | ((CBBNOC_BIT(_msb_+1) - 1) & ~(CBBNOC_BIT(_lsb_) - 1)) | ||
| 58 | #define CBBNOC_EXTRACT(_x_, _msb_, _lsb_) \ | ||
| 59 | ((_x_ & CBBNOC_MASK(_msb_, _lsb_)) >> _lsb_) | ||
| 60 | |||
| 61 | |||
| 62 | #define get_cbb_errlog0_trans_opc(_x_) CBBNOC_EXTRACT(_x_, 4, 1) | ||
| 63 | #define get_cbb_errlog0_code(_x_) CBBNOC_EXTRACT(_x_, 10, 8) | ||
| 64 | #define get_cbb_errlog0_src(_x_) CBBNOC_EXTRACT(_x_, 27, 16) | ||
| 65 | |||
| 66 | #define get_cbb_errlog5_axi_id(_x_) CBBNOC_EXTRACT(_x_, 30, 23) | ||
| 67 | #define get_cbb_errlog5_mstr_id(_x_) CBBNOC_EXTRACT(_x_, 22, 19) | ||
| 68 | #define get_cbb_errlog5_vqc(_x_) CBBNOC_EXTRACT(_x_, 18, 17) | ||
| 69 | #define get_cbb_errlog5_grpsec(_x_) CBBNOC_EXTRACT(_x_, 16, 10) | ||
| 70 | #define get_cbb_errlog5_falconsec(_x_) CBBNOC_EXTRACT(_x_, 9, 8) | ||
| 71 | #define get_cbb_errlog5_axprot(_x_) CBBNOC_EXTRACT(_x_, 7, 5) | ||
| 72 | #define get_cbb_errlog5_non_modify(_x_) CBBNOC_EXTRACT(_x_, 4, 4) | ||
| 73 | #define get_cbb_errlog5_axcache(_x_) CBBNOC_EXTRACT(_x_, 3, 0) | ||
| 74 | |||
| 75 | #define get_cbb_routeid_initflow(_x_) CBBNOC_EXTRACT(_x_, 23, 20) | ||
| 76 | #define get_cbb_routeid_targflow(_x_) CBBNOC_EXTRACT(_x_, 19, 16) | ||
| 77 | #define get_cbb_routeid_targsubrange(_x_) CBBNOC_EXTRACT(_x_, 15, 9) | ||
| 78 | #define get_cbb_routeid_seqid(_x_) CBBNOC_EXTRACT(_x_, 8, 0) | ||
| 79 | |||
| 80 | |||
| 81 | struct tegra_cbbnoc_errors { | ||
| 82 | char *errcode; | ||
| 83 | char *src; | ||
| 84 | char *type; | ||
| 85 | }; | ||
| 86 | |||
| 87 | struct tegra_noc_packet_header { | ||
| 88 | bool lock; // [0] | ||
| 89 | u8 opc; // [4:1] | ||
| 90 | u8 errcode;// [10:8]= RD, RDW, RDL, RDX, WR, WRW, WRC, PRE, URG | ||
| 91 | u16 len1; // [27:16] | ||
| 92 | bool format; // [31] = 1 -> FlexNoC versions 2.7 & above | ||
| 93 | }; | ||
| 94 | |||
| 95 | struct tegra_cbb_routeid { | ||
| 96 | u8 initflow; // [23:20] | ||
| 97 | u16 targflow; // [19:16] | ||
| 98 | u8 targ_subrange; // [15:09] | ||
| 99 | u16 seqid; // [08:00] | ||
| 100 | }; | ||
| 101 | |||
| 102 | |||
| 103 | struct tegra_cbb_errlog_record { | ||
| 104 | struct list_head node; | ||
| 105 | struct serr_hook *callback; | ||
| 106 | char *name; | ||
| 107 | phys_addr_t start; | ||
| 108 | void __iomem *vaddr; | ||
| 109 | u32 errlog0; | ||
| 110 | u32 errlog1; | ||
| 111 | u32 errlog2; | ||
| 112 | u32 errlog3; | ||
| 113 | u32 errlog4; | ||
| 114 | u32 errlog5; | ||
| 115 | u32 errlog6; //RESERVED | ||
| 116 | u32 errlog7; //RESERVED | ||
| 117 | u32 errlog8; //RESERVED | ||
| 118 | unsigned int (*errvld)(void __iomem *addr); | ||
| 119 | void (*errclr)(void __iomem *addr); | ||
| 120 | void (*faulten)(void __iomem *addr); | ||
| 121 | void (*stallen)(void __iomem *addr); | ||
| 122 | struct tegra_cbbnoc_errors *errors; | ||
| 123 | struct tegra_lookup_noc_aperture *noc_aperture; | ||
| 124 | int max_noc_aperture; | ||
| 125 | }; | ||
| 126 | |||
| 127 | struct tegra_lookup_noc_aperture { | ||
| 128 | u8 initflow; | ||
| 129 | u8 targflow; | ||
| 130 | u8 targ_subrange; | ||
| 131 | u8 init_mapping; | ||
| 132 | u32 init_localaddress; | ||
| 133 | u8 targ_mapping; | ||
| 134 | u32 targ_localaddress; | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct tegra_cbb_bridge_data { | ||
| 138 | char *name; | ||
| 139 | unsigned int (*errvld)(void __iomem *addr); | ||
| 140 | void (*errclr)(void __iomem *addr); | ||
| 141 | void (*faulten)(void __iomem *addr); | ||
| 142 | void (*stallen)(void __iomem *addr); | ||
| 143 | struct tegra_cbbnoc_errors *errors; | ||
| 144 | struct tegra_lookup_noc_aperture *noc_aperture; | ||
| 145 | int max_error; | ||
| 146 | int max_noc_aperture; | ||
| 147 | }; | ||
| 148 | |||
| 149 | |||
| 150 | /* | ||
| 151 | * NOC aperture lookup table as per file "cbb_central_noc_Structure.info". | ||
| 152 | * Fields: | ||
| 153 | * Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress, Targ mapping, Targ localAddress | ||
| 154 | * ----------------------------------------------------------------------------------------------------- | ||
| 155 | */ | ||
| 156 | |||
| 157 | static struct tegra_lookup_noc_aperture t194_lookup_noc_aperture[] = { | ||
| 158 | { 0x0, 0x0, 0x00, 0x0, 0x02300000, 0, 0x0 }, | ||
| 159 | { 0x0, 0x1, 0x00, 0x0, 0x02003000, 0, 0x02003000 }, | ||
| 160 | { 0x0, 0x1, 0x01, 0x0, 0x02006000, 2, 0x02006000 }, | ||
| 161 | { 0x0, 0x1, 0x02, 0x0, 0x02016000, 3, 0x02016000 }, | ||
| 162 | { 0x0, 0x1, 0x03, 0x0, 0x0201d000, 4, 0x0201d000 }, | ||
| 163 | { 0x0, 0x1, 0x04, 0x0, 0x0202b000, 6, 0x0202b000 }, | ||
| 164 | { 0x0, 0x1, 0x05, 0x0, 0x02434000, 20, 0x02434000 }, | ||
| 165 | { 0x0, 0x1, 0x06, 0x0, 0x02436000, 21, 0x02436000 }, | ||
| 166 | { 0x0, 0x1, 0x07, 0x0, 0x02438000, 22, 0x02438000 }, | ||
| 167 | { 0x0, 0x1, 0x08, 0x0, 0x02445000, 24, 0x02445000 }, | ||
| 168 | { 0x0, 0x1, 0x09, 0x0, 0x02446000, 25, 0x02446000 }, | ||
| 169 | { 0x0, 0x1, 0x0a, 0x0, 0x02004000, 1, 0x02004000 }, | ||
| 170 | { 0x0, 0x1, 0x0b, 0x0, 0x0201e000, 5, 0x0201e000 }, | ||
| 171 | { 0x0, 0x1, 0x0c, 0x0, 0x0202c000, 7, 0x0202c000 }, | ||
| 172 | { 0x0, 0x1, 0x0d, 0x0, 0x02204000, 8, 0x02204000 }, | ||
| 173 | { 0x0, 0x1, 0x0e, 0x0, 0x02214000, 9, 0x02214000 }, | ||
| 174 | { 0x0, 0x1, 0x0f, 0x0, 0x02224000, 10, 0x02224000 }, | ||
| 175 | { 0x0, 0x1, 0x10, 0x0, 0x02234000, 11, 0x02234000 }, | ||
| 176 | { 0x0, 0x1, 0x11, 0x0, 0x02244000, 12, 0x02244000 }, | ||
| 177 | { 0x0, 0x1, 0x12, 0x0, 0x02254000, 13, 0x02254000 }, | ||
| 178 | { 0x0, 0x1, 0x13, 0x0, 0x02264000, 14, 0x02264000 }, | ||
| 179 | { 0x0, 0x1, 0x14, 0x0, 0x02274000, 15, 0x02274000 }, | ||
| 180 | { 0x0, 0x1, 0x15, 0x0, 0x02284000, 16, 0x02284000 }, | ||
| 181 | { 0x0, 0x1, 0x16, 0x0, 0x0243a000, 23, 0x0243a000 }, | ||
| 182 | { 0x0, 0x1, 0x17, 0x0, 0x02370000, 17, 0x02370000 }, | ||
| 183 | { 0x0, 0x1, 0x18, 0x0, 0x023d0000, 18, 0x023d0000 }, | ||
| 184 | { 0x0, 0x1, 0x19, 0x0, 0x023e0000, 19, 0x023e0000 }, | ||
| 185 | { 0x0, 0x1, 0x1a, 0x0, 0x02450000, 26, 0x02450000 }, | ||
| 186 | { 0x0, 0x1, 0x1b, 0x0, 0x02460000, 27, 0x02460000 }, | ||
| 187 | { 0x0, 0x1, 0x1c, 0x0, 0x02490000, 28, 0x02490000 }, | ||
| 188 | { 0x0, 0x1, 0x1d, 0x0, 0x03130000, 31, 0x03130000 }, | ||
| 189 | { 0x0, 0x1, 0x1e, 0x0, 0x03160000, 32, 0x03160000 }, | ||
| 190 | { 0x0, 0x1, 0x1f, 0x0, 0x03270000, 33, 0x03270000 }, | ||
| 191 | { 0x0, 0x1, 0x20, 0x0, 0x032e0000, 35, 0x032e0000 }, | ||
| 192 | { 0x0, 0x1, 0x21, 0x0, 0x03300000, 36, 0x03300000 }, | ||
| 193 | { 0x0, 0x1, 0x22, 0x0, 0x13090000, 40, 0x13090000 }, | ||
| 194 | { 0x0, 0x1, 0x23, 0x0, 0x20120000, 43, 0x20120000 }, | ||
| 195 | { 0x0, 0x1, 0x24, 0x0, 0x20170000, 44, 0x20170000 }, | ||
| 196 | { 0x0, 0x1, 0x25, 0x0, 0x20190000, 45, 0x20190000 }, | ||
| 197 | { 0x0, 0x1, 0x26, 0x0, 0x201b0000, 46, 0x201b0000 }, | ||
| 198 | { 0x0, 0x1, 0x27, 0x0, 0x20250000, 47, 0x20250000 }, | ||
| 199 | { 0x0, 0x1, 0x28, 0x0, 0x20260000, 48, 0x20260000 }, | ||
| 200 | { 0x0, 0x1, 0x29, 0x0, 0x20420000, 49, 0x20420000 }, | ||
| 201 | { 0x0, 0x1, 0x2a, 0x0, 0x20460000, 50, 0x20460000 }, | ||
| 202 | { 0x0, 0x1, 0x2b, 0x0, 0x204f0000, 51, 0x204f0000 }, | ||
| 203 | { 0x0, 0x1, 0x2c, 0x0, 0x20520000, 52, 0x20520000 }, | ||
| 204 | { 0x0, 0x1, 0x2d, 0x0, 0x20580000, 53, 0x20580000 }, | ||
| 205 | { 0x0, 0x1, 0x2e, 0x0, 0x205a0000, 54, 0x205a0000 }, | ||
| 206 | { 0x0, 0x1, 0x2f, 0x0, 0x205c0000, 55, 0x205c0000 }, | ||
| 207 | { 0x0, 0x1, 0x30, 0x0, 0x20690000, 56, 0x20690000 }, | ||
| 208 | { 0x0, 0x1, 0x31, 0x0, 0x20770000, 57, 0x20770000 }, | ||
| 209 | { 0x0, 0x1, 0x32, 0x0, 0x20790000, 58, 0x20790000 }, | ||
| 210 | { 0x0, 0x1, 0x33, 0x0, 0x20880000, 59, 0x20880000 }, | ||
| 211 | { 0x0, 0x1, 0x34, 0x0, 0x20990000, 62, 0x20990000 }, | ||
| 212 | { 0x0, 0x1, 0x35, 0x0, 0x20e10000, 65, 0x20e10000 }, | ||
| 213 | { 0x0, 0x1, 0x36, 0x0, 0x20e70000, 66, 0x20e70000 }, | ||
| 214 | { 0x0, 0x1, 0x37, 0x0, 0x20e80000, 67, 0x20e80000 }, | ||
| 215 | { 0x0, 0x1, 0x38, 0x0, 0x20f30000, 68, 0x20f30000 }, | ||
| 216 | { 0x0, 0x1, 0x39, 0x0, 0x20f50000, 69, 0x20f50000 }, | ||
| 217 | { 0x0, 0x1, 0x3a, 0x0, 0x20fc0000, 70, 0x20fc0000 }, | ||
| 218 | { 0x0, 0x1, 0x3b, 0x0, 0x21110000, 72, 0x21110000 }, | ||
| 219 | { 0x0, 0x1, 0x3c, 0x0, 0x21270000, 73, 0x21270000 }, | ||
| 220 | { 0x0, 0x1, 0x3d, 0x0, 0x21290000, 74, 0x21290000 }, | ||
| 221 | { 0x0, 0x1, 0x3e, 0x0, 0x21840000, 75, 0x21840000 }, | ||
| 222 | { 0x0, 0x1, 0x3f, 0x0, 0x21880000, 76, 0x21880000 }, | ||
| 223 | { 0x0, 0x1, 0x40, 0x0, 0x218d0000, 77, 0x218d0000 }, | ||
| 224 | { 0x0, 0x1, 0x41, 0x0, 0x21950000, 78, 0x21950000 }, | ||
| 225 | { 0x0, 0x1, 0x42, 0x0, 0x21960000, 79, 0x21960000 }, | ||
| 226 | { 0x0, 0x1, 0x43, 0x0, 0x21a10000, 80, 0x21a10000 }, | ||
| 227 | { 0x0, 0x1, 0x44, 0x0, 0x024a0000, 29, 0x024a0000 }, | ||
| 228 | { 0x0, 0x1, 0x45, 0x0, 0x024c0000, 30, 0x024c0000 }, | ||
| 229 | { 0x0, 0x1, 0x46, 0x0, 0x032c0000, 34, 0x032c0000 }, | ||
| 230 | { 0x0, 0x1, 0x47, 0x0, 0x03400000, 37, 0x03400000 }, | ||
| 231 | { 0x0, 0x1, 0x48, 0x0, 0x130a0000, 41, 0x130a0000 }, | ||
| 232 | { 0x0, 0x1, 0x49, 0x0, 0x130c0000, 42, 0x130c0000 }, | ||
| 233 | { 0x0, 0x1, 0x4a, 0x0, 0x208a0000, 60, 0x208a0000 }, | ||
| 234 | { 0x0, 0x1, 0x4b, 0x0, 0x208c0000, 61, 0x208c0000 }, | ||
| 235 | { 0x0, 0x1, 0x4c, 0x0, 0x209a0000, 63, 0x209a0000 }, | ||
| 236 | { 0x0, 0x1, 0x4d, 0x0, 0x21a40000, 81, 0x21a40000 }, | ||
| 237 | { 0x0, 0x1, 0x4e, 0x0, 0x03440000, 38, 0x03440000 }, | ||
| 238 | { 0x0, 0x1, 0x4f, 0x0, 0x20d00000, 64, 0x20d00000 }, | ||
| 239 | { 0x0, 0x1, 0x50, 0x0, 0x21000000, 71, 0x21000000 }, | ||
| 240 | { 0x0, 0x1, 0x51, 0x0, 0x0b000000, 39, 0x0b000000 }, | ||
| 241 | { 0x0, 0x2, 0x00, 0x0, 0x00000000, 0, 0x00000000 }, | ||
| 242 | { 0x0, 0x3, 0x00, 0x0, 0x02340000, 0, 0x00000000 }, | ||
| 243 | { 0x0, 0x4, 0x00, 0x0, 0x17000000, 0, 0x17000000 }, | ||
| 244 | { 0x0, 0x4, 0x01, 0x0, 0x18000000, 1, 0x18000000 }, | ||
| 245 | { 0x0, 0x5, 0x00, 0x0, 0x13e80000, 1, 0x13e80000 }, | ||
| 246 | { 0x0, 0x5, 0x01, 0x0, 0x15810000, 12, 0x15810000 }, | ||
| 247 | { 0x0, 0x5, 0x02, 0x0, 0x15840000, 14, 0x15840000 }, | ||
| 248 | { 0x0, 0x5, 0x03, 0x0, 0x15a40000, 17, 0x15a40000 }, | ||
| 249 | { 0x0, 0x5, 0x04, 0x0, 0x13f00000, 3, 0x13f00000 }, | ||
| 250 | { 0x0, 0x5, 0x05, 0x0, 0x15820000, 13, 0x15820000 }, | ||
| 251 | { 0x0, 0x5, 0x06, 0x0, 0x13ec0000, 2, 0x13ec0000 }, | ||
| 252 | { 0x0, 0x5, 0x07, 0x0, 0x15200000, 6, 0x15200000 }, | ||
| 253 | { 0x0, 0x5, 0x08, 0x0, 0x15340000, 7, 0x15340000 }, | ||
| 254 | { 0x0, 0x5, 0x09, 0x0, 0x15380000, 8, 0x15380000 }, | ||
| 255 | { 0x0, 0x5, 0x0a, 0x0, 0x15500000, 10, 0x15500000 }, | ||
| 256 | { 0x0, 0x5, 0x0b, 0x0, 0x155c0000, 11, 0x155c0000 }, | ||
| 257 | { 0x0, 0x5, 0x0c, 0x0, 0x15a00000, 16, 0x15a00000 }, | ||
| 258 | { 0x0, 0x5, 0x0d, 0x0, 0x13e00000, 0, 0x13e00000 }, | ||
| 259 | { 0x0, 0x5, 0x0e, 0x0, 0x15100000, 5, 0x15100000 }, | ||
| 260 | { 0x0, 0x5, 0x0f, 0x0, 0x15480000, 9, 0x15480000 }, | ||
| 261 | { 0x0, 0x5, 0x10, 0x0, 0x15880000, 15, 0x15880000 }, | ||
| 262 | { 0x0, 0x5, 0x11, 0x0, 0x15a80000, 18, 0x15a80000 }, | ||
| 263 | { 0x0, 0x5, 0x12, 0x0, 0x15b00000, 19, 0x15b00000 }, | ||
| 264 | { 0x0, 0x5, 0x13, 0x0, 0x14800000, 4, 0x14800000 }, | ||
| 265 | { 0x0, 0x5, 0x14, 0x0, 0x15c00000, 20, 0x15c00000 }, | ||
| 266 | { 0x0, 0x5, 0x15, 0x0, 0x16000000, 21, 0x16000000 }, | ||
| 267 | { 0x0, 0x6, 0x00, 0x0, 0x02000000, 4, 0x02000000 }, | ||
| 268 | { 0x0, 0x6, 0x01, 0x0, 0x02007000, 5, 0x02007000 }, | ||
| 269 | { 0x0, 0x6, 0x02, 0x0, 0x02008000, 6, 0x02008000 }, | ||
| 270 | { 0x0, 0x6, 0x03, 0x0, 0x02013000, 7, 0x02013000 }, | ||
| 271 | { 0x0, 0x6, 0x04, 0x0, 0x0201c000, 8, 0x0201c000 }, | ||
| 272 | { 0x0, 0x6, 0x05, 0x0, 0x02020000, 9, 0x02020000 }, | ||
| 273 | { 0x0, 0x6, 0x06, 0x0, 0x0202a000, 10, 0x0202a000 }, | ||
| 274 | { 0x0, 0x6, 0x07, 0x0, 0x0202e000, 11, 0x0202e000 }, | ||
| 275 | { 0x0, 0x6, 0x08, 0x0, 0x06400000, 33, 0x06400000 }, | ||
| 276 | { 0x0, 0x6, 0x09, 0x0, 0x02038000, 12, 0x02038000 }, | ||
| 277 | { 0x0, 0x6, 0x0a, 0x0, 0x00100000, 0, 0x00100000 }, | ||
| 278 | { 0x0, 0x6, 0x0b, 0x0, 0x023b0000, 13, 0x023b0000 }, | ||
| 279 | { 0x0, 0x6, 0x0c, 0x0, 0x02800000, 16, 0x02800000 }, | ||
| 280 | { 0x0, 0x6, 0x0d, 0x0, 0x030e0000, 22, 0x030e0000 }, | ||
| 281 | { 0x0, 0x6, 0x0e, 0x0, 0x03800000, 23, 0x03800000 }, | ||
| 282 | { 0x0, 0x6, 0x0f, 0x0, 0x03980000, 25, 0x03980000 }, | ||
| 283 | { 0x0, 0x6, 0x10, 0x0, 0x03a60000, 26, 0x03a60000 }, | ||
| 284 | { 0x0, 0x6, 0x11, 0x0, 0x03d80000, 31, 0x03d80000 }, | ||
| 285 | { 0x0, 0x6, 0x12, 0x0, 0x20000000, 36, 0x20000000 }, | ||
| 286 | { 0x0, 0x6, 0x13, 0x0, 0x20050000, 38, 0x20050000 }, | ||
| 287 | { 0x0, 0x6, 0x14, 0x0, 0x201e0000, 40, 0x201e0000 }, | ||
| 288 | { 0x0, 0x6, 0x15, 0x0, 0x20280000, 42, 0x20280000 }, | ||
| 289 | { 0x0, 0x6, 0x16, 0x0, 0x202c0000, 43, 0x202c0000 }, | ||
| 290 | { 0x0, 0x6, 0x17, 0x0, 0x20390000, 44, 0x20390000 }, | ||
| 291 | { 0x0, 0x6, 0x18, 0x0, 0x20430000, 45, 0x20430000 }, | ||
| 292 | { 0x0, 0x6, 0x19, 0x0, 0x20440000, 46, 0x20440000 }, | ||
| 293 | { 0x0, 0x6, 0x1a, 0x0, 0x204e0000, 47, 0x204e0000 }, | ||
| 294 | { 0x0, 0x6, 0x1b, 0x0, 0x20550000, 48, 0x20550000 }, | ||
| 295 | { 0x0, 0x6, 0x1c, 0x0, 0x20570000, 49, 0x20570000 }, | ||
| 296 | { 0x0, 0x6, 0x1d, 0x0, 0x20590000, 50, 0x20590000 }, | ||
| 297 | { 0x0, 0x6, 0x1e, 0x0, 0x20730000, 52, 0x20730000 }, | ||
| 298 | { 0x0, 0x6, 0x1f, 0x0, 0x209f0000, 54, 0x209f0000 }, | ||
| 299 | { 0x0, 0x6, 0x20, 0x0, 0x20e20000, 55, 0x20e20000 }, | ||
| 300 | { 0x0, 0x6, 0x21, 0x0, 0x20ed0000, 56, 0x20ed0000 }, | ||
| 301 | { 0x0, 0x6, 0x22, 0x0, 0x20fd0000, 57, 0x20fd0000 }, | ||
| 302 | { 0x0, 0x6, 0x23, 0x0, 0x21120000, 59, 0x21120000 }, | ||
| 303 | { 0x0, 0x6, 0x24, 0x0, 0x211a0000, 60, 0x211a0000 }, | ||
| 304 | { 0x0, 0x6, 0x25, 0x0, 0x21850000, 61, 0x21850000 }, | ||
| 305 | { 0x0, 0x6, 0x26, 0x0, 0x21860000, 62, 0x21860000 }, | ||
| 306 | { 0x0, 0x6, 0x27, 0x0, 0x21890000, 63, 0x21890000 }, | ||
| 307 | { 0x0, 0x6, 0x28, 0x0, 0x21970000, 64, 0x21970000 }, | ||
| 308 | { 0x0, 0x6, 0x29, 0x0, 0x21990000, 65, 0x21990000 }, | ||
| 309 | { 0x0, 0x6, 0x2a, 0x0, 0x21a00000, 66, 0x21a00000 }, | ||
| 310 | { 0x0, 0x6, 0x2b, 0x0, 0x21a90000, 68, 0x21a90000 }, | ||
| 311 | { 0x0, 0x6, 0x2c, 0x0, 0x21ac0000, 70, 0x21ac0000 }, | ||
| 312 | { 0x0, 0x6, 0x2d, 0x0, 0x01f80000, 3, 0x01f80000 }, | ||
| 313 | { 0x0, 0x6, 0x2e, 0x0, 0x024e0000, 14, 0x024e0000 }, | ||
| 314 | { 0x0, 0x6, 0x2f, 0x0, 0x030c0000, 21, 0x030c0000 }, | ||
| 315 | { 0x0, 0x6, 0x30, 0x0, 0x03820000, 24, 0x03820000 }, | ||
| 316 | { 0x0, 0x6, 0x31, 0x0, 0x03aa0000, 27, 0x03aa0000 }, | ||
| 317 | { 0x0, 0x6, 0x32, 0x0, 0x03c80000, 29, 0x03c80000 }, | ||
| 318 | { 0x0, 0x6, 0x33, 0x0, 0x130e0000, 34, 0x130e0000 }, | ||
| 319 | { 0x0, 0x6, 0x34, 0x0, 0x20020000, 37, 0x20020000 }, | ||
| 320 | { 0x0, 0x6, 0x35, 0x0, 0x20060000, 39, 0x20060000 }, | ||
| 321 | { 0x0, 0x6, 0x36, 0x0, 0x20200000, 41, 0x20200000 }, | ||
| 322 | { 0x0, 0x6, 0x37, 0x0, 0x206a0000, 51, 0x206a0000 }, | ||
| 323 | { 0x0, 0x6, 0x38, 0x0, 0x20740000, 53, 0x20740000 }, | ||
| 324 | { 0x0, 0x6, 0x39, 0x0, 0x20fe0000, 58, 0x20fe0000 }, | ||
| 325 | { 0x0, 0x6, 0x3a, 0x0, 0x21a20000, 67, 0x21a20000 }, | ||
| 326 | { 0x0, 0x6, 0x3b, 0x0, 0x21aa0000, 69, 0x21aa0000 }, | ||
| 327 | { 0x0, 0x6, 0x3c, 0x0, 0x02b80000, 17, 0x02b80000 }, | ||
| 328 | { 0x0, 0x6, 0x3d, 0x0, 0x03080000, 20, 0x03080000 }, | ||
| 329 | { 0x0, 0x6, 0x3e, 0x0, 0x13100000, 35, 0x13100000 }, | ||
| 330 | { 0x0, 0x6, 0x3f, 0x0, 0x01f00000, 2, 0x01f00000 }, | ||
| 331 | { 0x0, 0x6, 0x40, 0x0, 0x03000000, 19, 0x03000000 }, | ||
| 332 | { 0x0, 0x6, 0x41, 0x0, 0x03c00000, 28, 0x03c00000 }, | ||
| 333 | { 0x0, 0x6, 0x42, 0x0, 0x03d00000, 30, 0x03d00000 }, | ||
| 334 | { 0x0, 0x6, 0x43, 0x0, 0x01700000, 1, 0x01700000 }, | ||
| 335 | { 0x0, 0x6, 0x44, 0x0, 0x02c00000, 18, 0x02c00000 }, | ||
| 336 | { 0x0, 0x6, 0x45, 0x0, 0x02600000, 15, 0x02600000 }, | ||
| 337 | { 0x0, 0x6, 0x46, 0x0, 0x06000000, 32, 0x06000000 }, | ||
| 338 | { 0x0, 0x6, 0x47, 0x0, 0x24000000, 71, 0x24000000 }, | ||
| 339 | { 0x0, 0x7, 0x00, 0x0, 0x12000000, 0, 0x12000000 }, | ||
| 340 | { 0x0, 0x8, 0x00, 0x0, 0x11000000, 0, 0x11000000 }, | ||
| 341 | { 0x0, 0x9, 0x00, 0x0, 0x10000000, 0, 0x10000000 }, | ||
| 342 | { 0x0, 0xA, 0x00, 0x0, 0x22000000, 0, 0x22000000 } | ||
| 343 | }; | ||
| 344 | |||