tegra: dp: Integrate t19x specific code paths

There are certain DP initialization sequences specific to T19x.

- Fork paths wherever required to incorporate chip specific logic

TDS-1553

Change-Id: If28eb7f55e8f7a5bad7ca0f2a35bfece3fa6d19c
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570524
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Reviewed-by: Santosh Galma <galmar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ujwal Patel <ujwalp@nvidia.com>

6 files changed, 130 insertions, 94 deletions

diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index 4ac21c384..cad1be38e 100644
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -1149,7 +1149,7 @@ static int tegra_dc_init_default_panel_link_cfg(struct tegra_dc_dp_link_config *
          */
         if (!cfg->is_valid) {
                 cfg->max_lane_count = 4;
-                cfg->tps3_supported = false;
+                cfg->tps = TEGRA_DC_DP_TRAINING_PATTERN_2;
                 cfg->support_enhanced_framing = true;
                 cfg->downspread = true;
                 cfg->support_fast_lt = true;
@@ -1164,8 +1164,8 @@ static int tegra_dc_init_default_panel_link_cfg(struct tegra_dc_dp_link_config *
         return 0;
 }
 
-static void tegra_dp_set_max_link_bw(struct tegra_dc_sor_data *sor,
-                                     struct tegra_dc_dp_link_config *cfg)
+void tegra_dp_set_max_link_bw(struct tegra_dc_sor_data *sor,
+                              struct tegra_dc_dp_link_config *cfg)
 {
         unsigned int key; /* Index into the link speed table */
 
@@ -1176,90 +1176,103 @@ static void tegra_dp_set_max_link_bw(struct tegra_dc_sor_data *sor,
         cfg->max_link_bw = sor->link_speeds[key].link_rate;
 }
 
-static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
+static int __tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
                                         struct tegra_dc_dp_link_config *cfg)
 {
-        if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
-                tegra_dc_init_default_panel_link_cfg(cfg);
-        else {
-                u8 dpcd_data;
-                int ret;
+        u8 dpcd_data;
+        int ret;
 
-                if (dp->sink_cap_valid)
-                        dpcd_data = dp->sink_cap[NV_DPCD_MAX_LANE_COUNT];
-                else
-                        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
-                                NV_DPCD_MAX_LANE_COUNT, &dpcd_data));
+        if (dp->sink_cap_valid)
+                dpcd_data = dp->sink_cap[NV_DPCD_MAX_LANE_COUNT];
+        else
+                CHECK_RET(tegra_dc_dp_dpcd_read(dp,
+                        NV_DPCD_MAX_LANE_COUNT, &dpcd_data));
 
-                cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
+        cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
 
-                if (cfg->max_lane_count >= 4)
-                        cfg->max_lane_count = 4;
-                else if (cfg->max_lane_count >= 2)
-                        cfg->max_lane_count = 2;
-                else
-                        cfg->max_lane_count = 1;
-
-                if (dp->pdata && dp->pdata->lanes &&
-                        dp->pdata->lanes < cfg->max_lane_count)
-                        cfg->max_lane_count = dp->pdata->lanes;
-
-                cfg->tps3_supported =
-                        (dpcd_data &
-                        NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ?
-                        true : false;
-                cfg->support_enhanced_framing =
-                (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
+        if (cfg->max_lane_count >= 4)
+                cfg->max_lane_count = 4;
+        else if (cfg->max_lane_count >= 2)
+                cfg->max_lane_count = 2;
+        else
+                cfg->max_lane_count = 1;
+
+        if (dp->pdata && dp->pdata->lanes &&
+                dp->pdata->lanes < cfg->max_lane_count)
+                cfg->max_lane_count = dp->pdata->lanes;
+
+        if (dpcd_data & NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES)
+                cfg->tps = TEGRA_DC_DP_TRAINING_PATTERN_3;
+
+        cfg->support_enhanced_framing =
+        (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
+        true : false;
+
+        if (dp->sink_cap_valid)
+                dpcd_data = dp->sink_cap[NV_DPCD_MAX_DOWNSPREAD];
+        else
+                CHECK_RET(tegra_dc_dp_dpcd_read(dp,
+                                NV_DPCD_MAX_DOWNSPREAD, &dpcd_data));
+        cfg->downspread =
+                (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
+                true : false;
+        cfg->support_fast_lt = (dpcd_data &
+                NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ?
                 true : false;
 
-                if (dp->sink_cap_valid)
-                        dpcd_data = dp->sink_cap[NV_DPCD_MAX_DOWNSPREAD];
-                else
-                        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
-                                        NV_DPCD_MAX_DOWNSPREAD, &dpcd_data));
-                cfg->downspread =
-                        (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
-                        true : false;
-                cfg->support_fast_lt = (dpcd_data &
-                        NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ?
-                        true : false;
+        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
+                NV_DPCD_TRAINING_AUX_RD_INTERVAL, &dpcd_data));
+        cfg->aux_rd_interval = dpcd_data;
 
+        if (dp->sink_cap_valid)
+                cfg->max_link_bw =
+                        dp->sink_cap[NV_DPCD_MAX_LINK_BANDWIDTH];
+        else
                 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
-                        NV_DPCD_TRAINING_AUX_RD_INTERVAL, &dpcd_data));
-                cfg->aux_rd_interval = dpcd_data;
+                        NV_DPCD_MAX_LINK_BANDWIDTH,
+                        &cfg->max_link_bw));
 
-                if (dp->sink_cap_valid)
-                        cfg->max_link_bw =
-                                dp->sink_cap[NV_DPCD_MAX_LINK_BANDWIDTH];
-                else
-                        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
-                                NV_DPCD_MAX_LINK_BANDWIDTH,
-                                &cfg->max_link_bw));
-
-                tegra_dp_set_max_link_bw(dp->sor, cfg);
-
-                if (dp->pdata && dp->pdata->link_bw &&
-                        dp->pdata->link_bw < cfg->max_link_bw)
-                        cfg->max_link_bw = dp->pdata->link_bw;
-
-                CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
-                        &dpcd_data));
-                cfg->alt_scramber_reset_cap =
-                        (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
-                        true : false;
-                cfg->only_enhanced_framing = (dpcd_data &
-                        NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
-                        true : false;
-                cfg->edp_cap = (dpcd_data &
-                        NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ?
-                        true : false;
-
-                CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_FEATURE_ENUM_LIST,
-                        &dpcd_data));
-                cfg->support_vsc_ext_colorimetry = (dpcd_data &
-                        NV_DPCD_FEATURE_ENUM_LIST_VSC_EXT_COLORIMETRY) ?
-                        true : false;
-        }
+        tegra_dp_set_max_link_bw(dp->sor, cfg);
+
+        if (dp->pdata && dp->pdata->link_bw &&
+                dp->pdata->link_bw < cfg->max_link_bw)
+                cfg->max_link_bw = dp->pdata->link_bw;
+
+        CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
+                &dpcd_data));
+        cfg->alt_scramber_reset_cap =
+                (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
+                true : false;
+        cfg->only_enhanced_framing = (dpcd_data &
+                NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
+                true : false;
+        cfg->edp_cap = (dpcd_data &
+                NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ?
+                true : false;
+
+        CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_FEATURE_ENUM_LIST,
+                &dpcd_data));
+        cfg->support_vsc_ext_colorimetry = (dpcd_data &
+                NV_DPCD_FEATURE_ENUM_LIST_VSC_EXT_COLORIMETRY) ?
+                true : false;
+
+        return 0;
+}
+
+static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
+                                        struct tegra_dc_dp_link_config *cfg)
+{
+        int ret = 0;
+
+        if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
+                tegra_dc_init_default_panel_link_cfg(cfg);
+        else if (tegra_dc_is_t19x())
+                ret = tegra_dp_init_max_link_cfg_t19x(dp, cfg);
+        else
+                ret = __tegra_dp_init_max_link_cfg(dp, cfg);
+
+        if (ret)
+                return ret;
 
         cfg->bits_per_pixel = dp->dc->out->depth ? : 24;
 
@@ -1275,6 +1288,7 @@ static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
         tegra_dc_dp_calc_config(dp, dp->mode, cfg);
 
         dp->max_link_cfg = *cfg;
+
         return 0;
 }
 
@@ -1294,7 +1308,6 @@ static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, bool ena)
         return 0;
 }
 
-
 static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
 {
         tegra_dc_sor_set_link_bandwidth(dp->sor, link_bw);
@@ -1867,6 +1880,7 @@ static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp)
 static void tegra_dp_dpcd_init(struct tegra_dc_dp_data *dp)
 {
         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
+        int ret;
         u32 size_ieee_oui = 3, auxstat;
         u8 data_ieee_oui_be[3] = {(NV_IEEE_OUI >> 16) & 0xff,
                 (NV_IEEE_OUI >> 8) & 0xff,
@@ -1877,9 +1891,9 @@ static void tegra_dp_dpcd_init(struct tegra_dc_dp_data *dp)
                 dev_err(&dp->dc->ndev->dev,
                         "dp: failed to read the revision number from sink\n");
 
-        if (tegra_dp_init_max_link_cfg(dp, cfg))
-                dev_err(&dp->dc->ndev->dev,
-                        "dp: failed to init link configuration\n");
+        ret = tegra_dp_init_max_link_cfg(dp, cfg);
+        if (ret)
+                dev_err(&dp->dc->ndev->dev, "dp: failed to init link cfg\n");
 
         tegra_dc_dpaux_write(dp->dpaux, DPAUX_DP_AUXCTL_CMD_AUXWR,
                 NV_DPCD_SOURCE_IEEE_OUI, data_ieee_oui_be, &size_ieee_oui,
diff --git a/drivers/video/tegra/dc/dp.h b/drivers/video/tegra/dc/dp.h
index 083bf2cc5..cd19b426f 100644
--- a/drivers/video/tegra/dc/dp.h
+++ b/drivers/video/tegra/dc/dp.h
@@ -378,4 +378,10 @@ static inline void tegra_dp_set_outdata(struct tegra_dc_dp_data *dp,
 #define NV_DPCD_HDCP_RXSTATUS                           (0x00069493)
 #define NV_DPCD_HDCP_RSVD                               (0x00069494)
 #define NV_DPCD_HDCP_DBG                                (0x00069518)
+
+int __attribute__((weak)) tegra_dp_init_max_link_cfg_t19x(
+                                        struct tegra_dc_dp_data *dp,
+                                        struct tegra_dc_dp_link_config *cfg);
+void tegra_dp_set_max_link_bw(struct tegra_dc_sor_data *sor,
+                              struct tegra_dc_dp_link_config *cfg);
 #endif
diff --git a/drivers/video/tegra/dc/dp_lt.c b/drivers/video/tegra/dc/dp_lt.c
index 8efad87ce..3997a6bfa 100644
--- a/drivers/video/tegra/dc/dp_lt.c
+++ b/drivers/video/tegra/dc/dp_lt.c
@@ -63,7 +63,8 @@ static inline bool is_pc2_supported(struct tegra_dp_lt_data *lt_data)
         struct tegra_dc_dp_link_config *cfg = &lt_data->dp->link_cfg;
         struct tegra_dp_out *dp_out = lt_data->dp->dc->out->dp_out;
 
-        return (!dp_out->pc2_disabled && cfg->tps3_supported);
+        return (!dp_out->pc2_disabled &&
+                cfg->tps == TEGRA_DC_DP_TRAINING_PATTERN_3);
 }
 
 /*
@@ -413,11 +414,8 @@ static int do_fast_lt_no_handshake(struct tegra_dp_lt_data *lt_data)
         set_lt_tpg(lt_data, TEGRA_DC_DP_TRAINING_PATTERN_1);
         usleep_range(500, 600);
 
-        /* transmit link training pattern 2/3 for min of 500us */
-        if (lt_data->dp->link_cfg.tps3_supported)
-                set_lt_tpg(lt_data, TEGRA_DC_DP_TRAINING_PATTERN_3);
-        else
-                set_lt_tpg(lt_data, TEGRA_DC_DP_TRAINING_PATTERN_2);
+        /* transmit channel equalization training pattern for min of 500us */
+        set_lt_tpg(lt_data, lt_data->dp->link_cfg.tps);
         usleep_range(500, 600);
 
         return 0;
@@ -692,7 +690,6 @@ static void lt_channel_equalization_state(struct tegra_dp_lt_data *lt_data)
 {
         int tgt_state;
         int timeout;
-        u32 tp_src = TEGRA_DC_DP_TRAINING_PATTERN_2;
         bool cr_done = true;
         bool ce_done = true;
         bool cur_hpd;
@@ -707,10 +704,7 @@ static void lt_channel_equalization_state(struct tegra_dp_lt_data *lt_data)
                 goto done;
         }
 
-        if (lt_data->dp->link_cfg.tps3_supported)
-                tp_src = TEGRA_DC_DP_TRAINING_PATTERN_3;
-
-        set_lt_tpg(lt_data, tp_src);
+        set_lt_tpg(lt_data, lt_data->dp->link_cfg.tps);
         wait_aux_training(lt_data, false);
 
         cr_done = get_clock_recovery_status(lt_data);
diff --git a/drivers/video/tegra/dc/dp_lt.h b/drivers/video/tegra/dc/dp_lt.h
index 9df98ecb4..4f1daa0d7 100644
--- a/drivers/video/tegra/dc/dp_lt.h
+++ b/drivers/video/tegra/dc/dp_lt.h
@@ -58,7 +58,6 @@ struct tegra_dp_lt_data {
         struct completion lt_complete;
 
         u8 no_aux_handshake;
-        u8 tps3_supported;
         u8 aux_rd_interval;
 
         bool lt_config_valid;
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index 7f8d9bf5e..abb321f67 100644
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -829,6 +829,9 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
 
         tegra_dc_populate_min_mode();
 
+        if (tegra_dc_is_t19x())
+                tegra_sor_init_quirks_t19x(sor);
+
         return sor;
 
 err_rst: __maybe_unused
diff --git a/drivers/video/tegra/dc/sor.h b/drivers/video/tegra/dc/sor.h
index 0147878ec..41c73faae 100644
--- a/drivers/video/tegra/dc/sor.h
+++ b/drivers/video/tegra/dc/sor.h
@@ -29,6 +29,9 @@
 #include "dc_priv.h"
 #include "sor_regs.h"
 
+/* Handle to a training pattern data object. Serves as the sole interface of
+ * APIs and data structures to the training pattern data object
+ */
 enum tegra_dc_dp_training_pattern_key {
         TEGRA_DC_DP_TRAINING_PATTERN_DISABLE,
         TEGRA_DC_DP_TRAINING_PATTERN_1,
@@ -41,6 +44,16 @@ enum tegra_dc_dp_training_pattern_key {
         TEGRA_DC_DP_TRAINING_PATTERN_HBR2_COMPLIANCE,
 };
 
+/*
+ * tegra_dc_dp_training_pattern - Training Pattern data object
+ * @dpcd_val    - DPCD value defined by DP spec, corresponding to the TPS
+ *                (Training Pattern Sequence). Used to hint the TPS to the sink
+ *                that the source intends to use for link training
+ * @sor_reg_val - SOR value corresponding to the TPS. Used to force the source
+ *                to use this TPS
+ * @scrambling  - Denotes whether the bit stream needs to be scrambled
+ * @chan_coding - Denotes whether the bit stream needs to be 8b/10b coded
+ */
 struct tegra_dc_dp_training_pattern {
         u8 dpcd_val;
         u8 sor_reg_val;
@@ -118,7 +131,12 @@ struct tegra_dc_dp_link_config {
         u32     preemphasis[4];
         u32     postcursor[4];
 
-        bool    tps3_supported;
+        /*
+         * Training Pattern Sequence to start channel equalization with,
+         * calculated based on an intersection of source and sink capabilities
+         */
+        u32     tps;
+
         u8      aux_rd_interval;
 };
 
@@ -249,6 +267,8 @@ u32 __attribute__((weak))
         tegra_sor_get_pixel_depth_t19x(struct tegra_dc *dc);
 u32 __attribute__((weak))
         tegra_sor_get_adjusted_hblank_t19x(struct tegra_dc *dc, u32 hblank_end);
+void __attribute__((weak)) tegra_sor_init_quirks_t19x(
+                                struct tegra_dc_sor_data *sor);
 
 static inline u32 nv_sor_head_state0(u32 i)
 {