EQOS: Enable DMA selection with filtering.

This change allows to configure filtering such that
specified  DMA channel is selected for packets which
match filtering criteria.

Bug 200743454

Change-Id: If990de0b499c36466258ce7f7cd79e1abe717537
Signed-off-by: Achal Verma <achalv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2575326
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Phoenix Jung <pjung@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 files changed, 521 insertions, 80 deletions

diff --git a/drivers/net/ethernet/nvidia/eqos/Makefile b/drivers/net/ethernet/nvidia/eqos/Makefile
index a954463fb..10d3f55d3 100644
--- a/drivers/net/ethernet/nvidia/eqos/Makefile
+++ b/drivers/net/ethernet/nvidia/eqos/Makefile
@@ -1,4 +1,4 @@
-# Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+# Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
 #
 # This program is free software; you can redistribute it and/or modify it
 # under the terms and conditions of the GNU General Public License,
@@ -15,7 +15,7 @@ ccflags-y += -DHWA_NV_1650337
 ccflags-y += -DHWA_FPGA_ONLY
 
 ## default build settings.
-ccflags-y += -DCONFIG_PTPSUPPORT_OBJ
+ccflags-y += -DCONFIG_PTPSUPPORT_OBJ -DFILTER_DEBUGFS
 
 ## enable this only for MODS verification
 ifeq ($(CONFIG_DISABLE_EQOS_CTRL_TRISTATE),y)
diff --git a/drivers/net/ethernet/nvidia/eqos/dev.c b/drivers/net/ethernet/nvidia/eqos/dev.c
index fd05f2dbf..e8eb921e9 100644
--- a/drivers/net/ethernet/nvidia/eqos/dev.c
+++ b/drivers/net/ethernet/nvidia/eqos/dev.c
@@ -429,6 +429,79 @@ static INT update_l4_sa_port_no(INT filter_no, USHORT port_no)
         return Y_SUCCESS;
 }
 
+/**
+ * @brief eqos_set_l3mask - update l3 filter address mask
+ *
+ * @note
+ * Algorithm:
+ *    This sequence is used to configure L3((IPv4/IPv6)
+ *    filter address mask for address matching.
+ *
+ * @param[in] value
+ * @param[in] l3_mask
+ *
+ * @note
+ * API Group:
+ * - Initialization: Yes
+ * - Run time: Yes
+ * - De-initialization: No
+ *
+ *@return updated UINT value
+ */
+
+static inline UINT eqos_set_l3mask(UINT value, USHORT l3_mask, BOOL is_dst)
+{
+        UINT t_val = value;
+
+        if (is_dst)
+                t_val |= ((l3_mask <<
+                        MAC_L3L4_CTR_L3HDBM0_SHIFT) &
+                        MAC_L3L4_CTR_L3HDBM0);
+        else
+                t_val |= ((l3_mask <<
+                        MAC_L3L4_CTR_L3HSBM0_SHIFT) &
+                        MAC_L3L4_CTR_L3HSBM0);
+
+        return t_val;
+}
+
+/**
+ * @brief eqos_set_dcs - update dma routing register
+ *
+ * @note
+ * Algorithm:
+ *    This sequence is used to configure L3((IPv4/IPv6)
+ *    filters for address matching.
+ *
+ * @param[in] value
+ * @param[in] dma_routing_enable
+ * @param[in] dma_chan
+ *
+ * @note
+ * API Group:
+ * - Initialization: Yes
+ * - Run time: Yes
+ * - De-initialization: No
+ *
+ *@return updated UINT value
+ */
+
+static inline UINT eqos_set_dcs(UINT value,
+                                UINT dma_routing_enable,
+                                UINT dma_chan)
+{
+        UINT t_val = value;
+
+        t_val |= ((dma_routing_enable <<
+                MAC_L3L4_CTR_DMCHEN0_SHIFT) &
+                MAC_L3L4_CTR_DMCHEN0);
+        t_val |= ((dma_chan <<
+                MAC_L3L4_CTR_DMCHN0_SHIFT) &
+                MAC_L3L4_CTR_DMCHN0);
+
+        return t_val;
+}
+
 /*!
 * \brief This sequence is used to configure L4(TCP/UDP) filters for
 * SA and DA Port Number matching
@@ -441,12 +514,12 @@ static INT update_l4_sa_port_no(INT filter_no, USHORT port_no)
 * \retval -1 Failure
 */
 
-static INT config_l4_filters(INT filter_no,
-                             INT enb_dis,
-                             INT tcp_udp_match,
-                             INT src_dst_port_match, INT perfect_inverse_match)
+static INT config_l4_filters(INT filter_no, INT enb_dis,
+                             INT tcp_udp_match, INT src_dst_port_match,
+                             INT perfect_inverse_match, INT dma_routing_enable,
+                             USHORT dma_channel)
 {
-
+        UINT val = 0U;
         MAC_L3L4CR_L4PEN0_WR(filter_no, tcp_udp_match);
 
         if (src_dst_port_match == 0) {
@@ -454,6 +527,10 @@ static INT config_l4_filters(INT filter_no,
                         /* Enable L4 filters for SOURCE Port No matching */
                         MAC_L3L4CR_L4SPM0_WR(filter_no, 0x1);
                         MAC_L3L4CR_L4SPIM0_WR(filter_no, perfect_inverse_match);
+                        MAC_L3L4CR_RD(filter_no, val);
+                        val = eqos_set_dcs(val, dma_routing_enable,
+                                                        dma_channel);
+                        MAC_L3L4CR_WR(filter_no, val);
                 } else {
                         /* Disable L4 filters for SOURCE Port No matching */
                         MAC_L3L4CR_L4SPM0_WR(filter_no, 0x0);
@@ -464,6 +541,10 @@ static INT config_l4_filters(INT filter_no,
                         /* Enable L4 filters for DESTINATION port No matching */
                         MAC_L3L4CR_L4DPM0_WR(filter_no, 0x1);
                         MAC_L3L4CR_L4DPIM0_WR(filter_no, perfect_inverse_match);
+                        MAC_L3L4CR_RD(filter_no, val);
+                        val = eqos_set_dcs(val, dma_routing_enable,
+                                                        dma_channel);
+                        MAC_L3L4CR_WR(filter_no, val);
                 } else {
                         /* Disable L4 filters for DESTINATION port No matching */
                         MAC_L3L4CR_L4DPM0_WR(filter_no, 0x0);
@@ -548,8 +629,13 @@ static INT update_ip4_addr0(INT filter_no, UCHAR addr[])
 static INT config_l3_filters(INT filter_no,
                              INT enb_dis,
                              INT ipv4_ipv6_match,
-                             INT src_dst_addr_match, INT perfect_inverse_match)
+                             INT src_dst_addr_match,
+                             INT perfect_inverse_match,
+                             INT dma_routing_enable,
+                             USHORT dma_channel,
+                             USHORT l3_mask)
 {
+        UINT val = 0U;
         MAC_L3L4CR_L3PEN0_WR(filter_no, ipv4_ipv6_match);
 
         /* For IPv6 either SA/DA can be checked, not both */
@@ -559,16 +645,24 @@ static INT config_l3_filters(INT filter_no,
                                 /* Enable L3 filters for IPv6 SOURCE addr matching */
                                 MAC_L3L4CR_L3SAM0_WR(filter_no, 0x1);
                                 MAC_L3L4CR_L3SAIM0_WR(filter_no,
-                                                      perfect_inverse_match);
+                                              perfect_inverse_match);
                                 MAC_L3L4CR_L3DAM0_WR(filter_no, 0x0);
                                 MAC_L3L4CR_L3DAIM0_WR(filter_no, 0x0);
+                                MAC_L3L4CR_RD(filter_no, val);
+                                val = eqos_set_dcs(val, dma_routing_enable,
+                                                                dma_channel);
+                                MAC_L3L4CR_WR(filter_no, val);
                         } else {
                                 /* Enable L3 filters for IPv6 DESTINATION addr matching */
                                 MAC_L3L4CR_L3SAM0_WR(filter_no, 0x0);
                                 MAC_L3L4CR_L3SAIM0_WR(filter_no, 0x0);
                                 MAC_L3L4CR_L3DAM0_WR(filter_no, 0x1);
                                 MAC_L3L4CR_L3DAIM0_WR(filter_no,
-                                                      perfect_inverse_match);
+                                              perfect_inverse_match);
+                                MAC_L3L4CR_RD(filter_no, val);
+                                val = eqos_set_dcs(val, dma_routing_enable,
+                                                                dma_channel);
+                                MAC_L3L4CR_WR(filter_no, val);
                         }
                 } else {
                         /* Disable L3 filters for IPv6 SOURCE/DESTINATION addr matching */
@@ -584,7 +678,14 @@ static INT config_l3_filters(INT filter_no,
                                 /* Enable L3 filters for IPv4 SOURCE addr matching */
                                 MAC_L3L4CR_L3SAM0_WR(filter_no, 0x1);
                                 MAC_L3L4CR_L3SAIM0_WR(filter_no,
-                                                      perfect_inverse_match);
+                                              perfect_inverse_match);
+                                MAC_L3L4CR_L3HSBM0_WR(filter_no, l3_mask);
+                                MAC_L3L4CR_RD(filter_no, val);
+                                val = eqos_set_dcs(val, dma_routing_enable,
+                                                                dma_channel);
+                                val = eqos_set_l3mask(val, l3_mask,
+                                                src_dst_addr_match);
+                                MAC_L3L4CR_WR(filter_no, val);
                         } else {
                                 /* Disable L3 filters for IPv4 SOURCE addr matching */
                                 MAC_L3L4CR_L3SAM0_WR(filter_no, 0x0);
@@ -596,6 +697,12 @@ static INT config_l3_filters(INT filter_no,
                                 MAC_L3L4CR_L3DAM0_WR(filter_no, 0x1);
                                 MAC_L3L4CR_L3DAIM0_WR(filter_no,
                                                       perfect_inverse_match);
+                                MAC_L3L4CR_RD(filter_no, val);
+                                val = eqos_set_dcs(val, dma_routing_enable,
+                                                                dma_channel);
+                                val = eqos_set_l3mask(val, l3_mask,
+                                                src_dst_addr_match);
+                                MAC_L3L4CR_WR(filter_no, val);
                         } else {
                                 /* Disable L3 filters for IPv4 DESTINATION addr matching */
                                 MAC_L3L4CR_L3DAM0_WR(filter_no, 0x0);
@@ -3848,7 +3955,8 @@ static INT configure_mac(struct eqos_prv_data *pdata)
 
 static INT eqos_yinit(struct eqos_prv_data *pdata)
 {
-        UINT qinx;
+        struct eqos_cfg *dt_cfg = &pdata->dt_cfg;
+        UINT qinx, val = 0U;
         int i, j;
 
         pr_debug("-->eqos_yinit\n");
@@ -3859,8 +3967,17 @@ static INT eqos_yinit(struct eqos_prv_data *pdata)
         for (qinx = 0; qinx < EQOS_TX_QUEUE_CNT; qinx++) {
                 configure_mtl_queue(qinx, pdata);
         }
-        /* Mapping MTL Rx queue and DMA Rx channel */
-        MTL_RQDCM0R_WR(0x3020100);
+        /* Mapping MTL Rx queue and DMA Rx channel
+         * dt entry queue_dma_map defines 0 for static
+         * 1 for dynamic queue to dma mapping.
+         * For static case queue n is mapped to dma channel n
+         */
+        val = ((dt_cfg->q_dma_map[3] ? BIT(28) : (3 << 24))  |  \
+                (dt_cfg->q_dma_map[2] ? BIT(20) : (2 << 16)) | \
+                (dt_cfg->q_dma_map[1] ? BIT(12) : (1 << 8)) | \
+                (dt_cfg->q_dma_map[0] ? BIT(4) : (0)));
+
+        MTL_RQDCM0R_WR(val);
 
         i = (VIRT_INTR_CH_CRTL_RX_WR_MASK | VIRT_INTR_CH_CRTL_TX_WR_MASK);
         for (j = 0; j < pdata->num_chans; j++) {
diff --git a/drivers/net/ethernet/nvidia/eqos/drv.c b/drivers/net/ethernet/nvidia/eqos/drv.c
index 7e2d80c75..7c7bb2605 100644
--- a/drivers/net/ethernet/nvidia/eqos/drv.c
+++ b/drivers/net/ethernet/nvidia/eqos/drv.c
@@ -47,6 +47,9 @@
 #include <linux/gpio.h>
 #include <linux/time.h>
 #include <linux/platform/tegra/ptp-notifier.h>
+#ifdef FILTER_DEBUGFS
+#include <linux/debugfs.h>
+#endif
 #include <linux/reset.h>
 #include "yheader.h"
 #include "yapphdr.h"
@@ -2604,6 +2607,152 @@ static int eqos_config_l3_l4_filtering(struct net_device *dev,
         return ret;
 }
 
+#ifdef FILTER_DEBUGFS
+struct fdata {
+        struct dentry *entry;
+        int index;
+        int type;
+        size_t size;
+        char name[64];
+        struct list_head list;
+};
+
+static int __eqos_debugfs_show(struct seq_file *file, void *unused)
+{
+        struct fdata *data = file->private;
+        struct eqos_l3_l4_filter *f = (struct eqos_l3_l4_filter *)(data + 1);
+
+        switch (data->type) {
+        case 0:
+                seq_printf(file, "Layer 3 filter\n");
+                seq_printf(file,
+        "..filter_no = %d\n..enable? = %s\n..src/dst = %s\n..type = %s\n"
+        "..ip = %d.%d.%d.%d\n..mask = %d\n..dma routing? = %s\n..dma = %d\n",
+        f->filter_no, f->filter_enb_dis ? "YES" : "NO",
+        f->src_dst_addr_match == 0 ? "SOURCE" : "DESTINATION",
+        f->perfect_inverse_match == 0 ? "PERFECT" : "INVERSE",
+        f->ip4_addr[0], f->ip4_addr[1], f->ip4_addr[2], f->ip4_addr[3],
+        f->l3_mask, f->dma_routing_enable ? "YES" : "NO",
+        f->dma_channel);
+                break;
+
+        case 1:
+                seq_printf(file, "Layer 4 filter\n");
+                seq_printf(file,
+        "..filter_no = %d\n..enable? = %s\n..src/dst = %s\n..type = %s\n"
+        "..port = %d\n..dma routing? = %s\n..dma = %d\n",
+        f->filter_no, f->filter_enb_dis ? "YES" : "NO",
+        f->src_dst_addr_match == 0 ? "SOURCE" : "DESTINATION",
+        f->perfect_inverse_match == 0 ? "PERFECT" : "INVERSE",
+        f->port_no, f->dma_routing_enable ? "YES" : "NO",
+        f->dma_channel);
+                break;
+
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int __eqos_debugfs_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, __eqos_debugfs_show, inode->i_private);
+}
+
+static const struct file_operations __eqos_filter_fops = {
+        .open       = __eqos_debugfs_open,
+        .read       = seq_read,
+        .llseek     = seq_lseek,
+        .release    = single_release,
+};
+
+static int __eqos_debugfs_filter(struct eqos_prv_data *pdata, int index,
+                                        int type, void *data,  size_t sz)
+{
+        struct fdata *pos, *new;
+
+        list_for_each_entry(pos, &pdata->d_head, list) {
+                if (pos->type == type && pos->index == index) {
+                        debugfs_remove_recursive(pos->entry);
+                        list_del_init(&pos->list);
+                        devm_kfree(&pdata->pdev->dev, pos);
+                        break;
+                }
+        }
+        new = devm_kzalloc(&pdata->pdev->dev, sizeof *new + sz, GFP_KERNEL);
+        if (!new)
+                return -ENOMEM;
+        new->type = type;
+        new->index = index;
+        memcpy(new + 1, data, sz);
+        snprintf(new->name, sizeof(new->name), "filter_%02d", index);
+        new->entry = debugfs_create_file(new->name, 0440, pdata->d_root, new,
+                        &__eqos_filter_fops);
+        INIT_LIST_HEAD(&new->list);
+        list_add(&new->list, &pdata->d_head);
+        return 0;
+}
+#endif
+
+static int __eqos_config_ip4_filters(struct eqos_prv_data *pdata,
+                                   struct eqos_l3_l4_filter *l3_filter)
+{
+        struct hw_if_struct *hw_if = &(pdata->hw_if);
+        int ret = 0;
+
+        if (pdata->hw_feat.l3l4_filter_num == 0)
+                return EQOS_NO_HW_SUPPORT;
+
+        if ((l3_filter->filter_no + 1) > pdata->hw_feat.l3l4_filter_num) {
+                pr_err("%d filter is not supported in the HW\n",
+                       l3_filter->filter_no);
+                return EQOS_NO_HW_SUPPORT;
+        }
+
+        if ((l3_filter->dma_routing_enable == EQOS_DMA_FILTER_ENABLE) &&
+                (l3_filter->dma_channel > (pdata->hw_feat.rx_ch_cnt))) {
+                pr_err("%u dma channel is not supported in the HW\n",
+                        l3_filter->dma_channel);
+                return EQOS_NO_HW_SUPPORT;
+        }
+
+
+        if (!pdata->l3_l4_filter) {
+                hw_if->config_l3_l4_filter_enable(1);
+                pdata->l3_l4_filter = 1;
+        }
+
+        /* configure the L3 filters */
+        hw_if->config_l3_filters(l3_filter->filter_no,
+                                 l3_filter->filter_enb_dis, 0,
+                                 l3_filter->src_dst_addr_match,
+                                 l3_filter->perfect_inverse_match,
+                                 l3_filter->dma_routing_enable,
+                                 l3_filter->dma_channel,
+                                 l3_filter->l3_mask);
+
+        if (!l3_filter->src_dst_addr_match)
+                hw_if->update_ip4_addr0(l3_filter->filter_no,
+                                        l3_filter->ip4_addr);
+        else
+                hw_if->update_ip4_addr1(l3_filter->filter_no,
+                                        l3_filter->ip4_addr);
+#ifdef FILTER_DEBUGFS
+        __eqos_debugfs_filter(pdata, l3_filter->filter_no, 0, l3_filter,
+                                sizeof(*l3_filter));
+#endif
+
+        DBGPR_FILTER
+            ("Successfully %s IPv4 %s %s addressing filtering on %d filter\n",
+             (l3_filter->filter_enb_dis ? "ENABLED" : "DISABLED"),
+             (l3_filter->perfect_inverse_match ? "INVERSE" : "PERFECT"),
+             (l3_filter->src_dst_addr_match ? "DESTINATION" : "SOURCE"),
+             l3_filter->filter_no);
+
+        return ret;
+}
+
 /*!
  * \details This function is invoked by ioctl function when user issues an
  * ioctl command to configure L3(IPv4) filtering. This function does following,
@@ -2623,7 +2772,6 @@ static int eqos_config_ip4_filters(struct net_device *dev,
                                    struct ifr_data_struct *req)
 {
         struct eqos_prv_data *pdata = netdev_priv(dev);
-        struct hw_if_struct *hw_if = &(pdata->hw_if);
         struct eqos_l3_l4_filter *u_l3_filter =
             (struct eqos_l3_l4_filter *)req->ptr;
         struct eqos_l3_l4_filter l_l3_filter;
@@ -2638,36 +2786,7 @@ static int eqos_config_ip4_filters(struct net_device *dev,
                            sizeof(struct eqos_l3_l4_filter)))
                 return -EFAULT;
 
-        if ((l_l3_filter.filter_no + 1) > pdata->hw_feat.l3l4_filter_num) {
-                pr_err("%d filter is not supported in the HW\n",
-                       l_l3_filter.filter_no);
-                return EQOS_NO_HW_SUPPORT;
-        }
-
-        if (!pdata->l3_l4_filter) {
-                hw_if->config_l3_l4_filter_enable(1);
-                pdata->l3_l4_filter = 1;
-        }
-
-        /* configure the L3 filters */
-        hw_if->config_l3_filters(l_l3_filter.filter_no,
-                                 l_l3_filter.filter_enb_dis, 0,
-                                 l_l3_filter.src_dst_addr_match,
-                                 l_l3_filter.perfect_inverse_match);
-
-        if (!l_l3_filter.src_dst_addr_match)
-                hw_if->update_ip4_addr0(l_l3_filter.filter_no,
-                                        l_l3_filter.ip4_addr);
-        else
-                hw_if->update_ip4_addr1(l_l3_filter.filter_no,
-                                        l_l3_filter.ip4_addr);
-
-        DBGPR_FILTER
-            ("Successfully %s IPv4 %s %s addressing filtering on %d filter\n",
-             (l_l3_filter.filter_enb_dis ? "ENABLED" : "DISABLED"),
-             (l_l3_filter.perfect_inverse_match ? "INVERSE" : "PERFECT"),
-             (l_l3_filter.src_dst_addr_match ? "DESTINATION" : "SOURCE"),
-             l_l3_filter.filter_no);
+        ret = __eqos_config_ip4_filters(pdata, &l_l3_filter);
 
         DBGPR_FILTER("<--eqos_config_ip4_filters\n");
 
@@ -2723,7 +2842,10 @@ static int eqos_config_ip6_filters(struct net_device *dev,
         hw_if->config_l3_filters(l_l3_filter.filter_no,
                                  l_l3_filter.filter_enb_dis, 1,
                                  l_l3_filter.src_dst_addr_match,
-                                 l_l3_filter.perfect_inverse_match);
+                                 l_l3_filter.perfect_inverse_match,
+                                 l_l3_filter.dma_routing_enable,
+                                 l_l3_filter.dma_channel,
+                                 l_l3_filter.l3_mask);
 
         hw_if->update_ip6_addr(l_l3_filter.filter_no, l_l3_filter.ip6_addr);
 
@@ -2739,6 +2861,65 @@ static int eqos_config_ip6_filters(struct net_device *dev,
         return ret;
 }
 
+static int __eqos_config_tcp_udp_filters(struct eqos_prv_data *pdata,
+                       struct eqos_l3_l4_filter *l4_filter, int tcp_udp)
+
+{
+        struct hw_if_struct *hw_if = &(pdata->hw_if);
+        int ret = 0;
+
+        if (pdata->hw_feat.l3l4_filter_num == 0)
+                return EQOS_NO_HW_SUPPORT;
+
+        if ((l4_filter->filter_no + 1) > pdata->hw_feat.l3l4_filter_num) {
+                pr_err("%d filter is not supported in the HW\n",
+                       l4_filter->filter_no);
+                return EQOS_NO_HW_SUPPORT;
+        }
+
+        if ((l4_filter->dma_routing_enable == EQOS_DMA_FILTER_ENABLE) &&
+                (l4_filter->dma_channel > (pdata->hw_feat.rx_ch_cnt))) {
+                pr_err("%u dma channel is not supported in the HW\n",
+                        l4_filter->dma_channel);
+                return EQOS_NO_HW_SUPPORT;
+        }
+
+        if (!pdata->l3_l4_filter) {
+                hw_if->config_l3_l4_filter_enable(1);
+                pdata->l3_l4_filter = 1;
+        }
+
+        /* configure the L4 filters */
+        hw_if->config_l4_filters(l4_filter->filter_no,
+                                 l4_filter->filter_enb_dis,
+                                 tcp_udp,
+                                 l4_filter->src_dst_addr_match,
+                                 l4_filter->perfect_inverse_match,
+                                 l4_filter->dma_routing_enable,
+                                 l4_filter->dma_channel);
+
+        if (l4_filter->src_dst_addr_match)
+                hw_if->update_l4_da_port_no(l4_filter->filter_no,
+                                            l4_filter->port_no);
+        else
+                hw_if->update_l4_sa_port_no(l4_filter->filter_no,
+                                            l4_filter->port_no);
+
+#ifdef FILTER_DEBUGFS
+        __eqos_debugfs_filter(pdata, l4_filter->filter_no, 1, l4_filter,
+                                sizeof(*l4_filter));
+#endif
+        DBGPR_FILTER
+            ("Successfully %s %s %s %s Port number filtering on %d filter\n",
+             (l4_filter->filter_enb_dis ? "ENABLED" : "DISABLED"),
+             (tcp_udp ? "UDP" : "TCP"),
+             (l4_filter->perfect_inverse_match ? "INVERSE" : "PERFECT"),
+             (l4_filter->src_dst_addr_match ? "DESTINATION" : "SOURCE"),
+             l4_filter->filter_no);
+
+        return ret;
+}
+
 /*!
  * \details This function is invoked by ioctl function when user issues an
  * ioctl command to configure L4(TCP/UDP) filtering. This function does following,
@@ -2786,27 +2967,7 @@ static int eqos_config_tcp_udp_filters(struct net_device *dev,
                 pdata->l3_l4_filter = 1;
         }
 
-        /* configure the L4 filters */
-        hw_if->config_l4_filters(l_l4_filter.filter_no,
-                                 l_l4_filter.filter_enb_dis,
-                                 tcp_udp,
-                                 l_l4_filter.src_dst_addr_match,
-                                 l_l4_filter.perfect_inverse_match);
-
-        if (l_l4_filter.src_dst_addr_match)
-                hw_if->update_l4_da_port_no(l_l4_filter.filter_no,
-                                            l_l4_filter.port_no);
-        else
-                hw_if->update_l4_sa_port_no(l_l4_filter.filter_no,
-                                            l_l4_filter.port_no);
-
-        DBGPR_FILTER
-            ("Successfully %s %s %s %s Port number filtering on %d filter\n",
-             (l_l4_filter.filter_enb_dis ? "ENABLED" : "DISABLED"),
-             (tcp_udp ? "UDP" : "TCP"),
-             (l_l4_filter.perfect_inverse_match ? "INVERSE" : "PERFECT"),
-             (l_l4_filter.src_dst_addr_match ? "DESTINATION" : "SOURCE"),
-             l_l4_filter.filter_no);
+        ret = __eqos_config_tcp_udp_filters(pdata, &l_l4_filter, tcp_udp);
 
         DBGPR_FILTER("<--eqos_config_tcp_udp_filters\n");
 
@@ -5430,6 +5591,101 @@ void eqos_stop_dev(struct eqos_prv_data *pdata)
         pr_debug("<--%s()\n", __func__);
 }
 
+void get_configure_l3v4_filter(struct eqos_prv_data *pdata)
+{
+        struct eqos_l3_l4_filter l3_l4_filter;
+        int i, filter_nums;
+        u32 filters[EQOS_MAX_L3_L4_FILTER][3] = { {0} };
+        struct device_node *pnode = pdata->pdev->dev.of_node;
+
+        dev_info(&pdata->dev->dev, "%s -->", __func__);
+
+        /* nvidia,filters = < filter_conf IP_addr Port_num >
+         * filter conf bits :
+         * 2     -> src/dst
+         * 3     -> enable/disable
+         * 4     -> perfect/inverse
+         * 5     -> dma_routing_enable
+         * 8:6   -> dma_channel
+         * 9     -> ipv4/ipv6
+         * 10    -> tcp/udp
+         * 15:11 -> Mask Value for L3 filter address
+         *          holds mask for L3 filter, 0 -> 31
+         *          0: No bits are masked
+         *          1: LSb[0] is maksed
+         *          2: LSb[1:0] are masked
+         *          ....
+         *          31: LSb[0:30] are masked , leaving only bit 31
+         *
+         * 26:24 -> L3/L4
+         * 30:28 -> filter number
+         */
+
+        filter_nums = of_property_read_variable_u32_array(pnode,
+                        "nvidia,filters", (u32 *)filters, 3,
+                        EQOS_MAX_L3_L4_FILTER * 3);
+
+        if (filter_nums < 0 || ((filter_nums % 3) != 0)) {
+                if (filter_nums != -EINVAL)
+                        dev_err(&pdata->pdev->dev,
+                        "%s: nvidia,filters read failed\n", __func__);
+                return;
+        }
+
+        filter_nums /= 3;
+
+        for (i = 0; i < filter_nums; i += 1) {
+                u32 cur_filter = filters[i][0];
+                u8 type = (u8)((cur_filter >> 24) & 0x7);
+
+                if (cur_filter & (1U << 9)) {
+                        dev_err(&pdata->pdev->dev, "Filter %d failed," \
+                        " IPV6 not supported\n", ((cur_filter >> 28) & 0x7));
+                        continue;
+                }
+
+                memset(&l3_l4_filter, 0, sizeof(l3_l4_filter));
+                l3_l4_filter.filter_no =  ((cur_filter >> 28) & 0x7);
+                l3_l4_filter.filter_enb_dis = ((cur_filter >> 3) & 0x1);
+                l3_l4_filter.src_dst_addr_match = ((cur_filter >> 2) & 0x1);
+                l3_l4_filter.perfect_inverse_match = ((cur_filter >> 4) & 0x1);
+                l3_l4_filter.dma_routing_enable = ((cur_filter >> 5) & 0x1);
+                l3_l4_filter.dma_channel = ((cur_filter >> 6) & 0x7);
+
+                /* L3 Filter */
+                if (!type) {
+                        l3_l4_filter.ip4_addr[0] = ((u8 *)&filters[i][1])[3];
+                        l3_l4_filter.ip4_addr[1] = ((u8 *)&filters[i][1])[2];
+                        l3_l4_filter.ip4_addr[2] = ((u8 *)&filters[i][1])[1];
+                        l3_l4_filter.ip4_addr[3] = ((u8 *)&filters[i][1])[0];
+                        l3_l4_filter.l3_mask =  ((cur_filter >> 11) & 0x1f);
+
+                        if (__eqos_config_ip4_filters(pdata, &l3_l4_filter))
+                                dev_err(&pdata->pdev->dev,
+                                        "%s: Failed to configure filter %d\n",
+                                        __func__,  l3_l4_filter.filter_no);
+
+                /* L4 Filter */
+                } else if (type == 1) {
+                        int is_udp = ((cur_filter >> 10) & 0x1);
+
+                        l3_l4_filter.port_no = filters[i][2];
+
+                        if (__eqos_config_tcp_udp_filters(pdata, &l3_l4_filter,
+                                                                        is_udp))
+                                dev_err(&pdata->pdev->dev,
+                                        "%s: Failed to configure filter %d\n",
+                                        __func__,  l3_l4_filter.filter_no);
+
+                /* Unsupported filter type */
+                } else {
+                        dev_err(&pdata->pdev->dev,
+                                "%s: Wrong filter type %u for filter %d\n",
+                                __func__, type, l3_l4_filter.filter_no);
+                }
+        }
+}
+
 void eqos_start_dev(struct eqos_prv_data *pdata)
 {
         struct hw_if_struct *hw_if = &pdata->hw_if;
@@ -5455,6 +5711,8 @@ void eqos_start_dev(struct eqos_prv_data *pdata)
         /* initializes MAC and DMA */
         hw_if->init(pdata);
 
+        get_configure_l3v4_filter(pdata);
+
         MAC_1US_TIC_WR(pdata->csr_clock_speed - 1);
 
         if (pdata->hw_feat.pcs_sel)
diff --git a/drivers/net/ethernet/nvidia/eqos/init.c b/drivers/net/ethernet/nvidia/eqos/init.c
index b4c7e61f7..596d1da16 100644
--- a/drivers/net/ethernet/nvidia/eqos/init.c
+++ b/drivers/net/ethernet/nvidia/eqos/init.c
@@ -62,6 +62,9 @@
 #include <linux/workqueue.h>
 #include <linux/tegra_prod.h>
 #include <linux/of_net.h>
+#ifdef FILTER_DEBUGFS
+#include <linux/debugfs.h>
+#endif
 
 #define LP_SUPPORTED 0
 static const struct of_device_id eqos_of_match[] = {
@@ -182,8 +185,9 @@ void get_dt_u32_array(struct eqos_prv_data *pdata, char *pdt_prop, u32 *pval,
         ret = of_property_read_u32_array(pnode, pdt_prop, pval, num_entries);
 
         if (ret < 0) {
-                pr_err("%s(): \"%s\" read failed %d. Using default\n",
-                        __func__, pdt_prop, ret);
+                if (ret != -EINVAL)
+                        pr_err("%s(): \"%s\" read failed %d. Using default\n",
+                                __func__, pdt_prop, ret);
                 for (i = 0; i < num_entries; i++)
                         pval[i] = val_def;
         }
@@ -1137,6 +1141,13 @@ int eqos_probe(struct platform_device *pdev)
         pdata->pdev = pdev;
 
         pdata->dev = ndev;
+#ifdef FILTER_DEBUGFS
+        pdata->d_root = debugfs_create_dir(dev_name(&pdev->dev), NULL);
+        if (IS_ERR_OR_NULL(pdata->d_root))
+                dev_warn(&pdev->dev, "debugfs_create_dir failed: %ld\n",
+                                                PTR_ERR(pdata->d_root));
+        INIT_LIST_HEAD(&pdata->d_head);
+#endif
 
         for (i = 0; i < num_chans; i++)
                 spin_lock_init(&pdata->chan_irq_lock[i]);
@@ -1233,12 +1244,10 @@ int eqos_probe(struct platform_device *pdev)
         ret = hw_if->pad_calibrate(pdata);
         if (ret < 0)
                 goto err_out_pad_calibrate_failed;
-
 #ifdef EQOS_CONFIG_DEBUGFS
-        /* to give prv data to debugfs */
+        /* To give prv data to debugfs */
         eqos_get_pdata(pdata);
 #endif
-
         ndev->irq = irq;
         pdata->common_irq = irq;
 
@@ -1291,6 +1300,8 @@ int eqos_probe(struct platform_device *pdev)
                         RXQ_CTRL_DEFAULT, RXQ_CTRL_MAX, 4);
         get_dt_u32_array(pdata, "nvidia,queue_prio", pdt_cfg->q_prio,
                         QUEUE_PRIO_DEFAULT, QUEUE_PRIO_MAX, 4);
+        get_dt_u32_array(pdata, "nvidia,queue_dma_map", pdt_cfg->q_dma_map,
+                        STATIC_Q_DMA_MAP, DYNAMIC_Q_DMA_MAP, 4);
         get_dt_u32(pdata, "nvidia,iso_bw", &pdt_cfg->iso_bw, ISO_BW_DEFAULT,
                 ISO_BW_DEFAULT);
         get_dt_u32(pdata, "nvidia,eth_iso_enable", &pdt_cfg->eth_iso_enable, 0,
@@ -1300,7 +1311,7 @@ int eqos_probe(struct platform_device *pdev)
                            &pdt_cfg->slot_intvl_val,
                            SLOT_INTVL_DEFAULT, SLOT_INTVL_MAX);
         pdata->dt_cfg.phy_apd_mode = of_property_read_bool(node,
-                                                           "nvidia,brcm_phy_apd_mode");
+                                           "nvidia,brcm_phy_apd_mode");
         eqos_get_slot_num_check_queues(pdata, pdt_cfg->slot_num_check);
 
 #ifndef DISABLE_TRISTATE
@@ -1452,7 +1463,7 @@ int eqos_probe(struct platform_device *pdev)
                         dev_err(&pdata->pdev->dev,
                                 "Failed to register attributes: %d\n", ret);
                         goto err_sysfs_create_failed;
-                        }
+                }
         }
 
         spin_lock_init(&pdata->lock);
@@ -1554,6 +1565,10 @@ int eqos_probe(struct platform_device *pdev)
         if (!tegra_platform_is_unit_fpga())
                 eqos_regulator_deinit(pdata);
  err_out_regulator_en_failed:
+#ifdef FILTER_DEBUGFS
+        if (!IS_ERR_OR_NULL(pdata->d_root))
+                debugfs_remove_recursive(pdata->d_root);
+#endif
         free_netdev(ndev);
         platform_set_drvdata(pdev, NULL);
 
@@ -1594,6 +1609,10 @@ int eqos_remove(struct platform_device *pdev)
 
         ndev = platform_get_drvdata(pdev);
         pdata = netdev_priv(ndev);
+#ifdef FILTER_DEBUGFS
+        if (!IS_ERR_OR_NULL(pdata->d_root))
+                debugfs_remove_recursive(pdata->d_root);
+#endif
         pdt_cfg = (struct eqos_cfg *)&pdata->dt_cfg;
         desc_if = &(pdata->desc_if);
 
diff --git a/drivers/net/ethernet/nvidia/eqos/yapphdr.h b/drivers/net/ethernet/nvidia/eqos/yapphdr.h
index 4b25f3518..6b0b29b94 100644
--- a/drivers/net/ethernet/nvidia/eqos/yapphdr.h
+++ b/drivers/net/ethernet/nvidia/eqos/yapphdr.h
@@ -30,7 +30,7 @@
  * =========================================================================
  */
 /*
- * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -212,6 +212,10 @@
 #define EQOS_L3_L4_FILTER_DISABLE 0x0
 #define EQOS_L3_L4_FILTER_ENABLE 0x1
 
+/* DMA Routing operations */
+#define EQOS_DMA_FILTER_DISABLE 0x0
+#define EQOS_DMA_FILTER_ENABLE 0x1
+
 /* Loopback mode */
 #define EQOS_MAC_LOOPBACK_DISABLE 0x0
 #define EQOS_MAC_LOOPBACK_ENABLE 0x1
@@ -331,6 +335,21 @@ struct eqos_l3_l4_filter {
 
         /* TCP/UDP src/dst port number */
         unsigned short port_no;
+
+        /* 0 - disable and 1 - enable */
+        int dma_routing_enable;
+
+        /* To hold DMA channel */
+        unsigned short dma_channel;
+
+        /* holds mask for L3 filter, 0 -> 31
+         * 0: No bits are masked
+         * 1: LSb[0] is maksed
+         * 2: LSb[1:0] are masked
+         * ....
+         * 31: LSb[0:30] are masked , leaving only 31 bit
+         */
+        unsigned short l3_mask;
 };
 
 struct eqos_vlan_filter {
diff --git a/drivers/net/ethernet/nvidia/eqos/yheader.h b/drivers/net/ethernet/nvidia/eqos/yheader.h
index f6e1794b2..1c14162e3 100644
--- a/drivers/net/ethernet/nvidia/eqos/yheader.h
+++ b/drivers/net/ethernet/nvidia/eqos/yheader.h
@@ -584,6 +584,9 @@
 /* Hash Table Reg count */
 #define EQOS_HTR_CNT (pdata->max_hash_table_size/32)
 
+/* MAX L3/L4 filters support */
+#define EQOS_MAX_L3_L4_FILTER           8U
+
 /* For handling VLAN filtering */
 #define EQOS_VLAN_PERFECT_FILTERING 0
 #define EQOS_VLAN_HASH_FILTERING 1
@@ -903,13 +906,16 @@ struct hw_if_struct {
         INT(*config_mac_pkt_filter_reg)(UCHAR, UCHAR, UCHAR, UCHAR, UCHAR);
         INT(*config_l3_l4_filter_enable)(INT);
         INT(*config_l3_filters)(INT filter_no, INT enb_dis, INT ipv4_ipv6_match,
-                     INT src_dst_addr_match, INT perfect_inverse_match);
+                        INT src_dst_addr_match, INT perfect_inverse_match,
+                        INT dma_routing_enable, USHORT dma_channel,
+                        USHORT l3_mask);
         INT(*update_ip4_addr0)(INT filter_no, UCHAR addr[]);
         INT(*update_ip4_addr1)(INT filter_no, UCHAR addr[]);
         INT(*update_ip6_addr)(INT filter_no, USHORT addr[]);
-        INT(*config_l4_filters)(INT filter_no, INT enb_dis,
-                INT tcp_udp_match, INT src_dst_port_match,
-                INT perfect_inverse_match);
+        INT(*config_l4_filters)(INT filter_no, INT enb_dis, INT tcp_udp_match,
+                                INT src_dst_port_match,
+                                INT perfect_inverse_match,
+                                INT dma_routing_enable, USHORT dma_channel);
         INT(*update_l4_sa_port_no)(INT filter_no, USHORT port_no);
         INT(*update_l4_da_port_no)(INT filter_no, USHORT port_no);
 
@@ -1342,6 +1348,8 @@ typedef enum {
 } pause_frames_e;
 #define PAUSE_FRAMES_DEFAULT PAUSE_FRAMES_ENABLED
 
+#define STATIC_Q_DMA_MAP 0
+#define DYNAMIC_Q_DMA_MAP 1
 #define QUEUE_PRIO_DEFAULT 0
 #define QUEUE_PRIO_MAX 7
 #define CHAN_NAPI_QUOTA_DEFAULT 64
@@ -1352,6 +1360,7 @@ typedef enum {
 struct eqos_cfg {
         bool    use_multi_q;    /* 0=single queue, jumbo frames enabled */
         rxq_ctrl_e      rxq_ctrl[MAX_CHANS];
+        uint            q_dma_map[MAX_CHANS];
         uint            q_prio[MAX_CHANS];
         uint            chan_napi_quota[MAX_CHANS];
         uint            slot_num_check[MAX_CHANS];
@@ -1587,6 +1596,11 @@ struct eqos_prv_data {
         /** Reserve SKB pointer and DMA */
         struct sk_buff *resv_skb;
         dma_addr_t resv_dma;
+        /* debugfs */
+#ifdef FILTER_DEBUGFS
+        struct dentry *d_root;
+        struct list_head d_head;
+#endif
 };
 
 typedef enum {
diff --git a/drivers/net/ethernet/nvidia/eqos/yregacc.h b/drivers/net/ethernet/nvidia/eqos/yregacc.h
index 0cbe363dd..18dfb14fe 100644
--- a/drivers/net/ethernet/nvidia/eqos/yregacc.h
+++ b/drivers/net/ethernet/nvidia/eqos/yregacc.h
@@ -30,7 +30,7 @@
  * =========================================================================
  */
 /*
- * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -37646,6 +37646,20 @@ extern ULONG eqos_base_addr;
 #define MAC_ISR_LPI_LPOS 5
 #define MAC_ISR_LPI_HPOS 5
 
+#define MAC_L3L4_CTR_DMCHEN0            BIT(28)
+#define MAC_L3L4_CTR_DMCHEN0_SHIFT      28
+#define MAC_L3L4_CTR_DMCHN0             (BIT(24) | BIT(25) | \
+                                        BIT(26) | BIT(27))
+#define MAC_L3L4_CTR_DMCHN0_SHIFT       24
+
+#define MAC_L3L4_CTR_L3HDBM0            (BIT(11) | BIT(12) | \
+                                        BIT(13) | BIT(14) | BIT(15))
+#define MAC_L3L4_CTR_L3HDBM0_SHIFT      11
+
+#define MAC_L3L4_CTR_L3HSBM0            (BIT(6) | BIT(7) | \
+                                        BIT(8) | BIT(9) | BIT(10))
+#define MAC_L3L4_CTR_L3HSBM0_SHIFT      6
+
 #define GET_VALUE(data, lbit, hbit) ((data >> lbit) & (~(~0<<(hbit-lbit+1))))
 
 #define GET_INDEXED_VALUE(data, lbit, hbit, index)\