phy: tegra: pcie: disable SLCG for P2U

Disables SLCG for P2U module for initial bringup

bug 200369845

Change-Id: I53e9488a1c276046770ccb3e0599cae89d02be5d
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1609992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/phy/phy-tegra-p2u.c b/drivers/phy/phy-tegra-p2u.c
index 5a52c255e..0f47622fc 100644
--- a/drivers/phy/phy-tegra-p2u.c
+++ b/drivers/phy/phy-tegra-p2u.c
@@ -23,6 +23,8 @@
 #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN       BIT(1)
 #define P2U_PERIODIC_EQ_CTRL_GEN4       0xc4
 #define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN       BIT(1)
+#define P2U_SLCG                                0xbc
+#define P2U_SLCG_MASTER                 BIT(0)
 
 struct tegra_p2u {
         void __iomem            *base;
@@ -39,6 +41,11 @@ static int tegra_p2u_power_on(struct phy *x)
         u32 val;
         struct tegra_p2u *phy = phy_get_drvdata(x);
 
+        /* Disable SLCG */
+        /* NOTE:- This needs to be removed after initial bringup */
+        val = readl(phy->base + P2U_SLCG);
+        writel(val | P2U_SLCG_MASTER, phy->base + P2U_SLCG);
+
         val = readl(phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);
         val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
         writel(val, phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);