summaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorSumit Gupta <sumitg@nvidia.com>2018-07-09 09:07:00 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-13 20:27:44 -0400
commit8be06c2bf3ca96fb216f064f18da7ac6470633a7 (patch)
treefd259d0006f968f956bc274e317199a63b44d241 /drivers
parent262b58181ec4259f6458ad9ad986c7de962327cb (diff)
platform: tegra: update RAS error codes
Updating ERR<x>CTLR bits and IERR codes to report correct error. RAS/MCA error codes and bits have been changed in recent MTS code due to which error info will not be reported correctly. So, updating related codevalues and bits in RAS driver as per latest sheet from MTS member "New_MCA_20180619_0114.xlsx". Bug 200420692 Change-Id: If5268a8f0b8005cf97b147b154b9249529c108ec Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774516 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/platform/tegra/carmel_ras.c264
1 files changed, 136 insertions, 128 deletions
diff --git a/drivers/platform/tegra/carmel_ras.c b/drivers/platform/tegra/carmel_ras.c
index 628caeb91..f6f8a036e 100644
--- a/drivers/platform/tegra/carmel_ras.c
+++ b/drivers/platform/tegra/carmel_ras.c
@@ -40,25 +40,24 @@ static enum cpuhp_state hp_state;
40 * error_code = value of ARM_ERR_STATUS:IERR[15:8] 40 * error_code = value of ARM_ERR_STATUS:IERR[15:8]
41 */ 41 */
42static struct ras_error ifu_errors[] = { 42static struct ras_error ifu_errors[] = {
43 {.name = "Mitigation Parity Error", .error_code = 0x12}, 43 {.name = "IMQ Data Parity", .error_code = 0x08},
44 {.name = "IMQ Data Parity", .error_code = 0x01}, 44 {.name = "L2 I$ Fetch Uncorrectable", .error_code = 0x07},
45 {.name = "L2 I$ Fetch Uncorrectable", .error_code = 0x02}, 45 {.name = "I$ Tag Parity Snoop", .error_code = 0x06},
46 {.name = "I$ Tag Parity Snoop", .error_code = 0x03}, 46 {.name = "I$ Multi-Hit Snoop", .error_code = 0x05},
47 {.name = "I$ Multi-Hit Snoop", .error_code = 0x04}, 47 {.name = "ITLB Parity", .error_code = 0x04},
48 {.name = "ITLB Parity", .error_code = 0x05}, 48 {.name = "Trace Hash Error", .error_code = 0x03},
49 {.name = "Trace Hash Error", .error_code = 0x06}, 49 {.name = "I$ Data Parity", .error_code = 0x02},
50 {.name = "I$ Data Parity", .error_code = 0x07}, 50 {.name = "I$ Tag Parity", .error_code = 0x01},
51 {.name = "I$ Tag Parity", .error_code = 0x10}, 51 {.name = "I$ Multi-Hit", .error_code = 0x0F},
52 {.name = "I$ Multi-Hit", .error_code = 0x11},
53 {} 52 {}
54}; 53};
55 54
56/* Error Records per CORE - RET JSR errors */ 55/* Error Records per CORE - RET JSR errors */
57static struct ras_error ret_jsr_errors[] = { 56static struct ras_error ret_jsr_errors[] = {
58 {.name = "Garbage Budle", .error_code = 0x19}, 57 {.name = "FRF Parity", .error_code = 0x13},
59 {.name = "FRF Parity", .error_code = 0x1B}, 58 {.name = "IRF Parity", .error_code = 0x12},
60 {.name = "IRF Parity", .error_code = 0x1A}, 59 {.name = "Garbage Bundle", .error_code = 0x11},
61 {.name = "RET Timeout", .error_code = 0x18}, 60 {.name = "Bundle Completion Timeout", .error_code = 0x10},
62 {} 61 {}
63}; 62};
64 63
@@ -73,40 +72,40 @@ static struct ras_error mts_jsr_errors[] = {
73 {} 72 {}
74}; 73};
75 74
76/* Error Records per CORE - LSD_1 errors */ 75/* Error Records per CORE - LSD_1/LSD_STQ errors */
77static struct ras_error lsd_1_errors[] = { 76static struct ras_error lsd_1_errors[] = {
78 {.name = "Core Cache Store Multi-line parity Error", 77 {.name = "Coherent Cache Data Store Multi-Line ECC",
79 .error_code = 0x38}, 78 .error_code = 0x39},
80 {.name = "Core-Cache Store ECC", .error_code = 0x37}, 79 {.name = "Coherent Cache Data Store Uncorrectable ECC",
81 {.name = "Core-Cache Store ECC", .error_code = 0x36}, 80 .error_code = 0x38},
82 {.name = "Core-Cache Load ECC", .error_code = 0x35}, 81 {.name = "Coherent Cache Data Store Correctable ECC",
83 {.name = "Core-Cache Load ECC", .error_code = 0x34}, 82 .error_code = 0x37},
84 {.name = "Mini-Cache Data Load Parity", .error_code = 0x33}, 83 {.name = "Coherent Cache Data Load Uncorrectable ECC",
85 {.name = "Core Cache Multi-Hit", .error_code = 0x32}, 84 .error_code = 0x36},
86 {.name = "Mini-Cache Multi-Hit", .error_code = 0x31}, 85 {.name = "Coherent Cache Data Load Correctable ECC",
87 {.name = "Core-Cache Tag Parity", .error_code = 0x30}, 86 .error_code = 0x35},
87 {.name = "Coherent Cache Multi-Hit", .error_code = 0x33},
88 {.name = "Coherent Cache Tag Store Parity", .error_code = 0x31},
89 {.name = "Coherent Cache Tag Load Parity", .error_code = 0x30},
88 {} 90 {}
89}; 91};
90 92
91/* Error Records per CORE - LSD_2 errors */ 93/* Error Records per CORE - LSD_2/LSD_ECC errors */
92static struct ras_error lsd_2_errors[] = { 94static struct ras_error lsd_2_errors[] = {
93 {.name = "L2 Detected Error on LSD Request", .error_code = 0x49}, 95 {.name = "BTU Copy Mini-Cache PPN Multi-Hit Error", .error_code = 0x49},
94 {.name = "Coherent Cache Uncorrectable ECC", .error_code = 0x48}, 96 {.name = "Coherent Cache Data Uncorrectable ECC", .error_code = 0x47},
95 {.name = "Coherent Cache Correctable ECC", .error_code = 0x47}, 97 {.name = "Coherent Cache Data Correctable ECC", .error_code = 0x46},
96 {.name = "Mini Cache Eviction Parity Error", .error_code = 0x46}, 98 {.name = "Version Cache Byte-Enable Parity", .error_code = 0x45},
97 {.name = "Version Cache Eviction Parity Error", .error_code = 0x45}, 99 {.name = "Version Cache Data Uncorrectable ECC", .error_code = 0x44},
98 {.name = "Version Cache Data ECC Uncorrectable", .error_code = 0x44}, 100 {.name = "Version Cache Data Correctable ECC", .error_code = 0x43},
99 {.name = "Version Cache Data ECC Correctable", .error_code = 0x43}, 101 {.name = "BTU Copy Coherent Cache PPN Parity", .error_code = 0x41},
100 {.name = "BTU Core Cache Multi-Hit", .error_code = 0x42}, 102 {.name = "BTU Copy Coherent Cache VPN Parity", .error_code = 0x40},
101 {.name = "BTU Mini Cache PPN", .error_code = 0x41},
102 {.name = "BTU Core Cache PPN", .error_code = 0x40},
103 {} 103 {}
104}; 104};
105 105
106/* Error Records per CORE - LSD_3 errors */ 106/* Error Records per CORE - LSD_3/LSD_L1HPF errors */
107static struct ras_error lsd_3_errors[] = { 107static struct ras_error lsd_3_errors[] = {
108 {.name = "LSD Latent Fault 3", .error_code = 0x3D}, 108 {.name = "L2 TLB Parity Error", .error_code = 0xE0},
109 {.name = "L2 TLB Parity Error", .error_code = 0x3C},
110 {} 109 {}
111}; 110};
112 111
@@ -114,12 +113,11 @@ static struct ras_error lsd_3_errors[] = {
114static struct error_record core_ers[] = { 113static struct error_record core_ers[] = {
115 {.name = "IFU", .errx = 0, 114 {.name = "IFU", .errx = 0,
116 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 115 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
117 ERR_CTL_IFU_ITLB_SNP_ERR | ERR_CTL_IFU_ICMH_ERR | 116 ERR_CTL_IFU_ICMH_ERR | ERR_CTL_IFU_ICTP_ERR |
118 ERR_CTL_IFU_ICTP_ERR | ERR_CTL_IFU_ICDP_ERR | 117 ERR_CTL_IFU_ICDP_ERR |
119 ERR_CTL_IFU_THERR_ERR | ERR_CTL_IFU_ITLBP_ERR | 118 ERR_CTL_IFU_THERR_ERR | ERR_CTL_IFU_ITLBP_ERR |
120 ERR_CTL_IFU_ICMHSNP_ERR | ERR_CTL_IFU_ICTPSNP_ERR | 119 ERR_CTL_IFU_ICMHSNP_ERR | ERR_CTL_IFU_ICTPSNP_ERR |
121 ERR_CTL_IFU_L2UC_ERR | ERR_CTL_IFU_IMQDP_ERR | 120 ERR_CTL_IFU_L2UC_ERR | ERR_CTL_IFU_IMQDP_ERR,
122 ERR_CTL_IFU_MITGRP_ERR,
123 .errors = ifu_errors}, 121 .errors = ifu_errors},
124 {.name = "RET_JSR", .errx = 1, 122 {.name = "RET_JSR", .errx = 1,
125 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | 123 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE |
@@ -132,25 +130,24 @@ static struct error_record core_ers[] = {
132 ERR_CTL_MTS_JSR_NAFLL_ERR | ERR_CTL_MTS_JSR_CARVE_ERR | 130 ERR_CTL_MTS_JSR_NAFLL_ERR | ERR_CTL_MTS_JSR_CARVE_ERR |
133 ERR_CTL_MTS_JSR_CRAB_ERR | ERR_CTL_MTS_JSR_MMIO_ERR, 131 ERR_CTL_MTS_JSR_CRAB_ERR | ERR_CTL_MTS_JSR_MMIO_ERR,
134 .errors = mts_jsr_errors}, 132 .errors = mts_jsr_errors},
135 {.name = "LSD_1", .errx = 3, 133 {.name = "LSD_STQ", .errx = 3,
136 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 134 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
137 ERR_CTL_LSD1_CCTP_ERR | ERR_CTL_LSD1_MCMH_ERR | 135 ERR_CTL_LSD1_CCTLP_ERR | ERR_CTL_LSD1_CCTSP_ERR |
138 ERR_CTL_LSD1_CCMH_ERR | ERR_CTL_LSD1_MCDLP_ERR | 136 ERR_CTL_LSD1_CCMH_ERR |
139 ERR_CTL_LSD1_CCDLECC_S_ERR | ERR_CTL_LSD1_CCDLECC_D_ERR | 137 ERR_CTL_LSD1_CCDLECC_S_ERR | ERR_CTL_LSD1_CCDLECC_D_ERR |
140 ERR_CTL_LSD1_CCDSECC_S_ERR | ERR_CTL_LSD1_CCDSECC_D_ERR | 138 ERR_CTL_LSD1_CCDSECC_S_ERR | ERR_CTL_LSD1_CCDSECC_D_ERR |
141 ERR_CTL_LSD1_CCDEMLECC_ERR, 139 ERR_CTL_LSD1_CCDEMLECC_ERR,
142 .errors = lsd_1_errors}, 140 .errors = lsd_1_errors},
143 {.name = "LSD_2", .errx = 4, 141 {.name = "LSD_DCC", .errx = 4,
144 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 142 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
145 ERR_CTL_LSD2_BTCCVPP_ERR | ERR_CTL_LSD2_BTCCPPP_ERR | 143 ERR_CTL_LSD2_BTCCVPP_ERR | ERR_CTL_LSD2_BTCCPPP_ERR |
146 ERR_CTL_LSD2_BTCCMH_ERR | ERR_CTL_LSD2_VRCDECC_S_ERR | 144 ERR_CTL_LSD2_VRCDECC_S_ERR | ERR_CTL_LSD2_VRCDECC_D_ERR |
147 ERR_CTL_LSD2_VRCDECC_D_ERR | ERR_CTL_LSD2_VRCDP_ERR | 145 ERR_CTL_LSD2_BTMCMH_ERR | ERR_CTL_LSD2_VRCBP_ERR |
148 ERR_CTL_LSD2_MCDEP_ERR | ERR_CTL_LSD2_CCDEECC_S_ERR | 146 ERR_CTL_LSD2_CCDEECC_S_ERR | ERR_CTL_LSD2_CCDEECC_D_ERR,
149 ERR_CTL_LSD2_CCDEECC_D_ERR | ERR_CTL_LSD2_L2REQ_UNCORR_ERR,
150 .errors = lsd_2_errors}, 147 .errors = lsd_2_errors},
151 {.name = "LSD_3", .errx = 5, 148 {.name = "LSD_L1HPF", .errx = 5,
152 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 149 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
153 ERR_CTL_LSD3_L2TLBP_ERR | ERR_CTL_LSD3_LATENT_ERR, 150 ERR_CTL_LSD3_L2TLBP_ERR,
154 .errors = lsd_3_errors}, 151 .errors = lsd_3_errors},
155 {} 152 {}
156}; 153};
@@ -166,14 +163,14 @@ static struct ras_error l2_errors[] = {
166 {.name = "SCF to L2 Decode Error Read", .error_code = 0x64}, 163 {.name = "SCF to L2 Decode Error Read", .error_code = 0x64},
167 {.name = "SCF to L2 Decode Error Write", .error_code = 0x63}, 164 {.name = "SCF to L2 Decode Error Write", .error_code = 0x63},
168 {.name = "SCF to L2 Request Response Interface Parity Errors", 165 {.name = "SCF to L2 Request Response Interface Parity Errors",
169 .error_code = 0x62}, 166 .error_code = 0x62},
170 {.name = "SCF to L2 Advance notice interface parity errors", 167 {.name = "SCF to L2 Advance notice interface parity errors",
171 .error_code = 0x61}, 168 .error_code = 0x61},
172 {.name = "SCF to L2 Filldata Parity Errors", .error_code = 0x60}, 169 {.name = "SCF to L2 Filldata Parity Errors", .error_code = 0x60},
173 {.name = "SCF to L2 UnCorrectable ECC Data Error on interface", 170 {.name = "SCF to L2 UnCorrectable ECC Data Error on interface",
174 .error_code = 0x5F}, 171 .error_code = 0x5F},
175 {.name = "SCF to L2 Correctable ECC Data Error on interface", 172 {.name = "SCF to L2 Correctable ECC Data Error on interface",
176 .error_code = 0x5E}, 173 .error_code = 0x5E},
177 {.name = "Core 1 to L2 Parity Error", .error_code = 0x5D}, 174 {.name = "Core 1 to L2 Parity Error", .error_code = 0x5D},
178 {.name = "Core 0 to L2 Parity Error", .error_code = 0x5C}, 175 {.name = "Core 0 to L2 Parity Error", .error_code = 0x5C},
179 {.name = "L2 Multi-Hit", .error_code = 0x5B}, 176 {.name = "L2 Multi-Hit", .error_code = 0x5B},
@@ -192,15 +189,14 @@ static struct ras_error l2_errors[] = {
192 189
193/* Error Records per CORE CLUSTER - MMU errors */ 190/* Error Records per CORE CLUSTER - MMU errors */
194static struct ras_error mmu_errors[] = { 191static struct ras_error mmu_errors[] = {
195 {.name = "Walker Cache Parity Error", .error_code = 0x2D}, 192 {.name = "Walker Cache Parity Error", .error_code = 0xE9},
196 {.name = "A$ Parity Error", .error_code = 0x2C}, 193 {.name = "A$ Parity Error", .error_code = 0xE8},
197 {} 194 {}
198}; 195};
199 196
200/* Error Records per CORE CLUSTER - Cluster Clocks errors */ 197/* Error Records per CORE CLUSTER - Cluster Clocks errors */
201static struct ras_error cluster_clocks_errors[] = { 198static struct ras_error cluster_clocks_errors[] = {
202 {.name = "Walker Cache Parity Error", .error_code = 0x2D}, 199 {.name = "Frequency Monitor Error", .error_code = 0xE4},
203 {.name = "A$ Parity Error", .error_code = 0x2C},
204 {} 200 {}
205}; 201};
206 202
@@ -224,13 +220,13 @@ static struct error_record corecluster_ers[] = {
224 ERR_CTL_L2_SCF2L2C_SLVRDERR_ERR | ERR_CTL_L2_L2PCL_ERR | 220 ERR_CTL_L2_SCF2L2C_SLVRDERR_ERR | ERR_CTL_L2_L2PCL_ERR |
225 ERR_CTL_L2_URTTO_ERR, 221 ERR_CTL_L2_URTTO_ERR,
226 .errors = l2_errors}, 222 .errors = l2_errors},
223 {.name = "CLUSTER_CLOCKS", .errx = 1,
224 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | ERR_CTL_CC_FREQ_MON_ERR,
225 .errors = cluster_clocks_errors},
227 {.name = "MMU", .errx = 2, 226 {.name = "MMU", .errx = 2,
228 .err_ctrl = RAS_CTL_ED | RAS_CTL_CFI | 227 .err_ctrl = RAS_CTL_ED | RAS_CTL_CFI |
229 ERR_CTL_MMU_ACPERR_ERR | ERR_CTL_MMU_WCPERR_ERR, 228 ERR_CTL_MMU_ACPERR_ERR | ERR_CTL_MMU_WCPERR_ERR,
230 .errors = mmu_errors}, 229 .errors = mmu_errors},
231 {.name = "CLUSTER_CLOCKS", .errx = 1,
232 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | ERR_CTL_CC_FREQ_MON_ERR,
233 .errors = cluster_clocks_errors},
234 {} 230 {}
235}; 231};
236 232
@@ -238,76 +234,84 @@ static struct error_record corecluster_ers[] = {
238 * error_code = value of ARM_ERR_STATUS:IERR[15:8] 234 * error_code = value of ARM_ERR_STATUS:IERR[15:8]
239 */ 235 */
240static struct ras_error cmu_ccpmu_errors[] = { 236static struct ras_error cmu_ccpmu_errors[] = {
241 {.name = "DMCE Ucode Error", .error_code = 0x2A}, 237 {.name = "MCE Ucode Error", .error_code = 0x84},
242 {.name = "Crab Access Error", .error_code = 0x29}, 238 {.name = "MCE IL1 Parity Error", .error_code = 0x83},
243 {.name = "DMCE Crab Access Error", .error_code = 0x28}, 239 {.name = "MCE Timeout Error", .error_code = 0x82},
240 {.name = "CRAB Access Error", .error_code = 0x81},
241 {.name = "MCE Memory Access Error", .error_code = 0x80},
244 {} 242 {}
245}; 243};
246 244
247/* Error Records per CCPLEX - SCF:IOB errors */ 245/* Error Records per CCPLEX - SCF:IOB errors */
248static struct ras_error scf_iob_errors[] = { 246static struct ras_error scf_iob_errors[] = {
249 {.name = "CBB Interface Error", .error_code = 0x76}, 247 {.name = "Request parity error", .error_code = 0x99},
250 {.name = "IHI Interface Error", .error_code = 0x74}, 248 {.name = "Putdata parity error", .error_code = 0x98},
251 {.name = "MMCRAB Error", .error_code = 0x75}, 249 {.name = "Uncorrectable ECC on Putdata", .error_code = 0x97},
252 {.name = "CRI Error", .error_code = 0x73}, 250 {.name = "CBB Interface Error", .error_code = 0x96},
253 {.name = "TBX Interface Error", .error_code = 0x72}, 251 {.name = "MMCRAB Error", .error_code = 0x95},
254 {.name = "EVP Interface Error", .error_code = 0x71}, 252 {.name = "IHI Interface Error", .error_code = 0x94},
255 {.name = "Uncorrectable ECC on Putdata", .error_code = 0x77}, 253 {.name = "CRI Error", .error_code = 0x93},
256 {.name = "Correctable ECC on Putdata", .error_code = 0x70}, 254 {.name = "TBX Interface Error", .error_code = 0x92},
257 {.name = "Putdata parity Error", .error_code = 0x78}, 255 {.name = "EVP Interface Error", .error_code = 0x91},
258 {.name = "Request Parity Error", .error_code = 0x79}, 256 {.name = "Correctable ECC on Putdata", .error_code = 0x90},
259 {} 257 {}
260}; 258};
261 259
262/* Error Records per CCPLEX - SCF:SNOC errors */ 260/* Error Records per CCPLEX - SCF:SNOC errors */
263static struct ras_error scf_snoc_errors[] = { 261static struct ras_error scf_snoc_errors[] = {
264 {.name = "Carveout Error", .error_code = 0x81}, 262 {.name = "Misc Client Parity Error", .error_code = 0xAA},
265 {.name = "Misc Client Parity Error", .error_code = 0x89}, 263 {.name = "Misc Filldata Parity Error", .error_code = 0xA9},
266 {.name = "Misc Filldata Parity Error", .error_code = 0x88}, 264 {.name = "Uncorrectable ECC Misc Client", .error_code = 0xA8},
267 {.name = "Uncorrectable ECC Misc Client", .error_code = 0x87}, 265 {.name = "DVMU Interface Parity Error", .error_code = 0xA7},
268 {.name = "Correctable ECC Misc Client", .error_code = 0x80}, 266 {.name = "DVMU Interface Timeout Error", .error_code = 0xA6},
269 {.name = "DVMU Interface Parity Error", .error_code = 0x86}, 267 {.name = "CPE Request Error", .error_code = 0xA5},
270 {.name = "DVMU Interface Timeout Error", .error_code = 0x85}, 268 {.name = "CPE Response Error", .error_code = 0xA4},
271 {.name = "CPE Request Error", .error_code = 0x84}, 269 {.name = "CPE Timeout Error", .error_code = 0xA3},
272 {.name = "CPE Response Error", .error_code = 0x83}, 270 {.name = "Uncorrectable Carveout Error", .error_code = 0xA2},
273 {.name = "CPE Timeout Error", .error_code = 0x82}, 271 {.name = "Correctable ECC Misc Client", .error_code = 0xA1},
272 {.name = "Correctable Carveout Error", .error_code = 0xA0},
274 {} 273 {}
275}; 274};
276 275
277/* Error Records per CCPLEX - CMU:CTU errors */ 276/* Error Records per CCPLEX - SCF:CTU errors */
278static struct ras_error cmu_ctu_errors[] = { 277static struct ras_error cmu_ctu_errors[] = {
279 {.name = "Timeout Error for TRC_DMA request timeout", 278 {.name = "Timeout error for TRC_DMA request", .error_code = 0xB7},
280 .error_code = 0xB6}, 279 {.name = "Timeout error for CTU Snp", .error_code = 0xB6},
281 {.name = "Timeout Error for CTU Snp", .error_code = 0xB5}, 280 {.name = "Parity error in CTU TAG RAM", .error_code = 0xB5},
282 {.name = "Parity Error in CTU TAG RAM", .error_code = 0xB4}, 281 {.name = "Parity error in CTU DATA RAM", .error_code = 0xB3},
283 {.name = "Parity Error in CTU DATA RAM", .error_code = 0xB3}, 282 {.name = "Parity error for Cluster Rsp", .error_code = 0xB4},
284 {.name = "Parity error for TRL requests from 9 agents", 283 {.name = "Parity error for TRL requests from 9 agents",
285 .error_code = 0xB2}, 284 .error_code = 0xB2},
286 {.name = "Parity error for MCF request", .error_code = 0xB1}, 285 {.name = "Parity error for MCF request", .error_code = 0xB1},
287 {.name = "TRC DMA fillsnoop parity error", .error_code = 0xB0}, 286 {.name = "TRC DMA fillsnoop parity error", .error_code = 0xB0},
288 {} 287 {}
289}; 288};
290 289
291/* Error Records per CCPLEX - SCF:L3_* errors */ 290/* Error Records per CCPLEX - SCF:L3_* errors */
292static struct ras_error scf_l3_errors[] = { 291static struct ras_error scf_l3_errors[] = {
293 {.name = "L3 Timeout Error", .error_code = 0x91}, 292 {.name = "L3 Correctable ECC Error", .error_code = 0x7C},
294 {.name = "L3 Protocol Error", .error_code = 0x92}, 293 {.name = "SNOC Interface Parity Error", .error_code = 0x7B},
295 {.name = "Destination Error", .error_code = 0x90}, 294 {.name = "MCF Interface Parity Error", .error_code = 0x7A},
296 {.name = "Unrecognised Command Error", .error_code = 0x93}, 295 {.name = "L3 Tag Parity Error", .error_code = 0x79},
297 {.name = "Multi-Hit Tage Error", .error_code = 0x94}, 296 {.name = "L3 Dir Parity Error", .error_code = 0x78},
298 {.name = "Multi-Hit CAM Error", .error_code = 0x95}, 297 {.name = "L3 Uncorrectable ECC Error", .error_code = 0x77},
299 {.name = "L3 Correctable ECC error", .error_code = 0x99}, 298 {.name = "Multi-Hit CAM Error", .error_code = 0x75},
300 {.name = "L3 Tag Parity Error", .error_code = 0x98}, 299 {.name = "Multi-Hit Tag Error", .error_code = 0x74},
301 {.name = "L3 Address Error", .error_code = 0x96}, 300 {.name = "Unrecognized Command Error", .error_code = 0x73},
301 {.name = "L3 Protocol Error", .error_code = 0x72},
302 {} 302 {}
303}; 303};
304 304
305/* Error Records per CCPLEX - SCFCMU_Clocks errors */ 305/* Error Records per CCPLEX - CMU_Clocks errors */
306static struct ras_error scfcmu_clocks_errors[] = { 306static struct ras_error scfcmu_clocks_errors[] = {
307 {.name = "Voltage Error on ADC1 Monitored Logic", .error_code = 0xA3}, 307 {.name = "Cluster 3 frequency monitor error", .error_code = 0xC7},
308 {.name = "Voltage Error on ADC0 Monitored Logic", .error_code = 0xA2}, 308 {.name = "Cluster 2 frequency monitor error", .error_code = 0xC6},
309 {.name = "Lookup Table 1 Parity Error", .error_code = 0xA1}, 309 {.name = "Cluster 1 frequency monitor error", .error_code = 0xC5},
310 {.name = "Lookup Table 0 Parity Error", .error_code = 0xA0}, 310 {.name = "Cluster 0 frequency monitor error", .error_code = 0xC3},
311 {.name = "Voltage error on ADC1 Monitored Logic", .error_code = 0xC4},
312 {.name = "Voltage error on ADC0 Monitored Logic", .error_code = 0xC2},
313 {.name = "Lookup Table 1 Parity Error", .error_code = 0xC1},
314 {.name = "Lookup Table 0 Parity Error", .error_code = 0xC0},
311 {} 315 {}
312}; 316};
313 317
@@ -316,6 +320,7 @@ static struct error_record ccplex_ers[] = {
316 {.name = "CMU:CCPMU", .errx = 1024, 320 {.name = "CMU:CCPMU", .errx = 1024,
317 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | 321 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE |
318 ERR_CTL_DPMU_DMCE_CRAB_ACC_ERR | ERR_CTL_DPMU_CRAB_ACC_ERR | 322 ERR_CTL_DPMU_DMCE_CRAB_ACC_ERR | ERR_CTL_DPMU_CRAB_ACC_ERR |
323 ERR_CTL_DPMU_DMCE_IL1_PAR_ERR | ERR_CTL_DPMU_DMCE_TIMEOUT_ERR |
319 ERR_CTL_DPMU_DMCE_UCODE_ERR, 324 ERR_CTL_DPMU_DMCE_UCODE_ERR,
320 .errors = cmu_ccpmu_errors}, 325 .errors = cmu_ccpmu_errors},
321 {.name = "SCF:IOB", .errx = 1025, 326 {.name = "SCF:IOB", .errx = 1025,
@@ -332,51 +337,54 @@ static struct error_record ccplex_ers[] = {
332 ERR_CTL_SCFSNOC_CPE_REQ_ERR | ERR_CTL_SCFSNOC_DVMU_TO_ERR | 337 ERR_CTL_SCFSNOC_CPE_REQ_ERR | ERR_CTL_SCFSNOC_DVMU_TO_ERR |
333 ERR_CTL_SCFSNOC_DVMU_PAR_ERR | ERR_CTL_SCFSNOC_MISC_CECC_ERR | 338 ERR_CTL_SCFSNOC_DVMU_PAR_ERR | ERR_CTL_SCFSNOC_MISC_CECC_ERR |
334 ERR_CTL_SCFSNOC_MISC_UECC_ERR | ERR_CTL_SCFSNOC_MISC_PAR_ERR | 339 ERR_CTL_SCFSNOC_MISC_UECC_ERR | ERR_CTL_SCFSNOC_MISC_PAR_ERR |
335 ERR_CTL_SCFSNOC_MISC_RSP_ERR | ERR_CTL_SCFSNOC_CARVEOUT_ERR, 340 ERR_CTL_SCFSNOC_MISC_RSP_ERR | ERR_CTL_SCFSNOC_CARVEOUT_ERR |
341 ERR_CTL_SCFSNOC_CARVEOUT_CECC_ERR,
336 .errors = scf_snoc_errors}, 342 .errors = scf_snoc_errors},
337 {.name = "CMU:CTU", .errx = 1027, 343 {.name = "CMU:CTU", .errx = 1027,
338 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | 344 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE |
339 ERR_CTL_CMUCTU_TRCDMA_PAR_ERR | ERR_CTL_CMUCTU_MCF_PAR_ERR | 345 ERR_CTL_CMUCTU_TRCDMA_PAR_ERR | ERR_CTL_CMUCTU_MCF_PAR_ERR |
340 ERR_CTL_CMUCTU_TRL_PAR_ERR | ERR_CTL_CMUCTU_CTU_DATA_PAR_ERR | 346 ERR_CTL_CMUCTU_TRL_PAR_ERR | ERR_CTL_CMUCTU_CTU_DATA_PAR_ERR |
341 ERR_CTL_CMUCTU_TAG_PAR_ERR | ERR_CTL_CMUCTU_CTU_SNP_ERR | 347 ERR_CTL_CMUCTU_TAG_PAR_ERR | ERR_CTL_CMUCTU_CTU_SNP_ERR |
342 ERR_CTL_CMUCTU_TRCDMA_REQ_ERR, 348 ERR_CTL_CMUCTU_TRCDMA_REQ_ERR | ERR_CTL_CMUCTU_RSP_PAR_ERR,
343 .errors = cmu_ctu_errors}, 349 .errors = cmu_ctu_errors},
344 {.name = "SCF:L3_0", .errx = 768, 350 {.name = "SCF:L3_0", .errx = 768,
345 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 351 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
346 ERR_CTL_SCFL3_ADR_ERR | ERR_CTL_SCFL3_PERR_ERR | 352 ERR_CTL_SCFL3_CECC_ERR | ERR_CTL_SCFL3_SNOC_INTFC_ERR |
347 ERR_CTL_SCFL3_UECC_ERR | ERR_CTL_SCFL3_CECC_ERR | 353 ERR_CTL_SCFL3_MCF_INTFC_ERR | ERR_CTL_SCFL3_TAG_ERR |
354 ERR_CTL_SCFL3_L2DIR_ERR | ERR_CTL_SCFL3_UECC_ERR |
348 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR | 355 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR |
349 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR | 356 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR,
350 ERR_CTL_SCFL3_TO_ERR,
351 .errors = scf_l3_errors}, 357 .errors = scf_l3_errors},
352 {.name = "SCF:L3_1", .errx = 769, 358 {.name = "SCF:L3_1", .errx = 769,
353 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 359 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
354 ERR_CTL_SCFL3_ADR_ERR | ERR_CTL_SCFL3_PERR_ERR | 360 ERR_CTL_SCFL3_CECC_ERR | ERR_CTL_SCFL3_SNOC_INTFC_ERR |
355 ERR_CTL_SCFL3_UECC_ERR | ERR_CTL_SCFL3_CECC_ERR | 361 ERR_CTL_SCFL3_MCF_INTFC_ERR | ERR_CTL_SCFL3_TAG_ERR |
362 ERR_CTL_SCFL3_L2DIR_ERR | ERR_CTL_SCFL3_UECC_ERR |
356 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR | 363 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR |
357 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR | 364 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR,
358 ERR_CTL_SCFL3_TO_ERR,
359 .errors = scf_l3_errors}, 365 .errors = scf_l3_errors},
360 {.name = "SCF:L3_2", .errx = 770, 366 {.name = "SCF:L3_2", .errx = 770,
361 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 367 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
362 ERR_CTL_SCFL3_ADR_ERR | ERR_CTL_SCFL3_PERR_ERR | 368 ERR_CTL_SCFL3_CECC_ERR | ERR_CTL_SCFL3_SNOC_INTFC_ERR |
363 ERR_CTL_SCFL3_UECC_ERR | ERR_CTL_SCFL3_CECC_ERR | 369 ERR_CTL_SCFL3_MCF_INTFC_ERR | ERR_CTL_SCFL3_TAG_ERR |
370 ERR_CTL_SCFL3_L2DIR_ERR | ERR_CTL_SCFL3_UECC_ERR |
364 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR | 371 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR |
365 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR | 372 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR,
366 ERR_CTL_SCFL3_TO_ERR,
367 .errors = scf_l3_errors}, 373 .errors = scf_l3_errors},
368 {.name = "SCF:L3_3", .errx = 771, 374 {.name = "SCF:L3_3", .errx = 771,
369 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI | 375 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | RAS_CTL_CFI |
370 ERR_CTL_SCFL3_ADR_ERR | ERR_CTL_SCFL3_PERR_ERR | 376 ERR_CTL_SCFL3_CECC_ERR | ERR_CTL_SCFL3_SNOC_INTFC_ERR |
371 ERR_CTL_SCFL3_UECC_ERR | ERR_CTL_SCFL3_CECC_ERR | 377 ERR_CTL_SCFL3_MCF_INTFC_ERR | ERR_CTL_SCFL3_TAG_ERR |
378 ERR_CTL_SCFL3_L2DIR_ERR | ERR_CTL_SCFL3_UECC_ERR |
372 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR | 379 ERR_CTL_SCFL3_MH_CAM_ERR | ERR_CTL_SCFL3_MH_TAG_ERR |
373 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR | 380 ERR_CTL_SCFL3_UNSUPP_REQ_ERR | ERR_CTL_SCFL3_PROT_ERR,
374 ERR_CTL_SCFL3_TO_ERR,
375 .errors = scf_l3_errors}, 381 .errors = scf_l3_errors},
376 {.name = "SCFCMU_CLOCKS", .errx = 1028, 382 {.name = "SCFCMU_CLOCKS", .errx = 1028,
377 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE | 383 .err_ctrl = RAS_CTL_ED | RAS_CTL_UE |
378 ERR_CTL_SCFCMU_LUT0_PAR_ERR | ERR_CTL_SCFCMU_LUT1_PAR_ERR | 384 ERR_CTL_SCFCMU_LUT0_PAR_ERR | ERR_CTL_SCFCMU_LUT1_PAR_ERR |
379 ERR_CTL_SCFCMU_ADC0_MON_ERR | ERR_CTL_SCFCMU_ADC1_MON_ERR, 385 ERR_CTL_SCFCMU_ADC0_MON_ERR | ERR_CTL_SCFCMU_ADC1_MON_ERR |
386 ERR_CTL_SCFCMU_FREQ0_MON_ERR | ERR_CTL_SCFCMU_FREQ1_MON_ERR |
387 ERR_CTL_SCFCMU_FREQ2_MON_ERR | ERR_CTL_SCFCMU_FREQ3_MON_ERR,
380 .errors = scfcmu_clocks_errors}, 388 .errors = scfcmu_clocks_errors},
381 {} 389 {}
382}; 390};