platform: tegra: mc: add option to disable L3 alloc hint from mss nvlink

Accessing memory beyond 64GB boundary from GPU on Xavier needs L3 cache
alloc hint disabled at mss nvlink.

Bug 3486025

Change-Id: Iac3a8932a6877b371df15d3e0d8dc9ebe1e48bdd
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2662169
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 6 insertions, 2 deletions

diff --git a/drivers/platform/tegra/mc/mc.c b/drivers/platform/tegra/mc/mc.c
index 38011ecc4..164ca1e74 100644
--- a/drivers/platform/tegra/mc/mc.c
+++ b/drivers/platform/tegra/mc/mc.c
@@ -2,7 +2,7 @@
  * arch/arm/mach-tegra/mc.c
  *
  * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011-2021, NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2011-2022, NVIDIA Corporation.  All rights reserved.
  *
  * Author:
  *      Erik Gilling <konkers@google.com>
@@ -320,6 +320,7 @@ static void enable_mssnvlinks(struct platform_device *pdev)
         void __iomem *regs;
         int ret = 0, i;
         u32 reg_val;
+        bool disable_l3_alloc_hint = false;
 
         /* MSSNVLINK support is available in silicon or fpga only */
         if (!tegra_platform_is_silicon())
@@ -346,6 +347,8 @@ static void enable_mssnvlinks(struct platform_device *pdev)
                 goto err_out;
         }
 
+        disable_l3_alloc_hint = of_property_read_bool(dn, "disable-nvlink-l3-alloc-hint");
+
         for (i = 0; i < mssnvlink_hubs; i++) {
                 regs = of_iomap(dn, i);
                 if (!regs) {
@@ -355,7 +358,8 @@ static void enable_mssnvlinks(struct platform_device *pdev)
                 }
                 mssnvlink_regs[i] = regs;
                 reg_val = __raw_readl(regs + MSSNVLINK_CYA_DESIGN_MODES);
-                reg_val |=  MSS_NVLINK_L3_ALLOC_HINT;
+                if (!disable_l3_alloc_hint)
+                        reg_val |=  MSS_NVLINK_L3_ALLOC_HINT;
                 __raw_writel(reg_val, regs + MSSNVLINK_CYA_DESIGN_MODES);
                 nvlink_reg_val[i] = reg_val;
         }