diff options
author | Ishwarya Balaji Gururajan <igururajan@nvidia.com> | 2017-10-03 13:19:27 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-24 20:02:34 -0400 |
commit | 578e9dcc3f0d0e87994708490002b43bc14574ab (patch) | |
tree | c08fa2d4617948aab7a086d1b06688bf85045a19 /drivers | |
parent | 7bd013d4c0ebdafbdb300d562f24737e0d3e583c (diff) |
tegra: dc: remove NVDISPLAY ifdefs on hdmihdcp.c
remove NVDISPLAY ifdefs on hdmihdcp.c. Use runtime APIs instead
to differentiate between chips.
Jira TDS-2766
Change-Id: Ic2218975ad5a540946065900d6f523813e124f92
Signed-off-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1572591
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Pranami Bhattacharya <pranamib@nvidia.com>
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/video/tegra/dc/hdmihdcp.c | 360 |
1 files changed, 184 insertions, 176 deletions
diff --git a/drivers/video/tegra/dc/hdmihdcp.c b/drivers/video/tegra/dc/hdmihdcp.c index 83dfad07e..b67a137ca 100644 --- a/drivers/video/tegra/dc/hdmihdcp.c +++ b/drivers/video/tegra/dc/hdmihdcp.c | |||
@@ -450,7 +450,6 @@ static int get_vprime(struct tegra_nvhdcp *nvhdcp, u8 *v_prime) | |||
450 | return 0; | 450 | return 0; |
451 | } | 451 | } |
452 | 452 | ||
453 | #if (!defined(CONFIG_TEGRA_NVDISPLAY)) | ||
454 | /* set or clear RUN_YES */ | 453 | /* set or clear RUN_YES */ |
455 | static void hdcp_ctrl_run(struct tegra_hdmi *hdmi, bool v) | 454 | static void hdcp_ctrl_run(struct tegra_hdmi *hdmi, bool v) |
456 | { | 455 | { |
@@ -465,7 +464,6 @@ static void hdcp_ctrl_run(struct tegra_hdmi *hdmi, bool v) | |||
465 | 464 | ||
466 | tegra_sor_writel_ext(hdmi->sor, NV_SOR_TMDS_HDCP_CTRL, ctrl); | 465 | tegra_sor_writel_ext(hdmi->sor, NV_SOR_TMDS_HDCP_CTRL, ctrl); |
467 | } | 466 | } |
468 | #endif | ||
469 | 467 | ||
470 | /* wait for any bits in mask to be set in NV_SOR_TMDS_HDCP_CTRL | 468 | /* wait for any bits in mask to be set in NV_SOR_TMDS_HDCP_CTRL |
471 | * sleeps up to 120mS */ | 469 | * sleeps up to 120mS */ |
@@ -1359,22 +1357,22 @@ static void nvhdcp_downstream_worker(struct work_struct *work) | |||
1359 | int e; | 1357 | int e; |
1360 | int alloc_err = 0; | 1358 | int alloc_err = 0; |
1361 | u8 b_caps; | 1359 | u8 b_caps; |
1362 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | ||
1363 | int hdcp_ta_ret; /* track returns from TA */ | 1360 | int hdcp_ta_ret; /* track returns from TA */ |
1364 | uint32_t ta_cmd = HDCP_AUTH_CMD; | 1361 | uint32_t ta_cmd = HDCP_AUTH_CMD; |
1365 | bool enc = false; | 1362 | bool enc = false; |
1363 | u32 tmp; | ||
1364 | u32 res; | ||
1365 | uint64_t *pkt = NULL; | ||
1366 | 1366 | ||
1367 | uint64_t *pkt = kzalloc(PKT_SIZE, GFP_KERNEL); | 1367 | if (tegra_dc_is_nvdisplay()) { |
1368 | pkt = kzalloc(PKT_SIZE, GFP_KERNEL); | ||
1368 | 1369 | ||
1369 | if (!pkt) { | 1370 | if (!pkt) { |
1370 | nvhdcp_err("Memory allocation failed\n"); | 1371 | nvhdcp_err("Memory allocation failed\n"); |
1371 | alloc_err = -ENOMEM; | 1372 | alloc_err = -ENOMEM; |
1372 | goto failure; | 1373 | goto failure; |
1374 | } | ||
1373 | } | 1375 | } |
1374 | #else | ||
1375 | u32 tmp; | ||
1376 | u32 res; | ||
1377 | #endif | ||
1378 | 1376 | ||
1379 | g_fallback = 0; | 1377 | g_fallback = 0; |
1380 | 1378 | ||
@@ -1409,116 +1407,120 @@ static void nvhdcp_downstream_worker(struct work_struct *work) | |||
1409 | 1407 | ||
1410 | nvhdcp_vdbg("read Bcaps = 0x%02x\n", b_caps); | 1408 | nvhdcp_vdbg("read Bcaps = 0x%02x\n", b_caps); |
1411 | 1409 | ||
1412 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | 1410 | if (tegra_dc_is_nvdisplay()) { |
1413 | ta_ctx = NULL; | 1411 | ta_ctx = NULL; |
1414 | e = te_open_trusted_session(HDCP_PORT_NAME, &ta_ctx); | 1412 | e = te_open_trusted_session(HDCP_PORT_NAME, &ta_ctx); |
1415 | if (e) { | 1413 | if (e) { |
1416 | nvhdcp_err("Error opening trusted session\n"); | 1414 | nvhdcp_err("Error opening trusted session\n"); |
1417 | goto failure; | 1415 | goto failure; |
1418 | } | 1416 | } |
1419 | 1417 | ||
1420 | /* if session successfully opened, launch operations */ | 1418 | /* if session successfully opened, launch operations |
1421 | /* repeater flag in Bskv must be configured before loading fuses */ | 1419 | * repeater flag in Bskv must be configured before loading fuses |
1422 | *pkt = HDCP_TA_CMD_REP; | 1420 | */ |
1423 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; | 1421 | *pkt = HDCP_TA_CMD_REP; |
1424 | *(pkt + 2*HDCP_CMD_OFFSET) = 0; | 1422 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; |
1425 | *(pkt + 3*HDCP_CMD_OFFSET) = b_caps & BCAPS_REPEATER; | 1423 | *(pkt + 2*HDCP_CMD_OFFSET) = 0; |
1426 | *(pkt + 4*HDCP_CMD_OFFSET) = false; | 1424 | *(pkt + 3*HDCP_CMD_OFFSET) = b_caps & BCAPS_REPEATER; |
1427 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | 1425 | *(pkt + 4*HDCP_CMD_OFFSET) = false; |
1428 | if (e) { | 1426 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); |
1429 | nvhdcp_err("te launch operation failed with error %d\n", e); | 1427 | if (e) { |
1430 | goto failure; | 1428 | nvhdcp_err("te launch operation failed with error %d\n", |
1429 | e); | ||
1430 | goto failure; | ||
1431 | } else { | ||
1432 | nvhdcp_vdbg("Loading kfuse\n"); | ||
1433 | e = load_kfuse(hdmi); | ||
1434 | if (e) { | ||
1435 | nvhdcp_err("kfuse could not be loaded\n"); | ||
1436 | goto failure; | ||
1437 | } | ||
1438 | } | ||
1439 | usleep_range(20000, 25000); | ||
1440 | *pkt = HDCP_TA_CMD_CTRL; | ||
1441 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; | ||
1442 | *(pkt + 2*HDCP_CMD_OFFSET) = HDCP_TA_CTRL_ENABLE; | ||
1443 | *(pkt + 3*HDCP_CMD_OFFSET) = false; | ||
1444 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | ||
1445 | if (e) { | ||
1446 | nvhdcp_err("te launch operation failed with error %d\n", | ||
1447 | e); | ||
1448 | goto failure; | ||
1449 | } else { | ||
1450 | nvhdcp_vdbg("wait AN_VALID ...\n"); | ||
1451 | |||
1452 | hdcp_ta_ret = *pkt; | ||
1453 | nvhdcp_vdbg("An returned %x\n", e); | ||
1454 | if (hdcp_ta_ret) { | ||
1455 | nvhdcp_err("An key generation timeout\n"); | ||
1456 | goto failure; | ||
1457 | } | ||
1458 | |||
1459 | /* check SROM return */ | ||
1460 | hdcp_ta_ret = *(pkt + HDCP_CMD_BYTE_OFFSET); | ||
1461 | if (hdcp_ta_ret) { | ||
1462 | nvhdcp_err("SROM error\n"); | ||
1463 | goto failure; | ||
1464 | } | ||
1465 | } | ||
1466 | |||
1467 | msleep(25); | ||
1468 | *pkt = HDCP_TA_CMD_AKSV; | ||
1469 | *(pkt + 1) = TEGRA_NVHDCP_PORT_HDMI; | ||
1470 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | ||
1471 | if (e) { | ||
1472 | nvhdcp_err("te launch operation failed with error %d\n", | ||
1473 | e); | ||
1474 | goto failure; | ||
1475 | } else { | ||
1476 | hdcp_ta_ret = (u64)*pkt; | ||
1477 | nvhdcp->a_ksv = (u64)*(pkt + 1*HDCP_CMD_BYTE_OFFSET); | ||
1478 | nvhdcp->a_n = (u64)*(pkt + 2*HDCP_CMD_BYTE_OFFSET); | ||
1479 | nvhdcp_vdbg("Aksv is 0x%016llx\n", nvhdcp->a_ksv); | ||
1480 | nvhdcp_vdbg("An is 0x%016llx\n", nvhdcp->a_n); | ||
1481 | /* check if verification of Aksv failed */ | ||
1482 | if (hdcp_ta_ret) { | ||
1483 | nvhdcp_err("Aksv verify failure\n"); | ||
1484 | goto disable; | ||
1485 | } | ||
1486 | } | ||
1431 | } else { | 1487 | } else { |
1432 | nvhdcp_vdbg("Loading kfuse\n"); | 1488 | set_bksv(hdmi, 0, (b_caps & BCAPS_REPEATER)); |
1433 | e = load_kfuse(hdmi); | 1489 | e = load_kfuse(hdmi); |
1434 | if (e) { | 1490 | if (e) { |
1435 | nvhdcp_err("kfuse could not be loaded\n"); | 1491 | nvhdcp_err("kfuse could not be loaded\n"); |
1436 | goto failure; | 1492 | goto failure; |
1437 | } | 1493 | } |
1438 | } | 1494 | |
1439 | usleep_range(20000, 25000); | 1495 | usleep_range(20000, 25000); |
1440 | *pkt = HDCP_TA_CMD_CTRL; | 1496 | hdcp_ctrl_run(hdmi, 1); |
1441 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; | 1497 | |
1442 | *(pkt + 2*HDCP_CMD_OFFSET) = HDCP_TA_CTRL_ENABLE; | ||
1443 | *(pkt + 3*HDCP_CMD_OFFSET) = false; | ||
1444 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | ||
1445 | if (e) { | ||
1446 | nvhdcp_err("te launch operation failed with error %d\n", e); | ||
1447 | goto failure; | ||
1448 | } else { | ||
1449 | nvhdcp_vdbg("wait AN_VALID ...\n"); | 1498 | nvhdcp_vdbg("wait AN_VALID ...\n"); |
1450 | 1499 | ||
1451 | hdcp_ta_ret = *pkt; | 1500 | /* wait for hardware to generate HDCP values */ |
1452 | nvhdcp_vdbg("An returned %x\n", e); | 1501 | e = wait_hdcp_ctrl(hdmi, AN_VALID | SROM_ERR, &res); |
1453 | if (hdcp_ta_ret) { | 1502 | if (e) { |
1454 | nvhdcp_err("An key generation timeout\n"); | 1503 | nvhdcp_err("An key generation timeout\n"); |
1455 | goto failure; | 1504 | goto failure; |
1456 | } | 1505 | } |
1457 | 1506 | if (res & SROM_ERR) { | |
1458 | /* check SROM return */ | ||
1459 | hdcp_ta_ret = *(pkt + HDCP_CMD_BYTE_OFFSET); | ||
1460 | if (hdcp_ta_ret) { | ||
1461 | nvhdcp_err("SROM error\n"); | 1507 | nvhdcp_err("SROM error\n"); |
1462 | goto failure; | 1508 | goto failure; |
1463 | } | 1509 | } |
1464 | } | ||
1465 | 1510 | ||
1466 | msleep(25); | 1511 | msleep(25); |
1467 | *pkt = HDCP_TA_CMD_AKSV; | 1512 | |
1468 | *(pkt + 1) = TEGRA_NVHDCP_PORT_HDMI; | 1513 | nvhdcp->a_ksv = get_aksv(hdmi); |
1469 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | 1514 | nvhdcp->a_n = get_an(hdmi); |
1470 | if (e) { | 1515 | nvhdcp_vdbg("Aksv is %016llx\n", nvhdcp->a_ksv); |
1471 | nvhdcp_err("te launch operation failed with error %d\n", e); | ||
1472 | goto failure; | ||
1473 | } else { | ||
1474 | hdcp_ta_ret = (u64)*pkt; | ||
1475 | nvhdcp->a_ksv = (u64)*(pkt + 1*HDCP_CMD_BYTE_OFFSET); | ||
1476 | nvhdcp->a_n = (u64)*(pkt + 2*HDCP_CMD_BYTE_OFFSET); | ||
1477 | nvhdcp_vdbg("Aksv is 0x%016llx\n", nvhdcp->a_ksv); | ||
1478 | nvhdcp_vdbg("An is 0x%016llx\n", nvhdcp->a_n); | 1516 | nvhdcp_vdbg("An is 0x%016llx\n", nvhdcp->a_n); |
1479 | /* check if verification of Aksv failed */ | 1517 | |
1480 | if (hdcp_ta_ret) { | 1518 | if (verify_ksv(nvhdcp->a_ksv)) { |
1481 | nvhdcp_err("Aksv verify failure\n"); | 1519 | nvhdcp_err("Aksv verify failure! (0x%016llx)\n", |
1520 | nvhdcp->a_ksv); | ||
1482 | goto disable; | 1521 | goto disable; |
1483 | } | 1522 | } |
1484 | } | 1523 | } |
1485 | #else | ||
1486 | set_bksv(hdmi, 0, (b_caps & BCAPS_REPEATER)); | ||
1487 | e = load_kfuse(hdmi); | ||
1488 | if (e) { | ||
1489 | nvhdcp_err("kfuse could not be loaded\n"); | ||
1490 | goto failure; | ||
1491 | } | ||
1492 | |||
1493 | usleep_range(20000, 25000); | ||
1494 | hdcp_ctrl_run(hdmi, 1); | ||
1495 | |||
1496 | nvhdcp_vdbg("wait AN_VALID ...\n"); | ||
1497 | |||
1498 | /* wait for hardware to generate HDCP values */ | ||
1499 | e = wait_hdcp_ctrl(hdmi, AN_VALID | SROM_ERR, &res); | ||
1500 | if (e) { | ||
1501 | nvhdcp_err("An key generation timeout\n"); | ||
1502 | goto failure; | ||
1503 | } | ||
1504 | if (res & SROM_ERR) { | ||
1505 | nvhdcp_err("SROM error\n"); | ||
1506 | goto failure; | ||
1507 | } | ||
1508 | |||
1509 | msleep(25); | ||
1510 | |||
1511 | nvhdcp->a_ksv = get_aksv(hdmi); | ||
1512 | nvhdcp->a_n = get_an(hdmi); | ||
1513 | nvhdcp_vdbg("Aksv is %016llx\n", nvhdcp->a_ksv); | ||
1514 | nvhdcp_vdbg("An is 0x%016llx\n", nvhdcp->a_n); | ||
1515 | |||
1516 | if (verify_ksv(nvhdcp->a_ksv)) { | ||
1517 | nvhdcp_err("Aksv verify failure! (0x%016llx)\n", nvhdcp->a_ksv); | ||
1518 | goto disable; | ||
1519 | } | ||
1520 | #endif | ||
1521 | |||
1522 | mutex_unlock(&nvhdcp->lock); | 1524 | mutex_unlock(&nvhdcp->lock); |
1523 | 1525 | ||
1524 | /* write Ainfo to receiver - set 1.1 only if b_caps supports it */ | 1526 | /* write Ainfo to receiver - set 1.1 only if b_caps supports it */ |
@@ -1564,47 +1566,48 @@ static void nvhdcp_downstream_worker(struct work_struct *work) | |||
1564 | } | 1566 | } |
1565 | nvhdcp_vdbg("Bksv is 0x%016llx\n", nvhdcp->b_ksv); | 1567 | nvhdcp_vdbg("Bksv is 0x%016llx\n", nvhdcp->b_ksv); |
1566 | 1568 | ||
1567 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | 1569 | if (tegra_dc_is_nvdisplay()) { |
1568 | *pkt = HDCP_TA_CMD_BKSV; | 1570 | *pkt = HDCP_TA_CMD_BKSV; |
1569 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; | 1571 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; |
1570 | *(pkt + 2*HDCP_CMD_OFFSET) = nvhdcp->b_ksv; | 1572 | *(pkt + 2*HDCP_CMD_OFFSET) = nvhdcp->b_ksv; |
1571 | *(pkt + 3*HDCP_CMD_OFFSET) = b_caps & BCAPS_REPEATER; | 1573 | *(pkt + 3*HDCP_CMD_OFFSET) = b_caps & BCAPS_REPEATER; |
1572 | *(pkt + 4*HDCP_CMD_OFFSET) = false; | 1574 | *(pkt + 4*HDCP_CMD_OFFSET) = false; |
1573 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | 1575 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); |
1574 | if (e) { | 1576 | if (e) { |
1575 | nvhdcp_err("te launch operation failed with error: %d\n", e); | 1577 | nvhdcp_err("te launch operation failed with error %d\n", |
1576 | goto failure; | 1578 | e); |
1577 | } else { | ||
1578 | /* check if Bksv verification was successful */ | ||
1579 | hdcp_ta_ret = (int)*pkt; | ||
1580 | if (hdcp_ta_ret) { | ||
1581 | nvhdcp_err("Bksv verify failure\n"); | ||
1582 | goto failure; | 1579 | goto failure; |
1583 | } else { | 1580 | } else { |
1584 | nvhdcp_vdbg("loaded Bksv into controller\n"); | 1581 | /* check if Bksv verification was successful */ |
1585 | /* check if R0 read was successful */ | ||
1586 | hdcp_ta_ret = (int)*pkt; | 1582 | hdcp_ta_ret = (int)*pkt; |
1587 | if (hdcp_ta_ret) { | 1583 | if (hdcp_ta_ret) { |
1588 | nvhdcp_err("R0 read failure\n"); | 1584 | nvhdcp_err("Bksv verify failure\n"); |
1589 | goto failure; | 1585 | goto failure; |
1586 | } else { | ||
1587 | nvhdcp_vdbg("loaded Bksv into controller\n"); | ||
1588 | /* check if R0 read was successful */ | ||
1589 | hdcp_ta_ret = (int)*pkt; | ||
1590 | if (hdcp_ta_ret) { | ||
1591 | nvhdcp_err("R0 read failure\n"); | ||
1592 | goto failure; | ||
1593 | } | ||
1590 | } | 1594 | } |
1591 | } | 1595 | } |
1592 | } | 1596 | } else { |
1593 | #else | 1597 | if (verify_ksv(nvhdcp->b_ksv)) { |
1594 | if (verify_ksv(nvhdcp->b_ksv)) { | 1598 | nvhdcp_err("Bksv verify failure!\n"); |
1595 | nvhdcp_err("Bksv verify failure!\n"); | 1599 | goto failure; |
1596 | goto failure; | 1600 | } |
1597 | } | ||
1598 | 1601 | ||
1599 | set_bksv(hdmi, nvhdcp->b_ksv, (b_caps & BCAPS_REPEATER)); | 1602 | set_bksv(hdmi, nvhdcp->b_ksv, (b_caps & BCAPS_REPEATER)); |
1600 | nvhdcp_vdbg("loaded Bksv into controller\n"); | 1603 | nvhdcp_vdbg("loaded Bksv into controller\n"); |
1601 | e = wait_hdcp_ctrl(hdmi, R0_VALID, NULL); | 1604 | e = wait_hdcp_ctrl(hdmi, R0_VALID, NULL); |
1602 | if (e) { | 1605 | if (e) { |
1603 | nvhdcp_err("R0 read failure!\n"); | 1606 | nvhdcp_err("R0 read failure!\n"); |
1604 | goto failure; | 1607 | goto failure; |
1608 | } | ||
1609 | nvhdcp_vdbg("R0 valid\n"); | ||
1605 | } | 1610 | } |
1606 | nvhdcp_vdbg("R0 valid\n"); | ||
1607 | #endif | ||
1608 | 1611 | ||
1609 | msleep(100); /* can't read R0' within 100ms of writing Aksv */ | 1612 | msleep(100); /* can't read R0' within 100ms of writing Aksv */ |
1610 | 1613 | ||
@@ -1619,23 +1622,26 @@ static void nvhdcp_downstream_worker(struct work_struct *work) | |||
1619 | } | 1622 | } |
1620 | 1623 | ||
1621 | mutex_lock(&nvhdcp->lock); | 1624 | mutex_lock(&nvhdcp->lock); |
1622 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | 1625 | |
1623 | *pkt = HDCP_TA_CMD_ENC; | 1626 | if (tegra_dc_is_nvdisplay()) { |
1624 | *(pkt + HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; | 1627 | *pkt = HDCP_TA_CMD_ENC; |
1625 | *(pkt + 2*HDCP_CMD_OFFSET) = b_caps; | 1628 | *(pkt + HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; |
1626 | e = te_launch_trusted_oper(pkt, PKT_SIZE/4, ta_cmd, ta_ctx); | 1629 | *(pkt + 2*HDCP_CMD_OFFSET) = b_caps; |
1627 | if (e) { | 1630 | e = te_launch_trusted_oper(pkt, PKT_SIZE/4, ta_cmd, ta_ctx); |
1628 | nvhdcp_err("te launch operation failed with error: %d\n", e); | 1631 | if (e) { |
1629 | goto failure; | 1632 | nvhdcp_err("te launch operation failed with error %d\n", |
1633 | e); | ||
1634 | goto failure; | ||
1635 | } | ||
1636 | enc = true; | ||
1637 | } else { | ||
1638 | tmp = tegra_sor_readl_ext(hdmi->sor, NV_SOR_TMDS_HDCP_CTRL); | ||
1639 | tmp |= CRYPT_ENABLED; | ||
1640 | if (b_caps & BCAPS_11) /* HDCP 1.1 ? */ | ||
1641 | tmp |= ONEONE_ENABLED; | ||
1642 | tegra_sor_writel_ext(hdmi->sor, NV_SOR_TMDS_HDCP_CTRL, tmp); | ||
1630 | } | 1643 | } |
1631 | enc = true; | 1644 | |
1632 | #else | ||
1633 | tmp = tegra_sor_readl_ext(hdmi->sor, NV_SOR_TMDS_HDCP_CTRL); | ||
1634 | tmp |= CRYPT_ENABLED; | ||
1635 | if (b_caps & BCAPS_11) /* HDCP 1.1 ? */ | ||
1636 | tmp |= ONEONE_ENABLED; | ||
1637 | tegra_sor_writel_ext(hdmi->sor, NV_SOR_TMDS_HDCP_CTRL, tmp); | ||
1638 | #endif | ||
1639 | nvhdcp_vdbg("CRYPT enabled\n"); | 1645 | nvhdcp_vdbg("CRYPT enabled\n"); |
1640 | mutex_unlock(&nvhdcp->lock); | 1646 | mutex_unlock(&nvhdcp->lock); |
1641 | 1647 | ||
@@ -1695,42 +1701,44 @@ failure: | |||
1695 | 1701 | ||
1696 | lost_hdmi: | 1702 | lost_hdmi: |
1697 | nvhdcp->state = STATE_UNAUTHENTICATED; | 1703 | nvhdcp->state = STATE_UNAUTHENTICATED; |
1698 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | 1704 | if (tegra_dc_is_nvdisplay()) { |
1699 | *pkt = HDCP_TA_CMD_CTRL; | 1705 | *pkt = HDCP_TA_CMD_CTRL; |
1700 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; | 1706 | *(pkt + 1*HDCP_CMD_OFFSET) = TEGRA_NVHDCP_PORT_HDMI; |
1701 | *(pkt + 2*HDCP_CMD_OFFSET) = HDCP_TA_CTRL_DISABLE; | 1707 | *(pkt + 2*HDCP_CMD_OFFSET) = HDCP_TA_CTRL_DISABLE; |
1702 | *(pkt + 3*HDCP_CMD_OFFSET) = false; | 1708 | *(pkt + 3*HDCP_CMD_OFFSET) = false; |
1703 | if (enc) { | 1709 | if (enc) { |
1704 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, ta_ctx); | 1710 | e = te_launch_trusted_oper(pkt, PKT_SIZE, ta_cmd, |
1705 | if (e) { | 1711 | ta_ctx); |
1706 | nvhdcp_err("te launch operation failed with error: %d\n", e); | 1712 | if (e) { |
1707 | goto failure; | 1713 | nvhdcp_err( |
1714 | "te launch operation failed with error: %d\n", | ||
1715 | e); | ||
1716 | goto failure; | ||
1717 | } | ||
1708 | } | 1718 | } |
1719 | } else { | ||
1720 | hdcp_ctrl_run(hdmi, 0); | ||
1709 | } | 1721 | } |
1710 | #else | ||
1711 | hdcp_ctrl_run(hdmi, 0); | ||
1712 | #endif | ||
1713 | |||
1714 | err: | 1722 | err: |
1715 | mutex_unlock(&nvhdcp->lock); | 1723 | mutex_unlock(&nvhdcp->lock); |
1716 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | 1724 | if (tegra_dc_is_nvdisplay()) { |
1717 | kfree(pkt); | 1725 | kfree(pkt); |
1718 | if (ta_ctx) { | 1726 | if (ta_ctx) { |
1719 | te_close_trusted_session(ta_ctx); | 1727 | te_close_trusted_session(ta_ctx); |
1720 | ta_ctx = NULL; | 1728 | ta_ctx = NULL; |
1729 | } | ||
1721 | } | 1730 | } |
1722 | #endif | ||
1723 | tegra_dc_io_end(dc); | 1731 | tegra_dc_io_end(dc); |
1724 | return; | 1732 | return; |
1725 | disable: | 1733 | disable: |
1726 | nvhdcp->state = STATE_OFF; | 1734 | nvhdcp->state = STATE_OFF; |
1727 | #if (defined(CONFIG_TEGRA_NVDISPLAY)) | 1735 | if (tegra_dc_is_nvdisplay()) { |
1728 | kfree(pkt); | 1736 | kfree(pkt); |
1729 | if (ta_ctx) { | 1737 | if (ta_ctx) { |
1730 | te_close_trusted_session(ta_ctx); | 1738 | te_close_trusted_session(ta_ctx); |
1731 | ta_ctx = NULL; | 1739 | ta_ctx = NULL; |
1740 | } | ||
1732 | } | 1741 | } |
1733 | #endif | ||
1734 | nvhdcp_set_plugged(nvhdcp, false); | 1742 | nvhdcp_set_plugged(nvhdcp, false); |
1735 | mutex_unlock(&nvhdcp->lock); | 1743 | mutex_unlock(&nvhdcp->lock); |
1736 | tegra_dc_io_end(dc); | 1744 | tegra_dc_io_end(dc); |