diff options
author | Suresh Mangipudi <smangipudi@nvidia.com> | 2015-09-10 23:53:35 -0400 |
---|---|---|
committer | Alexander Van Brunt <avanbrunt@nvidia.com> | 2015-10-01 21:57:03 -0400 |
commit | 0ccc89f705f28ae4c34e5d2bc732145731d2a46b (patch) | |
tree | ea9c26988c06c5139137450108fc8e957ed22e68 /drivers | |
parent | 14adae5e16f969560ecaee42b0d32b7aef781335 (diff) |
pinmux: tegra: Fix address offset for pex
Pex register offset was updated wrong, fixing it here.
Change-Id: I405f96f9f21368920c967a7a4859df4138d69cd8
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/797495
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/808265
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/pinctrl/pinctrl-tegra186.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra186.c b/drivers/pinctrl/pinctrl-tegra186.c index ac640f121..9d1c54c27 100644 --- a/drivers/pinctrl/pinctrl-tegra186.c +++ b/drivers/pinctrl/pinctrl-tegra186.c | |||
@@ -3442,12 +3442,12 @@ static const struct tegra_pingroup tegra186_groups[] = { | |||
3442 | PINGROUP(dp_aux_ch1_hpd_pp1, DP, RSVD1, RSVD2, RSVD3, 0x10028, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3442 | PINGROUP(dp_aux_ch1_hpd_pp1, DP, RSVD1, RSVD2, RSVD3, 0x10028, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3443 | PINGROUP(hdmi_cec_pp2, HDMI, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3443 | PINGROUP(hdmi_cec_pp2, HDMI, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3444 | PINGROUP(pex_l2_clkreq_n_pa6, PE2, GP, SATA, RSVD3, 0x7000, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3444 | PINGROUP(pex_l2_clkreq_n_pa6, PE2, GP, SATA, RSVD3, 0x7000, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3445 | PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x7004, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3445 | PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3446 | PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x700c, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3446 | PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3447 | PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x7014, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3447 | PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3448 | PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x701c, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3448 | PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3449 | PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x7024, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3449 | PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3450 | PINGROUP(pex_l2_rst_n_pa5, PE2, SOC, SATA, RSVD3, 0x702c, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), | 3450 | PINGROUP(pex_l2_rst_n_pa5, PE2, SOC, SATA, RSVD3, 0x7030, 0, Y, 5, 6, 8, -1, 10, 11, 12, N, -1, -1, N), |
3451 | PINGROUP(sdmmc1_clk_pd0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y), | 3451 | PINGROUP(sdmmc1_clk_pd0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y), |
3452 | PINGROUP(sdmmc1_cmd_pd1, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y), | 3452 | PINGROUP(sdmmc1_cmd_pd1, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y), |
3453 | PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, Y, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N), | 3453 | PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, Y, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N), |