video dsi: tegra: Fix support for hs clk in lp mode

Enables high speed clock on mipi lanes in low power mode.

Change-Id: I3b05d7f9bc5e8f63483220100f3361904e627c52
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/69951
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R3eba480195866b3cf03040949b179aaadd169916

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 0dff9925b..92a77e313 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -1244,7 +1244,8 @@ static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
 
         tegra_dsi_set_control_reg_hs(dsi);
 
-        if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS)
+        if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
+                dsi->info.enable_hs_clock_on_lp_cmd_mode)
                 tegra_dsi_hs_clk_out_enable(dsi);
 
         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;