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authorAnimesh Kishore <ankishore@nvidia.com>2012-02-22 10:37:00 -0500
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:02:08 -0400
commit5cc06c2fb1d9f765ee39f712278e7f3a57429b40 (patch)
treed8f55dfd3c795f8fe998204d1ac34e4d6ebedcef /drivers/video
parent3438b1bf9dbcf4a35e286eb0db907fce39dac547 (diff)
video: tegra: dsi: Fix dsi phy timing
Corrected the formulas to calculate phy timing. Added mipi d-phy constraints. Bug 938043 Change-Id: Ie1f2dd45e7e39f83735fe28e21a62dc0415c7c00 Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/85217 Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Rebase-Id: R96bda43f840b8fc2f0c7676fe21d3a7162b5cd24
Diffstat (limited to 'drivers/video')
-rw-r--r--drivers/video/tegra/dc/dsi.c330
-rw-r--r--drivers/video/tegra/dc/dsi.h192
2 files changed, 423 insertions, 99 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 77725e4a8..42bec9f69 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -118,6 +118,8 @@ struct tegra_dc_dsi_data {
118 118
119 struct dsi_status status; 119 struct dsi_status status;
120 120
121 struct dsi_phy_timing_inclk phy_timing;
122
121 u8 driven_mode; 123 u8 driven_mode;
122 u8 controller_index; 124 u8 controller_index;
123 125
@@ -510,63 +512,313 @@ static void tegra_dsi_init_sw(struct tegra_dc *dc,
510 512
511} 513}
512 514
515#define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns) ( \
516 (platform_t_phy_ns) ? ( \
517 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns)) < 0 ? 0 : \
518 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns)))) : \
519 ((default_phy) < 0 ? 0 : (default_phy)))
520
521static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
522 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
523{
524 phy_timing_clk->t_tlpx = SELECT_T_PHY(
525 dsi->info.phy_timing.t_tlpx_ns,
526 T_TLPX_DEFAULT(clk_ns), clk_ns);
527
528 phy_timing_clk->t_clktrail = SELECT_T_PHY(
529 dsi->info.phy_timing.t_clktrail_ns,
530 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns);
531
532 phy_timing_clk->t_clkpost = SELECT_T_PHY(
533 dsi->info.phy_timing.t_clkpost_ns,
534 T_CLKPOST_DEFAULT(clk_ns), clk_ns);
535
536 phy_timing_clk->t_clkzero = SELECT_T_PHY(
537 dsi->info.phy_timing.t_clkzero_ns,
538 T_CLKZERO_DEFAULT(clk_ns), clk_ns);
539
540 phy_timing_clk->t_clkprepare = SELECT_T_PHY(
541 dsi->info.phy_timing.t_clkprepare_ns,
542 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns);
543
544 phy_timing_clk->t_clkpre = SELECT_T_PHY(
545 dsi->info.phy_timing.t_clkpre_ns,
546 T_CLKPRE_DEFAULT, clk_ns);
547}
548
549static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
550 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
551{
552 phy_timing_clk->t_tlpx = SELECT_T_PHY(
553 dsi->info.phy_timing.t_tlpx_ns,
554 T_TLPX_DEFAULT(clk_ns), clk_ns);
555
556 phy_timing_clk->t_hsdexit = SELECT_T_PHY(
557 dsi->info.phy_timing.t_hsdexit_ns,
558 T_HSEXIT_DEFAULT(clk_ns), clk_ns);
559
560 phy_timing_clk->t_hstrail = SELECT_T_PHY(
561 dsi->info.phy_timing.t_hstrail_ns,
562 T_HSTRAIL_DEFAULT(clk_ns), clk_ns);
563
564 phy_timing_clk->t_datzero = SELECT_T_PHY(
565 dsi->info.phy_timing.t_datzero_ns,
566 T_DATZERO_DEFAULT(clk_ns), clk_ns);
567
568 phy_timing_clk->t_hsprepare = SELECT_T_PHY(
569 dsi->info.phy_timing.t_hsprepare_ns,
570 T_HSPREPARE_DEFAULT(clk_ns), clk_ns);
571}
572
573static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
574 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
575{
576 phy_timing_clk->t_tlpx = SELECT_T_PHY(
577 dsi->info.phy_timing.t_tlpx_ns,
578 T_TLPX_DEFAULT(clk_ns), clk_ns);
579}
580
581static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
582 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
583{
584 phy_timing_clk->t_tlpx = SELECT_T_PHY(
585 dsi->info.phy_timing.t_tlpx_ns,
586 T_TLPX_DEFAULT(clk_ns), clk_ns);
587
588 phy_timing_clk->t_taget = SELECT_T_PHY(
589 dsi->info.phy_timing.t_taget_ns,
590 T_TAGET_DEFAULT(clk_ns), clk_ns);
591
592 phy_timing_clk->t_tasure = SELECT_T_PHY(
593 dsi->info.phy_timing.t_tasure_ns,
594 T_TASURE_DEFAULT(clk_ns), clk_ns);
595
596 phy_timing_clk->t_tago = SELECT_T_PHY(
597 dsi->info.phy_timing.t_tago_ns,
598 T_TAGO_DEFAULT(clk_ns), clk_ns);
599}
600
601static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
602 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
603{
604 phy_timing_clk->t_tlpx = SELECT_T_PHY(
605 dsi->info.phy_timing.t_tlpx_ns,
606 T_TLPX_DEFAULT(clk_ns), clk_ns);
607
608 phy_timing_clk->t_wakeup = SELECT_T_PHY(
609 dsi->info.phy_timing.t_wakeup_ns,
610 T_WAKEUP_DEFAULT, clk_ns);
611}
612
613#undef SELECT_T_PHY
614
513static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi, 615static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
514 struct dsi_phy_timing_inclk *phy_timing_clk, 616 struct dsi_phy_timing_inclk *phy_timing_clk,
515 u32 clk_ns) 617 u32 clk_ns, u8 lphs)
516{ 618{
619 if (lphs == DSI_LPHS_IN_HS_MODE) {
620 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
621 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
622 } else {
623 /* default is LP mode */
624 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
625 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
626 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
627 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
628 tegra_dsi_get_clk_phy_timing
629 (dsi, phy_timing_clk, clk_ns);
630 }
631}
517 632
518 phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ? 633static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
519 (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) : 634 struct dsi_phy_timing_inclk *phy_timing,
520 (T_HSEXIT_DEFAULT(clk_ns)); 635 u32 clk_ns, u8 lphs)
636{
637#define CHECK_RANGE(val, min, max) ( \
638 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
639 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
521 640
522 phy_timing_clk->t_hstrail = dsi->info.phy_timing.t_hstrail_ns ? 641 int err = 0;
523 (dsi->info.phy_timing.t_hstrail_ns / clk_ns) :
524 (T_HSTRAIL_DEFAULT(clk_ns));
525 642
526 phy_timing_clk->t_datzero = dsi->info.phy_timing.t_datzero_ns ? 643 err = CHECK_RANGE(
527 (dsi->info.phy_timing.t_datzero_ns / clk_ns) : 644 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_tlpx, clk_ns),
528 (T_DATZERO_DEFAULT(clk_ns)); 645 MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
646 if (err < 0) {
647 dev_warn(&dsi->dc->ndev->dev,
648 "dsi: Tlpx mipi range violated\n");
649 goto fail;
650 }
529 651
530 phy_timing_clk->t_hsprepr = dsi->info.phy_timing.t_hsprepr_ns ? 652 if (lphs == DSI_LPHS_IN_HS_MODE) {
531 (dsi->info.phy_timing.t_hsprepr_ns / clk_ns) : 653 err = CHECK_RANGE(
532 (T_HSPREPR_DEFAULT(clk_ns)); 654 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hsdexit, clk_ns),
655 MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
656 if (err < 0) {
657 dev_warn(&dsi->dc->ndev->dev,
658 "dsi: HsExit mipi range violated\n");
659 goto fail;
660 }
533 661
534 phy_timing_clk->t_clktrail = dsi->info.phy_timing.t_clktrail_ns ? 662 err = CHECK_RANGE(
535 (dsi->info.phy_timing.t_clktrail_ns / clk_ns) : 663 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hstrail, clk_ns),
536 (T_CLKTRAIL_DEFAULT(clk_ns)); 664 MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
665 if (err < 0) {
666 dev_warn(&dsi->dc->ndev->dev,
667 "dsi: HsTrail mipi range violated\n");
668 goto fail;
669 }
537 670
538 phy_timing_clk->t_clkpost = dsi->info.phy_timing.t_clkpost_ns ? 671 err = CHECK_RANGE(
539 (dsi->info.phy_timing.t_clkpost_ns / clk_ns) : 672 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_datzero, clk_ns),
540 (T_CLKPOST_DEFAULT(clk_ns)); 673 MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
674 if (err < 0) {
675 dev_warn(&dsi->dc->ndev->dev,
676 "dsi: HsZero mipi range violated\n");
677 goto fail;
678 }
541 679
542 phy_timing_clk->t_clkzero = dsi->info.phy_timing.t_clkzero_ns ? 680 err = CHECK_RANGE(
543 (dsi->info.phy_timing.t_clkzero_ns / clk_ns) : 681 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_hsprepare, clk_ns),
544 (T_CLKZERO_DEFAULT(clk_ns)); 682 MIPI_T_HSPREPARE_NS_MIN(clk_ns),
683 MIPI_T_HSPREPARE_NS_MAX(clk_ns));
684 if (err < 0) {
685 dev_warn(&dsi->dc->ndev->dev,
686 "dsi: HsPrepare mipi range violated\n");
687 goto fail;
688 }
545 689
546 phy_timing_clk->t_tlpx = dsi->info.phy_timing.t_tlpx_ns ? 690 err = CHECK_RANGE(
547 (dsi->info.phy_timing.t_tlpx_ns / clk_ns) : 691 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
548 (T_TLPX_DEFAULT(clk_ns)); 692 phy_timing->t_hsprepare, clk_ns) +
693 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_datzero, clk_ns),
694 MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
695 MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
696 if (err < 0) {
697 dev_warn(&dsi->dc->ndev->dev,
698 "dsi: HsPrepare + HsZero mipi range violated\n");
699 goto fail;
700 }
701 } else {
702 /* default is LP mode */
703 err = CHECK_RANGE(
704 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_wakeup, clk_ns),
705 MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
706 if (err < 0) {
707 dev_warn(&dsi->dc->ndev->dev,
708 "dsi: WakeUp mipi range violated\n");
709 goto fail;
710 }
711
712 err = CHECK_RANGE(
713 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_tasure, clk_ns),
714 MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
715 phy_timing->t_tlpx, clk_ns)),
716 MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
717 phy_timing->t_tlpx, clk_ns)));
718 if (err < 0) {
719 dev_warn(&dsi->dc->ndev->dev,
720 "dsi: TaSure mipi range violated\n");
721 goto fail;
722 }
723 }
724
725 if (lphs == DSI_LPHS_IN_HS_MODE ||
726 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
727 err = CHECK_RANGE(
728 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clktrail, clk_ns),
729 MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
730 if (err < 0) {
731 dev_warn(&dsi->dc->ndev->dev,
732 "dsi: ClkTrail mipi range violated\n");
733 goto fail;
734 }
735
736 err = CHECK_RANGE(
737 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkpost, clk_ns),
738 MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
739 if (err < 0) {
740 dev_warn(&dsi->dc->ndev->dev,
741 "dsi: ClkPost mipi range violated\n");
742 goto fail;
743 }
744
745 err = CHECK_RANGE(
746 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkzero, clk_ns),
747 MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
748 if (err < 0) {
749 dev_warn(&dsi->dc->ndev->dev,
750 "dsi: ClkZero mipi range violated\n");
751 goto fail;
752 }
753
754 err = CHECK_RANGE(
755 DSI_CONVERT_T_PHY_TO_T_PHY_NS
756 (phy_timing->t_clkprepare, clk_ns),
757 MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
758 if (err < 0) {
759 dev_warn(&dsi->dc->ndev->dev,
760 "dsi: ClkPrepare mipi range violated\n");
761 goto fail;
762 }
763
764 err = CHECK_RANGE(
765 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkpre, clk_ns),
766 MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
767 if (err < 0) {
768 dev_warn(&dsi->dc->ndev->dev,
769 "dsi: ClkPre mipi range violated\n");
770 goto fail;
771 }
772
773 err = CHECK_RANGE(
774 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
775 phy_timing->t_clkprepare, clk_ns) +
776 DSI_CONVERT_T_PHY_TO_T_PHY_NS(phy_timing->t_clkzero, clk_ns),
777 MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
778 MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
779 if (err < 0) {
780 dev_warn(&dsi->dc->ndev->dev,
781 "dsi: ClkPrepare + ClkZero mipi range violated\n");
782 goto fail;
783 }
784 }
785fail:
786#undef CHECK_RANGE
787 return err;
788}
789
790static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
791 struct dsi_phy_timing_inclk *phy_timing,
792 u32 clk_ns, u8 lphs)
793{
794 int err = 0;
549 795
550 phy_timing_clk->t_clkpre = T_CLKPRE_DEFAULT(clk_ns); 796 err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
551 phy_timing_clk->t_clkprepare = T_CLKPREPARE_DEFAULT(clk_ns); 797 if (err < 0) {
552 phy_timing_clk->t_wakeup = T_WAKEUP_DEFAULT(clk_ns); 798 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
799 goto fail;
800 }
553 801
554 phy_timing_clk->t_taget = 5 * phy_timing_clk->t_tlpx; 802 /* TODO: add more contraints */
555 phy_timing_clk->t_tasure = 2 * phy_timing_clk->t_tlpx; 803fail:
556 phy_timing_clk->t_tago = 4 * phy_timing_clk->t_tlpx; 804 return err;
557} 805}
558 806
559static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi) 807static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
560{ 808{
561 u32 val; 809 u32 val;
562 struct dsi_phy_timing_inclk phy_timing; 810 struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
563 811
564 tegra_dsi_get_phy_timing(dsi, &phy_timing, dsi->current_bit_clk_ns); 812 tegra_dsi_get_phy_timing
813 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
814
815 tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
816 dsi->current_bit_clk_ns, lphs);
565 817
566 val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) | 818 val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
567 DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) | 819 DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
568 DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) | 820 DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
569 DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepr); 821 DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
570 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0); 822 tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
571 823
572 val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) | 824 val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
@@ -584,6 +836,8 @@ static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi)
584 DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) | 836 DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
585 DSI_BTA_TIMING_TTAGO(phy_timing.t_tago); 837 DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
586 tegra_dsi_writel(dsi, val, DSI_BTA_TIMING); 838 tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
839
840 dsi->phy_timing = phy_timing;
587} 841}
588 842
589static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc, 843static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
@@ -1151,7 +1405,7 @@ static int tegra_dsi_init_hw(struct tegra_dc *dc,
1151 } 1405 }
1152 1406
1153 /* TODO: only need to change the timing for bta */ 1407 /* TODO: only need to change the timing for bta */
1154 tegra_dsi_set_phy_timing(dsi); 1408 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1155 1409
1156 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) 1410 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1157 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi); 1411 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
@@ -1211,6 +1465,8 @@ static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
1211 tegra_dsi_set_timeout(dsi); 1465 tegra_dsi_set_timeout(dsi);
1212 } 1466 }
1213 1467
1468 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
1469
1214 tegra_dsi_set_control_reg_lp(dsi); 1470 tegra_dsi_set_control_reg_lp(dsi);
1215 1471
1216 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) && 1472 if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
@@ -1250,7 +1506,7 @@ static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
1250 tegra_dsi_set_timeout(dsi); 1506 tegra_dsi_set_timeout(dsi);
1251 } 1507 }
1252 1508
1253 tegra_dsi_set_phy_timing(dsi); 1509 tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
1254 1510
1255 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) { 1511 if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
1256 tegra_dsi_set_pkt_seq(dc, dsi); 1512 tegra_dsi_set_pkt_seq(dc, dsi);
diff --git a/drivers/video/tegra/dc/dsi.h b/drivers/video/tegra/dc/dsi.h
index d86a60a50..f8f05f23c 100644
--- a/drivers/video/tegra/dc/dsi.h
+++ b/drivers/video/tegra/dc/dsi.h
@@ -18,7 +18,7 @@
18#define __DRIVERS_VIDEO_TEGRA_DC_DSI_H__ 18#define __DRIVERS_VIDEO_TEGRA_DC_DSI_H__
19 19
20/* source of video data */ 20/* source of video data */
21enum{ 21enum {
22 TEGRA_DSI_VIDEO_DRIVEN_BY_DC, 22 TEGRA_DSI_VIDEO_DRIVEN_BY_DC,
23 TEGRA_DSI_VIDEO_DRIVEN_BY_HOST, 23 TEGRA_DSI_VIDEO_DRIVEN_BY_HOST,
24}; 24};
@@ -31,7 +31,7 @@ enum{
31/* DCS commands for command mode */ 31/* DCS commands for command mode */
32#define DSI_ENTER_PARTIAL_MODE 0x12 32#define DSI_ENTER_PARTIAL_MODE 0x12
33#define DSI_SET_PIXEL_FORMAT 0x3A 33#define DSI_SET_PIXEL_FORMAT 0x3A
34#define DSI_AREA_COLOR_MODE 0x4C 34#define DSI_AREA_COLOR_MODE 0x4C
35#define DSI_SET_PARTIAL_AREA 0x30 35#define DSI_SET_PARTIAL_AREA 0x30
36#define DSI_SET_PAGE_ADDRESS 0x2B 36#define DSI_SET_PAGE_ADDRESS 0x2B
37#define DSI_SET_ADDRESS_MODE 0x36 37#define DSI_SET_ADDRESS_MODE 0x36
@@ -151,7 +151,7 @@ enum {
151 * TODO: are DSI_HOST_DSI_CONTROL_CRC_RESET(RESET_CRC) and 151 * TODO: are DSI_HOST_DSI_CONTROL_CRC_RESET(RESET_CRC) and
152 * DSI_HOST_DSI_CONTROL_HOST_TX_TRIG_SRC(IMMEDIATE) required for everyone? 152 * DSI_HOST_DSI_CONTROL_HOST_TX_TRIG_SRC(IMMEDIATE) required for everyone?
153 */ 153 */
154#define HOST_DSI_CTRL_COMMON \ 154#define HOST_DSI_CTRL_COMMON \
155 (DSI_HOST_DSI_CONTROL_PHY_CLK_DIV(DSI_PHY_CLK_DIV1) | \ 155 (DSI_HOST_DSI_CONTROL_PHY_CLK_DIV(DSI_PHY_CLK_DIV1) | \
156 DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL) | \ 156 DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL) | \
157 DSI_HOST_DSI_CONTROL_PERIPH_RESET(TEGRA_DSI_DISABLE) | \ 157 DSI_HOST_DSI_CONTROL_PERIPH_RESET(TEGRA_DSI_DISABLE) | \
@@ -171,26 +171,26 @@ enum {
171#define DSI_CTRL_HOST_DRIVEN (DSI_CONTROL_VID_ENABLE(TEGRA_DSI_DISABLE) | \ 171#define DSI_CTRL_HOST_DRIVEN (DSI_CONTROL_VID_ENABLE(TEGRA_DSI_DISABLE) | \
172 DSI_CONTROL_HOST_ENABLE(TEGRA_DSI_ENABLE)) 172 DSI_CONTROL_HOST_ENABLE(TEGRA_DSI_ENABLE))
173 173
174#define DSI_CTRL_DC_DRIVEN (DSI_CONTROL_VID_TX_TRIG_SRC(SOL) | \ 174#define DSI_CTRL_DC_DRIVEN (DSI_CONTROL_VID_TX_TRIG_SRC(SOL) | \
175 DSI_CONTROL_VID_ENABLE(TEGRA_DSI_ENABLE) | \ 175 DSI_CONTROL_VID_ENABLE(TEGRA_DSI_ENABLE) | \
176 DSI_CONTROL_HOST_ENABLE(TEGRA_DSI_DISABLE)) 176 DSI_CONTROL_HOST_ENABLE(TEGRA_DSI_DISABLE))
177 177
178#define DSI_CTRL_CMD_MODE (DSI_CONTROL_VID_DCS_ENABLE(TEGRA_DSI_ENABLE)) 178#define DSI_CTRL_CMD_MODE (DSI_CONTROL_VID_DCS_ENABLE(TEGRA_DSI_ENABLE))
179 179
180#define DSI_CTRL_VIDEO_MODE (DSI_CONTROL_VID_DCS_ENABLE(TEGRA_DSI_DISABLE)) 180#define DSI_CTRL_VIDEO_MODE (DSI_CONTROL_VID_DCS_ENABLE(TEGRA_DSI_DISABLE))
181 181
182 182
183enum { 183enum {
184 CMD_VS = 0x01, 184 CMD_VS = 0x01,
185 CMD_VE = 0x11, 185 CMD_VE = 0x11,
186 186
187 CMD_HS = 0x21, 187 CMD_HS = 0x21,
188 CMD_HE = 0x31, 188 CMD_HE = 0x31,
189 189
190 CMD_EOT = 0x08, 190 CMD_EOT = 0x08,
191 CMD_NULL = 0x09, 191 CMD_NULL = 0x09,
192 CMD_SHORTW = 0x15, 192 CMD_SHORTW = 0x15,
193 CMD_BLNK = 0x19, 193 CMD_BLNK = 0x19,
194 CMD_LONGW = 0x39, 194 CMD_LONGW = 0x39,
195 195
196 CMD_RGB = 0x00, 196 CMD_RGB = 0x00,
@@ -200,80 +200,148 @@ enum {
200 CMD_RGB_24BPP = 0x3E, 200 CMD_RGB_24BPP = 0x3E,
201}; 201};
202 202
203#define PKT_ID0(id) DSI_PKT_SEQ_0_LO_PKT_00_ID(id) | \ 203#define PKT_ID0(id) (DSI_PKT_SEQ_0_LO_PKT_00_ID(id) | \
204 DSI_PKT_SEQ_1_LO_PKT_10_EN(TEGRA_DSI_ENABLE) 204 DSI_PKT_SEQ_1_LO_PKT_10_EN(TEGRA_DSI_ENABLE))
205#define PKT_LEN0(len) DSI_PKT_SEQ_0_LO_PKT_00_SIZE(len) 205#define PKT_LEN0(len) (DSI_PKT_SEQ_0_LO_PKT_00_SIZE(len))
206 206
207#define PKT_ID1(id) DSI_PKT_SEQ_0_LO_PKT_01_ID(id) | \ 207#define PKT_ID1(id) (DSI_PKT_SEQ_0_LO_PKT_01_ID(id) | \
208 DSI_PKT_SEQ_1_LO_PKT_11_EN(TEGRA_DSI_ENABLE) 208 DSI_PKT_SEQ_1_LO_PKT_11_EN(TEGRA_DSI_ENABLE))
209#define PKT_LEN1(len) DSI_PKT_SEQ_0_LO_PKT_01_SIZE(len) 209#define PKT_LEN1(len) (DSI_PKT_SEQ_0_LO_PKT_01_SIZE(len))
210 210
211#define PKT_ID2(id) DSI_PKT_SEQ_0_LO_PKT_02_ID(id) | \ 211#define PKT_ID2(id) (DSI_PKT_SEQ_0_LO_PKT_02_ID(id) | \
212 DSI_PKT_SEQ_1_LO_PKT_12_EN(TEGRA_DSI_ENABLE) 212 DSI_PKT_SEQ_1_LO_PKT_12_EN(TEGRA_DSI_ENABLE))
213#define PKT_LEN2(len) DSI_PKT_SEQ_0_LO_PKT_02_SIZE(len) 213#define PKT_LEN2(len) (DSI_PKT_SEQ_0_LO_PKT_02_SIZE(len))
214 214
215#define PKT_ID3(id) DSI_PKT_SEQ_0_HI_PKT_03_ID(id) | \ 215#define PKT_ID3(id) (DSI_PKT_SEQ_0_HI_PKT_03_ID(id) | \
216 DSI_PKT_SEQ_1_HI_PKT_13_EN(TEGRA_DSI_ENABLE) 216 DSI_PKT_SEQ_1_HI_PKT_13_EN(TEGRA_DSI_ENABLE))
217#define PKT_LEN3(len) DSI_PKT_SEQ_0_HI_PKT_03_SIZE(len) 217#define PKT_LEN3(len) (DSI_PKT_SEQ_0_HI_PKT_03_SIZE(len))
218 218
219#define PKT_ID4(id) DSI_PKT_SEQ_0_HI_PKT_04_ID(id) | \ 219#define PKT_ID4(id) (DSI_PKT_SEQ_0_HI_PKT_04_ID(id) | \
220 DSI_PKT_SEQ_1_HI_PKT_14_EN(TEGRA_DSI_ENABLE) 220 DSI_PKT_SEQ_1_HI_PKT_14_EN(TEGRA_DSI_ENABLE))
221#define PKT_LEN4(len) DSI_PKT_SEQ_0_HI_PKT_04_SIZE(len) 221#define PKT_LEN4(len) (DSI_PKT_SEQ_0_HI_PKT_04_SIZE(len))
222 222
223#define PKT_ID5(id) DSI_PKT_SEQ_0_HI_PKT_05_ID(id) | \ 223#define PKT_ID5(id) (DSI_PKT_SEQ_0_HI_PKT_05_ID(id) | \
224 DSI_PKT_SEQ_1_HI_PKT_15_EN(TEGRA_DSI_ENABLE) 224 DSI_PKT_SEQ_1_HI_PKT_15_EN(TEGRA_DSI_ENABLE))
225#define PKT_LEN5(len) DSI_PKT_SEQ_0_HI_PKT_05_SIZE(len) 225#define PKT_LEN5(len) (DSI_PKT_SEQ_0_HI_PKT_05_SIZE(len))
226 226
227#define PKT_LP DSI_PKT_SEQ_0_LO_SEQ_0_FORCE_LP(TEGRA_DSI_ENABLE) 227#define PKT_LP (DSI_PKT_SEQ_0_LO_SEQ_0_FORCE_LP(TEGRA_DSI_ENABLE))
228 228
229#define NUMOF_PKT_SEQ 12 229#define NUMOF_PKT_SEQ 12
230 230
231 231/* Mipi v1.00.00 phy timing range */
232/* Macros for calculating the phy timings */ 232#define NOT_DEFINED -1
233#define T_HSEXIT_DEFAULT(clkns) (100 / ((clkns) * 8) + 1) 233#define MIPI_T_HSEXIT_NS_MIN 100
234#define T_HSTRAIL_DEFAULT(clkns) (3 + max((8 * (clkns)), \ 234#define MIPI_T_HSEXIT_NS_MAX NOT_DEFINED
235 (60 + 4 * (clkns))) / ((clkns) * 8) + 1) 235#define MIPI_T_HSTRAIL_NS_MIN(clk_ns) max((8 * (clk_ns)), (60 + 4 * (clk_ns)))
236#define T_HSPREPR_ORG(clkns) ((65 + 5 * (clkns)) / ((clkns) * 8)) 236#define MIPI_T_HSTRAIL_NS_MAX NOT_DEFINED
237#define T_HSPREPR_DEFAULT(clkns) ((T_HSPREPR_ORG(clkns) == 0) ? \ 237#define MIPI_T_HSZERO_NS_MIN NOT_DEFINED
238 1 : T_HSPREPR_ORG(clkns)) 238#define MIPI_T_HSZERO_NS_MAX NOT_DEFINED
239#define T_DATZERO_DEFAULT(clkns) ((145 + 5 * (clkns)) / ((clkns) * 8) +1) 239#define MIPI_T_HSPREPARE_NS_MIN(clk_ns) (40 + 4 * (clk_ns))
240 240#define MIPI_T_HSPREPARE_NS_MAX(clk_ns) (85 + 6 * (clk_ns))
241#define T_CLKTRAIL_DEFAULT(clkns) (60 / ((clkns) * 8) + 1) 241#define MIPI_T_CLKTRAIL_NS_MIN 60
242#define T_CLKPOST_DEFAULT(clkns) ((60 + 52 * (clkns)) / ((clkns) * 8) +1) 242#define MIPI_T_CLKTRAIL_NS_MAX NOT_DEFINED
243#define T_CLKZERO_DEFAULT(clkns) (170 / ((clkns) * 8) + 1) 243#define MIPI_T_CLKPOST_NS_MIN(clk_ns) (60 + 52 * (clk_ns))
244#define T_TLPX_ORG(clkns) (50 / ((clkns) * 8) + 1) 244#define MIPI_T_CLKPOST_NS_MAX NOT_DEFINED
245#define T_TLPX_DEFAULT(clkns) ((T_TLPX_ORG(clkns) == 0) ? \ 245#define MIPI_T_CLKZERO_NS_MIN NOT_DEFINED
246 1 : T_TLPX_ORG(clkns)) 246#define MIPI_T_CLKZERO_NS_MAX NOT_DEFINED
247 247#define MIPI_T_TLPX_NS_MIN 50
248#define T_CLKPRE_DEFAULT(clkns) 1 248#define MIPI_T_TLPX_NS_MAX NOT_DEFINED
249#define T_CLKPREPARE_DEFAULT(clkns) 4 249#define MIPI_T_CLKPREPARE_NS_MIN 38
250 250#define MIPI_T_CLKPREPARE_NS_MAX 95
251/* Minimum ULPM wakeup time as per the spec is 1msec */ 251#define MIPI_T_CLKPRE_NS_MIN 8
252#define T_WAKEUP_DEFAULT(clkns) (2*1000*1000 / (clkns)) 252#define MIPI_T_CLKPRE_NS_MAX NOT_DEFINED
253 253#define MIPI_T_WAKEUP_NS_MIN 1
254#define DSI_CYCLE_COUNTER_VALUE 512 254#define MIPI_T_WAKEUP_NS_MAX NOT_DEFINED
255#define MIPI_T_TASURE_NS_MIN(tlpx_ns) (tlpx_ns)
256#define MIPI_T_TASURE_NS_MAX(tlpx_ns) (2 * (tlpx_ns))
257#define MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns) (145 + 10 * (clk_ns))
258#define MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX NOT_DEFINED
259#define MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN 300
260#define MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX NOT_DEFINED
261
262#define DSI_TBYTE(clk_ns) ((clk_ns) * (BITS_PER_BYTE))
263#define DSI_CONVERT_T_PHY_NS_TO_T_PHY(t_phy_ns, clk_ns) \
264 ((int)((DIV_ROUND_CLOSEST((t_phy_ns), \
265 (DSI_TBYTE(clk_ns)))) - 1))
266
267#define DSI_CONVERT_T_PHY_TO_T_PHY_NS(t_phy, clk_ns) \
268 (((t_phy) + 1) * (DSI_TBYTE(clk_ns)))
269
270/* Default phy timing in ns */
271#define T_HSEXIT_NS_DEFAULT 120
272#define T_HSTRAIL_NS_DEFAULT(clk_ns) \
273 max((8 * (clk_ns)), (60 + 4 * (clk_ns)))
274
275#define T_DATZERO_NS_DEFAULT(clk_ns) (145 + 5 * (clk_ns))
276#define T_HSPREPARE_NS_DEFAULT(clk_ns) (65 + 5 * (clk_ns))
277#define T_CLKTRAIL_NS_DEFAULT 80
278#define T_CLKPOST_NS_DEFAULT(clk_ns) (70 + 52 * (clk_ns))
279#define T_CLKZERO_NS_DEFAULT 260
280#define T_TLPX_NS_DEFAULT 60
281#define T_CLKPREPARE_NS_DEFAULT 65
282#define T_TAGO_NS_DEFAULT (4 * (T_TLPX_NS_DEFAULT))
283#define T_TASURE_NS_DEFAULT (2 * (T_TLPX_NS_DEFAULT))
284#define T_TAGET_NS_DEFAULT (5 * (T_TLPX_NS_DEFAULT))
285
286/* Default phy timing reg values */
287#define T_HSEXIT_DEFAULT(clk_ns) \
288(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_HSEXIT_NS_DEFAULT, clk_ns))
289
290#define T_HSTRAIL_DEFAULT(clk_ns) \
291(3 + (DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_HSTRAIL_NS_DEFAULT(clk_ns), clk_ns)))
292
293#define T_DATZERO_DEFAULT(clk_ns) \
294(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_DATZERO_NS_DEFAULT(clk_ns), clk_ns))
295
296#define T_HSPREPARE_DEFAULT(clk_ns) \
297(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_HSPREPARE_NS_DEFAULT(clk_ns), clk_ns))
298
299#define T_CLKTRAIL_DEFAULT(clk_ns) \
300(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_CLKTRAIL_NS_DEFAULT, clk_ns))
301
302#define T_CLKPOST_DEFAULT(clk_ns) \
303(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_CLKPOST_NS_DEFAULT(clk_ns), clk_ns))
304
305#define T_CLKZERO_DEFAULT(clk_ns) \
306(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_CLKZERO_NS_DEFAULT, clk_ns))
307
308#define T_TLPX_DEFAULT(clk_ns) \
309(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_TLPX_NS_DEFAULT, clk_ns))
310
311#define T_CLKPREPARE_DEFAULT(clk_ns) \
312(DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_CLKPREPARE_NS_DEFAULT, clk_ns))
313
314#define T_CLKPRE_DEFAULT 0x1
315#define T_WAKEUP_DEFAULT 0x7f
316
317#define T_TAGO_DEFAULT(clk_ns) \
318DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_TAGO_NS_DEFAULT, clk_ns)
319
320#define T_TASURE_DEFAULT(clk_ns) \
321DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_TASURE_NS_DEFAULT, clk_ns)
322
323#define T_TAGET_DEFAULT(clk_ns) \
324DSI_CONVERT_T_PHY_NS_TO_T_PHY(T_TAGET_NS_DEFAULT, clk_ns)
255 325
256/* Defines the DSI phy timing parameters */ 326/* Defines the DSI phy timing parameters */
257struct dsi_phy_timing_inclk 327struct dsi_phy_timing_inclk {
258{
259 unsigned t_hsdexit; 328 unsigned t_hsdexit;
260 unsigned t_hstrail; 329 unsigned t_hstrail;
261 unsigned t_hsprepr; 330 unsigned t_hsprepare;
262 unsigned t_datzero; 331 unsigned t_datzero;
263 332
264 unsigned t_clktrail; 333 unsigned t_clktrail;
265 unsigned t_clkpost; 334 unsigned t_clkpost;
266 unsigned t_clkzero; 335 unsigned t_clkzero;
267 unsigned t_tlpx; 336 unsigned t_tlpx;
268 337
269 unsigned t_clkpre; 338 unsigned t_clkpre;
270 unsigned t_clkprepare; 339 unsigned t_clkprepare;
271 unsigned t_wakeup; 340 unsigned t_wakeup;
272 341
273 unsigned t_taget; 342 unsigned t_taget;
274 unsigned t_tasure; 343 unsigned t_tasure;
275 unsigned t_tago; 344 unsigned t_tago;
276
277}; 345};
278 346
279#endif 347#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 07:32:15 -0500