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authorWilliam Pierce <wpierce@nvidia.com>2017-05-18 12:21:00 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-26 21:56:24 -0400
commit0f813559ccfa121072784e3914aa4d32023851e6 (patch)
tree3012b509cfb60c9053755ee6d2e7d37c8f28ddb6 /drivers/video/tegra
parent2f37ad6e7494533881795cd7ad17384221c90f64 (diff)
dc: linsim removal
Removed tegra_platform_is_linsim if statements and related #define because of linsim deprecation. Bug 1903831 Change-Id: Iad07394e8f1459ab524c2098d25c52fc710221b6 Signed-off-by: William Pierce <wpierce@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1523449 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/video/tegra')
-rw-r--r--drivers/video/tegra/dc/dc.c20
-rw-r--r--drivers/video/tegra/dc/dp.c11
-rw-r--r--drivers/video/tegra/dc/dsi_padctrl.c2
-rw-r--r--drivers/video/tegra/dc/edid.c2
-rw-r--r--drivers/video/tegra/dc/hdmi2.0.c3
-rw-r--r--drivers/video/tegra/dc/null_or.c2
-rw-r--r--drivers/video/tegra/dc/sor.c23
-rw-r--r--drivers/video/tegra/dc/window.c18
8 files changed, 27 insertions, 54 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 7718b144e..25ab63fad 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -2816,7 +2816,7 @@ unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
2816 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms); 2816 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
2817 u32 reg_val = 0; 2817 u32 reg_val = 0;
2818 2818
2819 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 2819 if (tegra_platform_is_vdk())
2820 return 0; 2820 return 0;
2821 2821
2822 do { 2822 do {
@@ -3799,7 +3799,7 @@ bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask)
3799{ 3799{
3800 u32 val; 3800 u32 val;
3801 3801
3802 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 3802 if (tegra_platform_is_vdk())
3803 return false; 3803 return false;
3804 3804
3805 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 3805 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
@@ -5502,11 +5502,8 @@ void tegra_dc_blank_wins(struct tegra_dc *dc, unsigned windows)
5502 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED; 5502 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
5503 } 5503 }
5504 5504
5505 /* Skip update for linsim */ 5505 tegra_dc_update_windows(dcwins, nr_win, NULL, true, false);
5506 if (!tegra_platform_is_linsim()) { 5506 tegra_dc_sync_windows(dcwins, nr_win);
5507 tegra_dc_update_windows(dcwins, nr_win, NULL, true, false);
5508 tegra_dc_sync_windows(dcwins, nr_win);
5509 }
5510 5507
5511 tegra_dc_program_bandwidth(dc, true); 5508 tegra_dc_program_bandwidth(dc, true);
5512 5509
@@ -5866,13 +5863,6 @@ static int tegra_dc_probe(struct platform_device *ndev)
5866 struct resource of_fb_res; 5863 struct resource of_fb_res;
5867 int hotplug_init_status = -1; 5864 int hotplug_init_status = -1;
5868 5865
5869#ifdef CONFIG_ARCH_TEGRA_210_SOC
5870 if (tegra_platform_is_linsim()) {
5871 dev_info(&ndev->dev, "DC instances are not present on linsim\n");
5872 return -ENODEV;
5873 }
5874#endif
5875
5876 /* Specify parameters for the maximum physical segment size. */ 5866 /* Specify parameters for the maximum physical segment size. */
5877 ndev->dev.dma_parms = &tegra_dc_dma_parameters; 5867 ndev->dev.dma_parms = &tegra_dc_dma_parameters;
5878 5868
@@ -6245,7 +6235,7 @@ static int tegra_dc_probe(struct platform_device *ndev)
6245 6235
6246 if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) { 6236 if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
6247 /* WAR: BL is putting DC in bad state for EDP configuration */ 6237 /* WAR: BL is putting DC in bad state for EDP configuration */
6248 if (!(tegra_platform_is_linsim() || tegra_platform_is_vdk()) && 6238 if (!tegra_platform_is_vdk() &&
6249 (dc->out->type == TEGRA_DC_OUT_DP || 6239 (dc->out->type == TEGRA_DC_OUT_DP ||
6250 dc->out->type == TEGRA_DC_OUT_NVSR_DP)) { 6240 dc->out->type == TEGRA_DC_OUT_NVSR_DP)) {
6251 tegra_disp_clk_prepare_enable(dc->clk); 6241 tegra_disp_clk_prepare_enable(dc->clk);
diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index 83322de3d..94bf74c83 100644
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -105,7 +105,6 @@ static inline void tegra_dp_disable_irq(u32 irq)
105 105
106#define is_hotplug_supported(dp) \ 106#define is_hotplug_supported(dp) \
107({ \ 107({ \
108 !tegra_platform_is_linsim() && \
109 tegra_dc_is_ext_dp_panel(dp->dc); \ 108 tegra_dc_is_ext_dp_panel(dp->dc); \
110}) 109})
111 110
@@ -133,7 +132,7 @@ tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
133 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms); 132 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
134 u32 reg_val = 0; 133 u32 reg_val = 0;
135 134
136 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 135 if (tegra_platform_is_vdk())
137 return 0; 136 return 0;
138 137
139 do { 138 do {
@@ -2611,7 +2610,7 @@ static void tegra_dp_hpd_op_edid_recheck(void *drv_data)
2611 2610
2612static inline void tegra_dp_reset(struct tegra_dc_dp_data *dp) 2611static inline void tegra_dp_reset(struct tegra_dc_dp_data *dp)
2613{ 2612{
2614 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 2613 if (tegra_platform_is_vdk())
2615 return; 2614 return;
2616 2615
2617 if (!dp || !dp->dpaux) 2616 if (!dp || !dp->dpaux)
@@ -3162,9 +3161,7 @@ static bool tegra_dc_dp_hpd_state(struct tegra_dc *dc)
3162 if (WARN_ON(!dc || !dc->out)) 3161 if (WARN_ON(!dc || !dc->out))
3163 return false; 3162 return false;
3164 3163
3165 if (dc->out->type == TEGRA_DC_OUT_FAKE_DP || 3164 if (dc->out->type == TEGRA_DC_OUT_FAKE_DP || tegra_platform_is_vdk())
3166 tegra_platform_is_linsim() ||
3167 tegra_platform_is_vdk())
3168 return true; 3165 return true;
3169 3166
3170 tegra_dpaux_clk_en(dpaux); 3167 tegra_dpaux_clk_en(dpaux);
@@ -3251,7 +3248,7 @@ static void tegra_dc_dp_modeset_notifier(struct tegra_dc *dc)
3251 tegra_dc_sor_modeset_notifier(dp->sor, false); 3248 tegra_dc_sor_modeset_notifier(dp->sor, false);
3252 /* Pixel clock may be changed in new mode, 3249 /* Pixel clock may be changed in new mode,
3253 * recalculate link config */ 3250 * recalculate link config */
3254 if (!(tegra_platform_is_linsim() || tegra_platform_is_vdk())) 3251 if (!(tegra_platform_is_vdk()))
3255 tegra_dc_dp_calc_config(dp, dp->mode, &dp->link_cfg); 3252 tegra_dc_dp_calc_config(dp, dp->mode, &dp->link_cfg);
3256 3253
3257 3254
diff --git a/drivers/video/tegra/dc/dsi_padctrl.c b/drivers/video/tegra/dc/dsi_padctrl.c
index fc25d11a8..ef72b85c9 100644
--- a/drivers/video/tegra/dc/dsi_padctrl.c
+++ b/drivers/video/tegra/dc/dsi_padctrl.c
@@ -220,7 +220,7 @@ struct tegra_dsi_padctrl *tegra_dsi_padctrl_init(struct tegra_dc *dc)
220 int err; 220 int err;
221 221
222 /* Padctrl module doesn't exist on fpga */ 222 /* Padctrl module doesn't exist on fpga */
223 if (tegra_platform_is_linsim() || tegra_platform_is_fpga()) 223 if (tegra_platform_is_fpga())
224 return NULL; 224 return NULL;
225 225
226 dsi = tegra_dc_get_outdata(dc); 226 dsi = tegra_dc_get_outdata(dc);
diff --git a/drivers/video/tegra/dc/edid.c b/drivers/video/tegra/dc/edid.c
index c28260809..748da1a6d 100644
--- a/drivers/video/tegra/dc/edid.c
+++ b/drivers/video/tegra/dc/edid.c
@@ -625,7 +625,7 @@ u16 tegra_edid_get_max_clk_rate(struct tegra_edid *edid)
625 625
626bool tegra_edid_is_scdc_present(struct tegra_edid *edid) 626bool tegra_edid_is_scdc_present(struct tegra_edid *edid)
627{ 627{
628 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 628 if (tegra_platform_is_vdk())
629 return false; 629 return false;
630 630
631 if (!edid || !edid->data) { 631 if (!edid || !edid->data) {
diff --git a/drivers/video/tegra/dc/hdmi2.0.c b/drivers/video/tegra/dc/hdmi2.0.c
index fca376563..823e1c9ff 100644
--- a/drivers/video/tegra/dc/hdmi2.0.c
+++ b/drivers/video/tegra/dc/hdmi2.0.c
@@ -2660,9 +2660,6 @@ static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
2660 if (clk_type == hdmi->clk_type) 2660 if (clk_type == hdmi->clk_type)
2661 return; 2661 return;
2662 2662
2663 if (tegra_platform_is_linsim())
2664 return;
2665
2666 if (clk_type == TEGRA_HDMI_BRICK_CLK) { 2663 if (clk_type == TEGRA_HDMI_BRICK_CLK) {
2667 u32 val; 2664 u32 val;
2668 struct tegra_dc_sor_data *sor = hdmi->sor; 2665 struct tegra_dc_sor_data *sor = hdmi->sor;
diff --git a/drivers/video/tegra/dc/null_or.c b/drivers/video/tegra/dc/null_or.c
index 73659e4b2..7887bd95a 100644
--- a/drivers/video/tegra/dc/null_or.c
+++ b/drivers/video/tegra/dc/null_or.c
@@ -245,7 +245,7 @@ static long tegra_dc_null_setup_clk(struct tegra_dc *dc, struct clk *clk)
245 struct clk *base_clk; 245 struct clk *base_clk;
246 long rate; 246 long rate;
247 247
248 if ((clk == NULL) || (parent_clk == NULL) || tegra_platform_is_linsim()) 248 if ((clk == NULL) || (parent_clk == NULL))
249 return 0; 249 return 0;
250 250
251 if (dc->out != NULL) 251 if (dc->out != NULL)
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index 980630d1a..9633b9db9 100644
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -51,7 +51,7 @@ tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
51 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms); 51 unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
52 u32 reg_val = 0; 52 u32 reg_val = 0;
53 53
54 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 54 if (tegra_platform_is_vdk())
55 return 0; 55 return 0;
56 56
57 do { 57 do {
@@ -323,7 +323,7 @@ static int dbg_sor_show(struct seq_file *s, void *unused)
323 DUMP_REG(nv_sor_dp_misc1_override()); 323 DUMP_REG(nv_sor_dp_misc1_override());
324 DUMP_REG(nv_sor_dp_misc1_bit6()); 324 DUMP_REG(nv_sor_dp_misc1_bit6());
325 325
326 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 326 if (tegra_platform_is_vdk())
327 DUMP_REG(NV_SOR_FPGA_HDMI_HEAD_SEL); 327 DUMP_REG(NV_SOR_FPGA_HDMI_HEAD_SEL);
328 hdmi_dump = 1; /* SOR and SOR1 have same registers */ 328 hdmi_dump = 1; /* SOR and SOR1 have same registers */
329#else 329#else
@@ -501,8 +501,7 @@ static void tegra_sor_fpga_settings(struct tegra_dc *dc,
501 NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_OUT_EN_ENABLE; 501 NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_OUT_EN_ENABLE;
502 502
503 /* continue for system fpga and HDMI */ 503 /* continue for system fpga and HDMI */
504 if ((!(tegra_platform_is_linsim() || tegra_platform_is_vdk())) || 504 if ((!tegra_platform_is_vdk()) || (dc->out->type != TEGRA_DC_OUT_HDMI))
505 (dc->out->type != TEGRA_DC_OUT_HDMI))
506 return; 505 return;
507 506
508 if (dc->ndev->id == 0) {/* HEAD 0 */ 507 if (dc->ndev->id == 0) {/* HEAD 0 */
@@ -1043,7 +1042,7 @@ static inline void tegra_dc_sor_update(struct tegra_dc_sor_data *sor)
1043 1042
1044static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, bool up) 1043static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, bool up)
1045{ 1044{
1046 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 1045 if (tegra_platform_is_vdk())
1047 return; 1046 return;
1048 1047
1049 if (sor->io_padctrl) { 1048 if (sor->io_padctrl) {
@@ -1408,7 +1407,7 @@ static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
1408 1407
1409 reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 1408 reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1410 1409
1411 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 1410 if (tegra_platform_is_vdk())
1412 tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, 1411 tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY,
1413 DC_CMD_STATE_ACCESS); 1412 DC_CMD_STATE_ACCESS);
1414 else 1413 else
@@ -1638,7 +1637,7 @@ void tegra_sor_start_dc(struct tegra_dc_sor_data *sor)
1638 tegra_dc_get(dc); 1637 tegra_dc_get(dc);
1639 reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 1638 reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1640 1639
1641 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 1640 if (tegra_platform_is_vdk())
1642 tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, 1641 tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY,
1643 DC_CMD_STATE_ACCESS); 1642 DC_CMD_STATE_ACCESS);
1644 else 1643 else
@@ -1664,7 +1663,7 @@ void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
1664 1663
1665 reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 1664 reg_val = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1666 1665
1667 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 1666 if (tegra_platform_is_vdk())
1668 tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY, 1667 tegra_dc_writel(dc, reg_val | WRITE_MUX_ASSEMBLY,
1669 DC_CMD_STATE_ACCESS); 1668 DC_CMD_STATE_ACCESS);
1670 else 1669 else
@@ -1739,7 +1738,7 @@ tegra_dc_sor_disable_win_short_raster(struct tegra_dc *dc, int *dc_reg_ctx)
1739{ 1738{
1740 int selected_windows, i; 1739 int selected_windows, i;
1741 1740
1742 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 1741 if (tegra_platform_is_vdk())
1743 return; 1742 return;
1744 1743
1745 selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER); 1744 selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
@@ -1788,7 +1787,7 @@ tegra_dc_sor_restore_win_and_raster(struct tegra_dc *dc, int *dc_reg_ctx)
1788{ 1787{
1789 int selected_windows, i; 1788 int selected_windows, i;
1790 1789
1791 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 1790 if (tegra_platform_is_vdk())
1792 return; 1791 return;
1793 1792
1794 selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER); 1793 selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
@@ -2065,7 +2064,7 @@ void tegra_dc_sor_disable(struct tegra_dc_sor_data *sor, bool is_lvds)
2065 return; 2064 return;
2066 } 2065 }
2067 2066
2068 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 2067 if (tegra_platform_is_vdk())
2069 return; 2068 return;
2070 2069
2071 /* Reset SOR */ 2070 /* Reset SOR */
@@ -2182,7 +2181,7 @@ void tegra_sor_setup_clk(struct tegra_dc_sor_data *sor, struct clk *clk,
2182 struct clk *dc_parent_clk; 2181 struct clk *dc_parent_clk;
2183 struct tegra_dc *dc = sor->dc; 2182 struct tegra_dc *dc = sor->dc;
2184 2183
2185 if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) 2184 if (tegra_platform_is_vdk())
2186 return; 2185 return;
2187 2186
2188 if (clk == dc->clk) { 2187 if (clk == dc->clk) {
diff --git a/drivers/video/tegra/dc/window.c b/drivers/video/tegra/dc/window.c
index db79d8a38..47c12a2ce 100644
--- a/drivers/video/tegra/dc/window.c
+++ b/drivers/video/tegra/dc/window.c
@@ -1152,21 +1152,11 @@ void tegra_dc_trigger_windows(struct tegra_dc *dc)
1152 tegra_dc_get_numof_dispwindows()) { 1152 tegra_dc_get_numof_dispwindows()) {
1153 struct tegra_dc_win *win = tegra_dc_get_window(dc, i); 1153 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
1154 1154
1155 if (tegra_platform_is_linsim()) { 1155 if (!(val & (WIN_A_ACT_REQ << i)) && interlace_done) {
1156 /* FIXME: this is not needed when 1156 win->dirty = 0;
1157 the simulator clears WIN_x_UPDATE 1157 completed = 1;
1158 bits as in HW */
1159 if (interlace_done) {
1160 win->dirty = 0;
1161 completed = 1;
1162 }
1163 } else { 1158 } else {
1164 if (!(val & (WIN_A_ACT_REQ << i)) && interlace_done) { 1159 dirty = 1;
1165 win->dirty = 0;
1166 completed = 1;
1167 } else {
1168 dirty = 1;
1169 }
1170 } 1160 }
1171 } 1161 }
1172 1162