video: tegra: dsi: Fix slow slew rate

Programmed the recommended register sequence to improve signal swing

Bug 1393348

Change-Id: Ic851ddbdf6ce52c5d378420ecda698334ae2e947
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/304629
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 37d9f8caf..6edcb554b 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -2074,11 +2074,23 @@ static void tegra_dsi_mipi_calibration_12x(struct tegra_dc_dsi_data *dsi)
         clk_prepare_enable(clk72mhz);
 
         /* Calibration settings begin */
+        val = tegra_mipi_cal_read(dsi->mipi_cal,
+                        MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
+        val &= ~PAD_DRIV_UP_REF(0x7);
+        val |= PAD_DRIV_UP_REF(0x3);
+        tegra_mipi_cal_write(dsi->mipi_cal, val,
+                        MIPI_CAL_MIPI_BIAS_PAD_CFG1_0);
+
         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
                 DSI_PAD_OUTADJCLK(0x0));
         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
 
+        val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
+        val |= (DSI_PAD_PREEMP_PU_CLK(0x3) |
+                   DSI_PAD_PREEMP_PD(0x3) | DSI_PAD_PREEMP_PU(0x3));
+        tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
+
         /* Calibrate DSI 0 */
         if (dsi->info.ganged_type ||
                 dsi->info.dsi_instance == DSI_INSTANCE_0) {