video: tegra: dsi: Dont program initialized panels

Do not program some panels that the bootloader has already initialized.
This avoids periods of blanking during boot.

Bug 1219004

Change-Id: Ie08b20a0892d62dc1b960d37f709eda933e886cc
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/197685
(cherry picked from commit 1d3bfb96cb6e6b09609cca842bb4cc5c90ee33c3)
Reviewed-on: http://git-master/r/204247
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

1 files changed, 57 insertions, 7 deletions

diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 5a797f87d..5f8418aa7 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -3249,6 +3249,43 @@ static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
         }
 }
 
+static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
+{
+        regulator_enable(dsi->avdd_dsi_csi);
+
+        dsi->status.init = DSI_MODULE_INIT;
+        dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
+        dsi->status.driven = DSI_DRIVEN_MODE_DC;
+        dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
+        dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
+        dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
+        dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
+
+        if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
+                dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
+        else
+                dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
+
+        if (!(dsi->info.ganged_type)) {
+                if (dsi->info.video_burst_mode ==
+                        TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
+                        dsi->info.video_burst_mode ==
+                        TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
+                        dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
+                else
+                        dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
+        }
+
+        if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
+                dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
+        else
+                dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
+
+        tegra_dsi_clk_enable(dsi);
+
+        dsi->enabled = true;
+}
+
 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
 {
         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
@@ -3257,6 +3294,15 @@ static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
         mutex_lock(&dsi->lock);
         tegra_dc_io_start(dc);
 
+        /*
+         * Do not program this panel as the bootloader as has already
+         * initialized it. This avoids periods of blanking during boot.
+         */
+        if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
+                tegra_dsi_setup_initialized_panel(dsi);
+                goto fail;
+        }
+
         /* Stop DC stream before configuring DSI registers
          * to avoid visible glitches on panel during transition
          * from bootloader to kernel driver
@@ -4187,6 +4233,16 @@ static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
         struct clk *parent_clk;
         struct clk *base_clk;
 
+        /* divide by 1000 to avoid overflow */
+        dc->mode.pclk /= 1000;
+        rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
+                                / dc->shift_clk_div.div;
+        rate *= 1000;
+        dc->mode.pclk *= 1000;
+
+        if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
+                goto skip_setup;
+
         if (clk == dc->clk) {
                 parent_clk = clk_get_sys(NULL,
                                 dc->out->parent_clk ? : "pll_d_out0");
@@ -4209,19 +4265,13 @@ static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
                 }
         }
 
-        /* divide by 1000 to avoid overflow */
-        dc->mode.pclk /= 1000;
-        rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
-                                / dc->shift_clk_div.div;
-        rate *= 1000;
-        dc->mode.pclk *= 1000;
-
         if (rate != clk_get_rate(base_clk))
                 clk_set_rate(base_clk, rate);
 
         if (clk_get_parent(clk) != parent_clk)
                 clk_set_parent(clk, parent_clk);
 
+skip_setup:
         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
 }