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authorJuha Tukkinen <jtukkinen@nvidia.com>2014-03-05 03:35:49 -0500
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:08:21 -0400
commit729088bb8163214cf8386df9658ee80ba690e364 (patch)
treeeab97f2d6b1c1cd9e6d77fd872f93331920fd283 /drivers/video/tegra/dc/dsi.c
parent5399fa26209192dad5c0ababd005ef3a1e891814 (diff)
Revert "video: tegra: dsi: Enable VBLANK DCS via init api"
Breaks boot of bowmore_ers. This reverts commit 74b455e813f3bff2b4921170e04b718f939069f8. Change-Id: Ia69637b302f2f6fb900f29a44ff64ce3bc89118a Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-on: http://git-master/r/377686 Reviewed-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dsi.c')
-rw-r--r--drivers/video/tegra/dc/dsi.c121
1 files changed, 45 insertions, 76 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 786da1823..0354f84af 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -313,17 +313,6 @@ const u32 init_reg_vs1_ext[] = {
313 DSI_GANGED_MODE_SIZE, 313 DSI_GANGED_MODE_SIZE,
314}; 314};
315 315
316static int tegra_dsi_start_host_cmd_v_blank_video(
317 struct tegra_dc_dsi_data *dsi,
318 struct tegra_dsi_cmd *cmd);
319static void tegra_dsi_stop_host_cmd_v_blank_video(
320 struct tegra_dc_dsi_data *dsi);
321static int tegra_dsi_start_host_cmd_v_blank_dcs(
322 struct tegra_dc_dsi_data *dsi,
323 struct tegra_dsi_cmd *cmd);
324static void tegra_dsi_stop_host_cmd_v_blank_dcs(
325 struct tegra_dc_dsi_data *dsi);
326
327static int tegra_dsi_host_suspend(struct tegra_dc *dc); 316static int tegra_dsi_host_suspend(struct tegra_dc *dc);
328static int tegra_dsi_host_resume(struct tegra_dc *dc); 317static int tegra_dsi_host_resume(struct tegra_dc *dc);
329static void tegra_dc_dsi_idle_work(struct work_struct *work); 318static void tegra_dc_dsi_idle_work(struct work_struct *work);
@@ -2968,7 +2957,7 @@ static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2968 } 2957 }
2969 } 2958 }
2970 2959
2971 if (cmd->cmd_type != TEGRA_DSI_PACKET_VBLANK_CMD) { 2960 if (cmd->cmd_type != TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
2972 err = tegra_dsi_host_trigger(dsi, cmd->link_id); 2961 err = tegra_dsi_host_trigger(dsi, cmd->link_id);
2973 if (err < 0) 2962 if (err < 0)
2974 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n"); 2963 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
@@ -3053,97 +3042,57 @@ int tegra_dsi_write_data(struct tegra_dc *dc,
3053 3042
3054EXPORT_SYMBOL(tegra_dsi_write_data); 3043EXPORT_SYMBOL(tegra_dsi_write_data);
3055 3044
3056int tegra_dsi_start_host_cmd_v_blank(struct tegra_dc_dsi_data *dsi, 3045int tegra_dsi_start_host_cmd_v_blank_video(struct tegra_dc_dsi_data *dsi,
3057 struct tegra_dsi_cmd *cmd) 3046 struct tegra_dsi_cmd *cmd)
3058{ 3047{
3059 struct tegra_dc *dc = dsi->dc; 3048 struct tegra_dc *dc = dsi->dc;
3060 int err = 0; 3049 int err = 0;
3050 u32 val;
3061 3051
3062 if (!dsi->enabled) { 3052 if (!dsi->enabled) {
3063 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n"); 3053 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3064 return -EINVAL; 3054 return -EINVAL;
3065 } 3055 }
3066 3056
3067 if (cmd->cmd_type != TEGRA_DSI_PACKET_VBLANK_CMD) {
3068 dev_err(&dc->ndev->dev, "Invalid VBLANK command\n");
3069 return -EINVAL;
3070 }
3071
3072 mutex_lock(&dsi->lock);
3073 tegra_dc_io_start(dc); 3057 tegra_dc_io_start(dc);
3074 tegra_dc_dsi_hold_host(dc); 3058 tegra_dc_dsi_hold_host(dc);
3075 3059 val = (DSI_CMD_PKT_VID_ENABLE(1) | DSI_LINE_TYPE(4));
3076 if (dsi->info.video_data_type == 3060 tegra_dsi_writel(dsi, val, DSI_VID_MODE_CONTROL);
3077 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) 3061 _tegra_dsi_write_data(dsi, cmd);
3078 tegra_dsi_start_host_cmd_v_blank_video(dsi, cmd);
3079 else
3080 tegra_dsi_start_host_cmd_v_blank_dcs(dsi, cmd);
3081
3082 if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) { 3062 if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3083 err = tegra_dsi_set_to_hs_mode(dc, dsi, 3063 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3084 TEGRA_DSI_DRIVEN_BY_DC); 3064 TEGRA_DSI_DRIVEN_BY_DC);
3085 if (err < 0) { 3065 if (err < 0) {
3086 dev_err(&dc->ndev->dev, 3066 dev_err(&dc->ndev->dev,
3087 "dsi: not able to set to hs mode: %d\n", err); 3067 "dsi: not able to set to hs mode\n");
3088 goto fail; 3068 goto fail;
3089 } 3069 }
3090 } 3070 }
3091 3071 tegra_dsi_start_dc_stream(dc, dsi);
3092 if (dsi->status.dc_stream == DSI_DC_STREAM_DISABLE)
3093 tegra_dsi_start_dc_stream(dc, dsi);
3094 tegra_dsi_wait_frame_end(dc, dsi, 2); 3072 tegra_dsi_wait_frame_end(dc, dsi, 2);
3095 3073 fail:
3096fail:
3097 tegra_dc_dsi_release_host(dc); 3074 tegra_dc_dsi_release_host(dc);
3098 tegra_dc_io_end(dc); 3075 tegra_dc_io_end(dc);
3099 mutex_unlock(&dsi->lock); 3076
3100 return err; 3077 return err;
3101} 3078}
3102EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank); 3079EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_video);
3103 3080
3104int tegra_dsi_stop_host_cmd_v_blank(struct tegra_dc_dsi_data *dsi) 3081int tegra_dsi_end_host_cmd_v_blank_video(struct tegra_dc *dc,
3082 struct tegra_dc_dsi_data *dsi)
3105{ 3083{
3106 struct tegra_dc *dc = dsi->dc;
3107
3108 if (!dsi->enabled) { 3084 if (!dsi->enabled) {
3109 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n"); 3085 dev_err(&dsi->dc->ndev->dev, "DSI controller suspended\n");
3110 return -EINVAL; 3086 return -EINVAL;
3111 } 3087 }
3112 3088
3113 mutex_lock(&dsi->lock);
3114 tegra_dc_io_start(dc); 3089 tegra_dc_io_start(dc);
3115 tegra_dc_dsi_hold_host(dc); 3090 tegra_dsi_writel(dsi, 0, DSI_VID_MODE_CONTROL);
3116
3117 if (dsi->info.video_data_type ==
3118 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE)
3119 tegra_dsi_stop_host_cmd_v_blank_video(dsi);
3120 else
3121 tegra_dsi_stop_host_cmd_v_blank_dcs(dsi);
3122
3123 tegra_dc_dsi_release_host(dc);
3124 tegra_dc_io_end(dc); 3091 tegra_dc_io_end(dc);
3125 mutex_unlock(&dsi->lock);
3126 return 0;
3127}
3128EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank);
3129 3092
3130static int tegra_dsi_start_host_cmd_v_blank_video(
3131 struct tegra_dc_dsi_data *dsi,
3132 struct tegra_dsi_cmd *cmd)
3133{
3134 u32 val;
3135
3136 val = (DSI_CMD_PKT_VID_ENABLE(1) | DSI_LINE_TYPE(4));
3137 tegra_dsi_writel(dsi, val, DSI_VID_MODE_CONTROL);
3138 _tegra_dsi_write_data(dsi, cmd);
3139 return 0; 3093 return 0;
3140} 3094}
3141 3095EXPORT_SYMBOL(tegra_dsi_end_host_cmd_v_blank_video);
3142static void tegra_dsi_stop_host_cmd_v_blank_video(
3143 struct tegra_dc_dsi_data *dsi)
3144{
3145 tegra_dsi_writel(dsi, 0, DSI_VID_MODE_CONTROL);
3146}
3147 3096
3148static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc, 3097static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3149 struct tegra_dc_dsi_data *dsi, 3098 struct tegra_dc_dsi_data *dsi,
@@ -3173,9 +3122,9 @@ static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3173 dsi, 3122 dsi,
3174 cur_cmd->sp_len_dly.frame_cnt); 3123 cur_cmd->sp_len_dly.frame_cnt);
3175 } else if (cur_cmd->cmd_type == 3124 } else if (cur_cmd->cmd_type ==
3176 TEGRA_DSI_PACKET_VBLANK_CMD) { 3125 TEGRA_DSI_PACKET_VIDEO_VBLANK_CMD) {
3177 tegra_dsi_start_host_cmd_v_blank(dsi, cur_cmd); 3126 tegra_dsi_start_host_cmd_v_blank_video(dsi, cur_cmd);
3178 tegra_dsi_stop_host_cmd_v_blank(dsi); 3127 tegra_dsi_end_host_cmd_v_blank_video(dc, dsi);
3179 } else { 3128 } else {
3180 delay_ms = DEFAULT_DELAY_MS; 3129 delay_ms = DEFAULT_DELAY_MS;
3181 if ((i + 1 < n_cmd) && 3130 if ((i + 1 < n_cmd) &&
@@ -3292,9 +3241,8 @@ static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
3292 return 0; 3241 return 0;
3293} 3242}
3294 3243
3295static int tegra_dsi_start_host_cmd_v_blank_dcs( 3244int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi,
3296 struct tegra_dc_dsi_data *dsi, 3245 struct tegra_dsi_cmd *cmd)
3297 struct tegra_dsi_cmd *cmd)
3298{ 3246{
3299#define PKT_HEADER_LEN_BYTE 4 3247#define PKT_HEADER_LEN_BYTE 4
3300#define CHECKSUM_LEN_BYTE 2 3248#define CHECKSUM_LEN_BYTE 2
@@ -3302,6 +3250,14 @@ static int tegra_dsi_start_host_cmd_v_blank_dcs(
3302 int err = 0; 3250 int err = 0;
3303 u32 val; 3251 u32 val;
3304 u16 tot_pkt_len = PKT_HEADER_LEN_BYTE; 3252 u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
3253 struct tegra_dc *dc = dsi->dc;
3254
3255 if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
3256 return -EINVAL;
3257
3258 mutex_lock(&dsi->lock);
3259 tegra_dc_io_start(dc);
3260 tegra_dc_dsi_hold_host(dc);
3305 3261
3306#if DSI_USE_SYNC_POINTS 3262#if DSI_USE_SYNC_POINTS
3307 atomic_set(&dsi_syncpt_rst, 1); 3263 atomic_set(&dsi_syncpt_rst, 1);
@@ -3310,7 +3266,7 @@ static int tegra_dsi_start_host_cmd_v_blank_dcs(
3310 err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd); 3266 err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
3311 if (err < 0) { 3267 if (err < 0) {
3312 dev_err(&dsi->dc->ndev->dev, 3268 dev_err(&dsi->dc->ndev->dev,
3313 "dsi: dcs pkt seq ctrl init failed: %d\n", err); 3269 "dsi: dcs pkt seq ctrl init failed\n");
3314 goto fail; 3270 goto fail;
3315 } 3271 }
3316 3272
@@ -3325,20 +3281,28 @@ static int tegra_dsi_start_host_cmd_v_blank_dcs(
3325 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL); 3281 tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
3326 3282
3327fail: 3283fail:
3284 tegra_dc_dsi_release_host(dc);
3285 tegra_dc_io_end(dc);
3286 mutex_unlock(&dsi->lock);
3328 return err; 3287 return err;
3329 3288
3330#undef PKT_HEADER_LEN_BYTE 3289#undef PKT_HEADER_LEN_BYTE
3331#undef CHECKSUM_LEN_BYTE 3290#undef CHECKSUM_LEN_BYTE
3332} 3291}
3292EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
3333 3293
3334static void tegra_dsi_stop_host_cmd_v_blank_dcs( 3294void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data *dsi)
3335 struct tegra_dc_dsi_data *dsi)
3336{ 3295{
3296 struct tegra_dc *dc = dsi->dc;
3337 u32 cnt; 3297 u32 cnt;
3338 3298
3299 mutex_lock(&dsi->lock);
3300 tegra_dc_io_start(dc);
3301 tegra_dc_dsi_hold_host(dc);
3302
3339 if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS) 3303 if (!tegra_cpu_is_asim() && DSI_USE_SYNC_POINTS)
3340 if (atomic_read(&dsi_syncpt_rst)) { 3304 if (atomic_read(&dsi_syncpt_rst)) {
3341 tegra_dsi_wait_frame_end(dsi->dc, dsi, 2); 3305 tegra_dsi_wait_frame_end(dc, dsi, 2);
3342 tegra_dsi_syncpt_reset(dsi); 3306 tegra_dsi_syncpt_reset(dsi);
3343 atomic_set(&dsi_syncpt_rst, 0); 3307 atomic_set(&dsi_syncpt_rst, 0);
3344 } 3308 }
@@ -3349,7 +3313,12 @@ static void tegra_dsi_stop_host_cmd_v_blank_dcs(
3349 for (cnt = 0; cnt < 8; cnt++) 3313 for (cnt = 0; cnt < 8; cnt++)
3350 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt); 3314 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
3351 3315
3316 tegra_dc_dsi_release_host(dc);
3317 tegra_dc_io_end(dc);
3318
3319 mutex_unlock(&dsi->lock);
3352} 3320}
3321EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
3353 3322
3354static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi) 3323static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
3355{ 3324{