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authorDaniel Solomon <daniels@nvidia.com>2014-08-05 17:48:42 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:10:50 -0400
commit6277e4d884c690fd848dbc51e0afe6ded5880b4b (patch)
treeb705a6b596ab1940e530db403927b0ae0a1cf895 /drivers/video/tegra/dc/dsi.c
parent9f9ec181aa6d618ba84dcb1b936c950df7cbae8e (diff)
video: tegra: dc: Fix and refactor FRAME_END_INT
- Fix a conflict with other DC interrupt masks when the DSI driver waits on FRAME_END_INT - Move generic FRAME_END_INT mask/unmask and wait-for functions to dc.c Bug 1534724 Change-Id: I40e26ada2f0494782979e32c1a22906361b214b5 Signed-off-by: Daniel Solomon <daniels@nvidia.com> Reviewed-on: http://git-master/r/451186 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dsi.c')
-rw-r--r--drivers/video/tegra/dc/dsi.c19
1 files changed, 2 insertions, 17 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 4967d08d8..8fd4539b0 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -1728,7 +1728,6 @@ static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1728 struct tegra_dc_dsi_data *dsi, 1728 struct tegra_dc_dsi_data *dsi,
1729 u32 timeout_n_frames) 1729 u32 timeout_n_frames)
1730{ 1730{
1731 int val;
1732 long timeout; 1731 long timeout;
1733 u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate); 1732 u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1734 struct tegra_dc_mode mode = dc->mode; 1733 struct tegra_dc_mode mode = dc->mode;
@@ -1741,26 +1740,12 @@ static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1741 dev_WARN(&dc->ndev->dev, 1740 dev_WARN(&dc->ndev->dev,
1742 "dsi: to stop at next frame give at least 2 frame delay\n"); 1741 "dsi: to stop at next frame give at least 2 frame delay\n");
1743 1742
1744 reinit_completion(&dc->frame_end_complete); 1743 timeout = tegra_dc_wait_for_frame_end(dc, timeout_n_frames *
1745 1744 frame_period);
1746 tegra_dc_get(dc);
1747
1748 tegra_dc_flush_interrupt(dc, FRAME_END_INT);
1749 /* unmask frame end interrupt */
1750 val = tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1751
1752 timeout = wait_for_completion_interruptible_timeout(
1753 &dc->frame_end_complete,
1754 msecs_to_jiffies(timeout_n_frames * frame_period));
1755
1756 /* reinstate interrupt mask */
1757 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1758 1745
1759 /* wait for v_ref_to_sync no. of lines after frame end interrupt */ 1746 /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1760 udelay(mode.v_ref_to_sync * line_period); 1747 udelay(mode.v_ref_to_sync * line_period);
1761 1748
1762 tegra_dc_put(dc);
1763
1764 return timeout; 1749 return timeout;
1765} 1750}
1766 1751