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authorAnimesh Kishore <ankishore@nvidia.com>2013-10-08 10:30:41 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:06:39 -0400
commit50495bb19a08d43fd975df51b6240f99389234a3 (patch)
tree65d36183eae7612f9a17c5fc6796e5dbcaec4059 /drivers/video/tegra/dc/dsi.c
parent7d6650558de42d0af9c53e61a730b7d23015916f (diff)
video: tegra: dsi: Disable TE during OSidle
Bug 1381539 Change-Id: I4758b12f782dc3c669af3937182f77e8e74c4a6a Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/289990 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dsi.c')
-rw-r--r--drivers/video/tegra/dc/dsi.c61
1 files changed, 56 insertions, 5 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 88e135a61..72b52dce4 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -3059,7 +3059,7 @@ static void tegra_dc_dsi_idle_work(struct work_struct *work)
3059 3059
3060static int tegra_dsi_write_data_nosync(struct tegra_dc *dc, 3060static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
3061 struct tegra_dc_dsi_data *dsi, 3061 struct tegra_dc_dsi_data *dsi,
3062 struct tegra_dsi_cmd *cmd) 3062 struct tegra_dsi_cmd *cmd, u8 delay_ms)
3063{ 3063{
3064 int err = 0; 3064 int err = 0;
3065 struct dsi_status *init_status; 3065 struct dsi_status *init_status;
@@ -3073,6 +3073,7 @@ static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
3073 } 3073 }
3074 3074
3075 err = _tegra_dsi_write_data(dsi, cmd); 3075 err = _tegra_dsi_write_data(dsi, cmd);
3076 mdelay(delay_ms);
3076fail: 3077fail:
3077 err = tegra_dsi_restore_state(dc, dsi, init_status); 3078 err = tegra_dsi_restore_state(dc, dsi, init_status);
3078 if (err < 0) 3079 if (err < 0)
@@ -3083,14 +3084,14 @@ fail:
3083 3084
3084int tegra_dsi_write_data(struct tegra_dc *dc, 3085int tegra_dsi_write_data(struct tegra_dc *dc,
3085 struct tegra_dc_dsi_data *dsi, 3086 struct tegra_dc_dsi_data *dsi,
3086 struct tegra_dsi_cmd *cmd) 3087 struct tegra_dsi_cmd *cmd, u8 delay_ms)
3087{ 3088{
3088 int err; 3089 int err;
3089 3090
3090 tegra_dc_io_start(dc); 3091 tegra_dc_io_start(dc);
3091 tegra_dc_dsi_hold_host(dc); 3092 tegra_dc_dsi_hold_host(dc);
3092 3093
3093 err = tegra_dsi_write_data_nosync(dc, dsi, cmd); 3094 err = tegra_dsi_write_data_nosync(dc, dsi, cmd, delay_ms);
3094 3095
3095 tegra_dc_dsi_release_host(dc); 3096 tegra_dc_dsi_release_host(dc);
3096 tegra_dc_io_end(dc); 3097 tegra_dc_io_end(dc);
@@ -3107,6 +3108,7 @@ static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3107{ 3108{
3108 u32 i; 3109 u32 i;
3109 int err; 3110 int err;
3111 u8 delay_ms;
3110 3112
3111 err = 0; 3113 err = 0;
3112 for (i = 0; i < n_cmd; i++) { 3114 for (i = 0; i < n_cmd; i++) {
@@ -3126,8 +3128,15 @@ static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
3126 dsi, 3128 dsi,
3127 cur_cmd->sp_len_dly.frame_cnt); 3129 cur_cmd->sp_len_dly.frame_cnt);
3128 } else { 3130 } else {
3129 err = tegra_dsi_write_data_nosync(dc, dsi, cur_cmd); 3131 /* default delay 1ms after command */
3130 mdelay(1); 3132 delay_ms = 1;
3133 if ((i + 1 < n_cmd) &&
3134 (cmd[i + 1].cmd_type == TEGRA_DSI_DELAY_MS)) {
3135 delay_ms = cmd[i + 1].sp_len_dly.delay_ms;
3136 i++;
3137 }
3138 err = tegra_dsi_write_data_nosync(dc, dsi,
3139 cur_cmd, delay_ms);
3131 if (err < 0) 3140 if (err < 0)
3132 break; 3141 break;
3133 } 3142 }
@@ -4451,6 +4460,32 @@ static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
4451 } 4460 }
4452} 4461}
4453 4462
4463static int tegra_dsi_te_on_off(struct tegra_dc_dsi_data *dsi, bool flag)
4464{
4465 int ret;
4466
4467 struct tegra_dsi_cmd te_enable[] = {
4468 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4469 DSI_DCS_SET_TEARING_EFFECT_ON, 0x0),
4470 DSI_DLY_MS(20),
4471 };
4472
4473 struct tegra_dsi_cmd te_disable[] = {
4474 DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM,
4475 DSI_DCS_SET_TEARING_EFFECT_OFF, 0x0),
4476 DSI_DLY_MS(20),
4477 };
4478
4479 if (flag)
4480 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_enable,
4481 ARRAY_SIZE(te_enable));
4482 else
4483 ret = tegra_dsi_send_panel_cmd(dsi->dc, dsi, te_disable,
4484 ARRAY_SIZE(te_disable));
4485
4486 return ret;
4487}
4488
4454static int _tegra_dsi_host_suspend(struct tegra_dc *dc, 4489static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
4455 struct tegra_dc_dsi_data *dsi, 4490 struct tegra_dc_dsi_data *dsi,
4456 u32 suspend_aggr) 4491 u32 suspend_aggr)
@@ -4630,10 +4665,13 @@ static int tegra_dsi_host_suspend(struct tegra_dc *dc)
4630 cond_resched(); 4665 cond_resched();
4631 4666
4632 tegra_dc_io_start(dc); 4667 tegra_dc_io_start(dc);
4668
4633 dsi->host_suspended = true; 4669 dsi->host_suspended = true;
4634 4670
4635 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2); 4671 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4636 4672
4673 tegra_dsi_te_on_off(dsi, false);
4674
4637 err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr); 4675 err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
4638 if (err < 0) { 4676 if (err < 0) {
4639 dev_err(&dc->ndev->dev, 4677 dev_err(&dc->ndev->dev,
@@ -4652,6 +4690,16 @@ fail:
4652 return err; 4690 return err;
4653} 4691}
4654 4692
4693static bool tegra_dc_dsi_osidle(struct tegra_dc *dc)
4694{
4695 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4696
4697 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4698 return dsi->host_suspended;
4699 else
4700 return false;
4701}
4702
4655static void tegra_dsi_bl_off(struct backlight_device *bd) 4703static void tegra_dsi_bl_off(struct backlight_device *bd)
4656{ 4704{
4657 if (!bd) 4705 if (!bd)
@@ -4761,6 +4809,8 @@ static int tegra_dsi_host_resume(struct tegra_dc *dc)
4761 goto fail; 4809 goto fail;
4762 } 4810 }
4763 4811
4812 tegra_dsi_te_on_off(dsi, true);
4813
4764 tegra_dsi_start_dc_stream(dc, dsi); 4814 tegra_dsi_start_dc_stream(dc, dsi);
4765 dsi->host_suspended = false; 4815 dsi->host_suspended = false;
4766fail: 4816fail:
@@ -4980,4 +5030,5 @@ struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4980 .resume = tegra_dc_dsi_resume, 5030 .resume = tegra_dc_dsi_resume,
4981#endif 5031#endif
4982 .setup_clk = tegra_dc_dsi_setup_clk, 5032 .setup_clk = tegra_dc_dsi_setup_clk,
5033 .osidle = tegra_dc_dsi_osidle,
4983}; 5034};