video: tegra: dsi: turn off pads after calibration

Turn off mipi bias pads after calibration

Bug 200021693

Change-Id: Ia62e2e386fc766b15e1abaee1bacb873a326d1bf
Signed-off-by: Vineel Kumar Reddy Kovvuri <vineelkumarr@nvidia.com>
Reviewed-on: http://git-master/r/438645
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>

1 files changed, 16 insertions, 18 deletions

diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 3c31e3975..866cdf931 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -2514,6 +2514,8 @@ static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
 #endif
 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
 {
+        u32 val = 0;
+
         if (!dsi->ulpm)
                 tegra_dsi_pad_enable(dsi);
         else
@@ -2525,6 +2527,13 @@ static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
 
                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
 
+                /* enable mipi bias pad */
+                val = tegra_mipi_cal_read(dsi->mipi_cal,
+                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
+                val &= ~MIPI_BIAS_PAD_PDVCLAMP(0x1);
+                tegra_mipi_cal_write(dsi->mipi_cal, val,
+                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
+
 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || \
         defined(CONFIG_ARCH_TEGRA_14x_SOC) || \
         defined(CONFIG_ARCH_TEGRA_12x_SOC)
@@ -2548,6 +2557,13 @@ static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
                 tegra_dsi_mipi_calibration_12x(dsi);
 #endif
+                /* disable mipi bias pad */
+                val = tegra_mipi_cal_read(dsi->mipi_cal,
+                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
+                val |= MIPI_BIAS_PAD_PDVCLAMP(0x1);
+                tegra_mipi_cal_write(dsi->mipi_cal, val,
+                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
+
                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
         } else {
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -4615,15 +4631,6 @@ static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
                 val |= DSI_PAD_PDVCLAMP(0x1);
                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_3_VS1);
 
-                /* disable mipi bias pad */
-                tegra_mipi_cal_clk_enable(dsi->mipi_cal);
-                val = tegra_mipi_cal_read(dsi->mipi_cal,
-                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
-                val |= MIPI_BIAS_PAD_PDVCLAMP(0x1);
-                tegra_mipi_cal_write(dsi->mipi_cal, val,
-                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
-                tegra_mipi_cal_clk_disable(dsi->mipi_cal);
-
                 /* fall through */
         case DSI_HOST_SUSPEND_LV1:
                 /* Disable dsi fast and slow clock */
@@ -4666,15 +4673,6 @@ static int _tegra_dsi_host_resume(struct tegra_dc *dc,
                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
                 tegra_dsi_clk_enable(dsi);
 
-                /* enable mipi bias pad */
-                tegra_mipi_cal_clk_enable(dsi->mipi_cal);
-                val = tegra_mipi_cal_read(dsi->mipi_cal,
-                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
-                val &= ~MIPI_BIAS_PAD_PDVCLAMP(0x1);
-                tegra_mipi_cal_write(dsi->mipi_cal, val,
-                                MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
-                tegra_mipi_cal_clk_disable(dsi->mipi_cal);
-
                 /* enable HS logic */
                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_3_VS1);
                 val &= ~DSI_PAD_PDVCLAMP(0x1);