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authorAnimesh Kishore <ankishore@nvidia.com>2015-08-19 05:13:51 -0400
committerAnimesh Kishore <ankishore@nvidia.com>2015-10-08 08:19:00 -0400
commitc29244bdfa3a145340510965826a4ca95892106f (patch)
tree55e17171cfa2cd885214840ef28c19a1b844112d /drivers/video/tegra/dc/dp.c
parent7d74e2ba2f52c5c9af81b9ab268f027f184ad01c (diff)
video: tegra: dp: Fix CTS 700.1.1.2
CTS description: Additional DPCD handling test 2 - Fix corrupted DPCD link capabilities Bug 200103501 Change-Id: I7ebeb055284f73140a5f284bf8dc74da5662dc3d Signed-off-by: Animesh Kishore <ankishore@nvidia.com> Reviewed-on: http://git-master/r/785852 (cherry picked from commit 10228ba705d70ded2d52d95524e173d1bb9198b9) Reviewed-on: http://git-master/r/812198 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dp.c')
-rw-r--r--drivers/video/tegra/dc/dp.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index 03bab4c5c..7ea1dfb2c 100644
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -1543,6 +1543,14 @@ static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
1543 NV_DPCD_MAX_LANE_COUNT, &dpcd_data)); 1543 NV_DPCD_MAX_LANE_COUNT, &dpcd_data));
1544 1544
1545 cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; 1545 cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
1546
1547 if (cfg->max_lane_count >= 4)
1548 cfg->max_lane_count = 4;
1549 else if (cfg->max_lane_count >= 2)
1550 cfg->max_lane_count = 2;
1551 else
1552 cfg->max_lane_count = 1;
1553
1546 if (dp->pdata && dp->pdata->lanes && 1554 if (dp->pdata && dp->pdata->lanes &&
1547 dp->pdata->lanes < cfg->max_lane_count) 1555 dp->pdata->lanes < cfg->max_lane_count)
1548 cfg->max_lane_count = dp->pdata->lanes; 1556 cfg->max_lane_count = dp->pdata->lanes;
@@ -1578,6 +1586,14 @@ static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
1578 CHECK_RET(tegra_dc_dp_dpcd_read(dp, 1586 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
1579 NV_DPCD_MAX_LINK_BANDWIDTH, 1587 NV_DPCD_MAX_LINK_BANDWIDTH,
1580 &cfg->max_link_bw)); 1588 &cfg->max_link_bw));
1589
1590 if (cfg->max_link_bw >= SOR_LINK_SPEED_G5_4)
1591 cfg->max_link_bw = SOR_LINK_SPEED_G5_4;
1592 else if (cfg->max_link_bw >= SOR_LINK_SPEED_G2_7)
1593 cfg->max_link_bw = SOR_LINK_SPEED_G2_7;
1594 else
1595 cfg->max_link_bw = SOR_LINK_SPEED_G1_62;
1596
1581 if (dp->pdata && dp->pdata->link_bw && 1597 if (dp->pdata && dp->pdata->link_bw &&
1582 dp->pdata->link_bw < cfg->max_link_bw) 1598 dp->pdata->link_bw < cfg->max_link_bw)
1583 cfg->max_link_bw = dp->pdata->link_bw; 1599 cfg->max_link_bw = dp->pdata->link_bw;