diff options
author | Santosh Reddy Galma <galmar@nvidia.com> | 2017-08-29 10:23:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-11 14:22:46 -0400 |
commit | c20fb12aebbefd13dd334a2b60b8e43b85e9eb48 (patch) | |
tree | a988bd3c474adcdcc155116a5008e107e056dad9 /drivers/video/tegra/dc/dp.c | |
parent | 41338a0f55d79d3e4958e809ee75707bb3857d70 (diff) |
video: tegra: dc: fix display powerdomains
Change does the following
- enable clocks nvdisplayhub,nvdisplay_disp,nvdisplay_p0,
nvdisplay_p1,nvdisplay_p2,nvdisplay_dsc before enabling
head0 powerdomain before accessing any display register
as WAR to fix issues in kernel due to BL enabling all
display power domains unconditionally.
- unpowergate/powergate DPAUX powerdomain instead
of corresponding head power domain in display drivers
as per display powerdomains in guidelines.
- read powergate id for DPAUX based on compatible field
from dt.
- enable/disable dpaux powerdomain before I2C transfer
using DDC.
- code refactoring and cleanup.
Bug 200292406
Change-Id: I473c5aa74aceed6131dec9da848c588e9e3c490c
Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1547730
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dp.c')
-rw-r--r-- | drivers/video/tegra/dc/dp.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c index b4d7c68af..3699efaee 100644 --- a/drivers/video/tegra/dc/dp.c +++ b/drivers/video/tegra/dc/dp.c | |||
@@ -2089,6 +2089,8 @@ static void _tegra_dpaux_init(struct tegra_dc_dp_data *dp) | |||
2089 | { | 2089 | { |
2090 | if (dp->sor->safe_clk) | 2090 | if (dp->sor->safe_clk) |
2091 | tegra_sor_safe_clk_enable(dp->sor); | 2091 | tegra_sor_safe_clk_enable(dp->sor); |
2092 | |||
2093 | tegra_unpowergate_partition(dp->dpaux->powergate_id); | ||
2092 | tegra_dpaux_clk_en(dp->dpaux); | 2094 | tegra_dpaux_clk_en(dp->dpaux); |
2093 | 2095 | ||
2094 | tegra_dc_io_start(dp->dc); | 2096 | tegra_dc_io_start(dp->dc); |
@@ -2119,11 +2121,6 @@ static int tegra_dc_dp_hotplug_init(struct tegra_dc *dc) | |||
2119 | struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc); | 2121 | struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc); |
2120 | 2122 | ||
2121 | /* | 2123 | /* |
2122 | * SOR partition must be awake for dpaux | ||
2123 | */ | ||
2124 | tegra_dc_unpowergate_locked(dc); | ||
2125 | |||
2126 | /* | ||
2127 | * dp interrupts are received by dpaux. | 2124 | * dp interrupts are received by dpaux. |
2128 | * Initialize dpaux to receive hotplug events. | 2125 | * Initialize dpaux to receive hotplug events. |
2129 | */ | 2126 | */ |
@@ -3213,7 +3210,7 @@ static void tegra_dc_dp_suspend(struct tegra_dc *dc) | |||
3213 | 3210 | ||
3214 | tegra_dp_hpd_suspend(dp); | 3211 | tegra_dp_hpd_suspend(dp); |
3215 | 3212 | ||
3216 | tegra_dc_powergate_locked(dc); | 3213 | tegra_powergate_partition(dp->dpaux->powergate_id); |
3217 | } | 3214 | } |
3218 | 3215 | ||
3219 | static void tegra_dc_dp_resume(struct tegra_dc *dc) | 3216 | static void tegra_dc_dp_resume(struct tegra_dc *dc) |
@@ -3223,8 +3220,6 @@ static void tegra_dc_dp_resume(struct tegra_dc *dc) | |||
3223 | if (!dp->suspended) | 3220 | if (!dp->suspended) |
3224 | return; | 3221 | return; |
3225 | 3222 | ||
3226 | tegra_dc_unpowergate_locked(dc); | ||
3227 | |||
3228 | if (dp->pdata->hdmi2fpd_bridge_enable) | 3223 | if (dp->pdata->hdmi2fpd_bridge_enable) |
3229 | hdmi2fpd_resume(dc); | 3224 | hdmi2fpd_resume(dc); |
3230 | 3225 | ||