video: tegra: dp: Fix CTS 4.2.2.2

CTS description: DPCD sink capability read
upon HPD

Bug 200103501

Change-Id: Iba000486c4fd72e651394710037eebd17dd02eec
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/782416
(cherry picked from commit 8e2de69e87a4194a73cb929b6057a5f850478d46)
Reviewed-on: http://git-master/r/812194
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

1 files changed, 54 insertions, 21 deletions

diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index 740c8cab9..7eeeac387 100644
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -1536,8 +1536,11 @@ static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
                 u8 dpcd_data;
                 int ret;
 
-                CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
-                        &dpcd_data));
+                if (dp->sink_cap_valid)
+                        dpcd_data = dp->sink_cap[NV_DPCD_MAX_LANE_COUNT];
+                else
+                        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
+                                NV_DPCD_MAX_LANE_COUNT, &dpcd_data));
 
                 cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
                 if (dp->pdata && dp->pdata->lanes &&
@@ -1545,28 +1548,36 @@ static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
                         cfg->max_lane_count = dp->pdata->lanes;
 
                 cfg->tps3_supported =
-                (dpcd_data & NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ?
-                true : false;
-
+                        (dpcd_data &
+                        NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ?
+                        true : false;
                 cfg->support_enhanced_framing =
                 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
                 true : false;
 
-                CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
-                        &dpcd_data));
+                if (dp->sink_cap_valid)
+                        dpcd_data = dp->sink_cap[NV_DPCD_MAX_DOWNSPREAD];
+                else
+                        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
+                                        NV_DPCD_MAX_DOWNSPREAD, &dpcd_data));
                 cfg->downspread =
-                (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
-                true : false;
-
+                        (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
+                        true : false;
                 cfg->support_fast_lt = (dpcd_data &
-                NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ? true : false;
+                        NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ?
+                        true : false;
 
                 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
                         NV_DPCD_TRAINING_AUX_RD_INTERVAL, &dpcd_data));
                 cfg->aux_rd_interval = dpcd_data;
 
-                CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
-                        &cfg->max_link_bw));
+                if (dp->sink_cap_valid)
+                        cfg->max_link_bw =
+                                dp->sink_cap[NV_DPCD_MAX_LINK_BANDWIDTH];
+                else
+                        CHECK_RET(tegra_dc_dp_dpcd_read(dp,
+                                NV_DPCD_MAX_LINK_BANDWIDTH,
+                                &cfg->max_link_bw));
                 if (dp->pdata && dp->pdata->link_bw &&
                         dp->pdata->link_bw < cfg->max_link_bw)
                         cfg->max_link_bw = dp->pdata->link_bw;
@@ -1574,15 +1585,14 @@ static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
                         &dpcd_data));
                 cfg->alt_scramber_reset_cap =
-                (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
-                true : false;
-
-                cfg->only_enhanced_framing =
-                (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
-                true : false;
-
+                        (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
+                        true : false;
+                cfg->only_enhanced_framing = (dpcd_data &
+                        NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
+                        true : false;
                 cfg->edp_cap = (dpcd_data &
-                NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ? true : false;
+                        NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ?
+                        true : false;
         }
 
         cfg->bits_per_pixel = dp->dc->out->depth ? : 24;
@@ -2170,6 +2180,27 @@ void tegra_dp_update_link_config(struct tegra_dc_dp_data *dp)
         tegra_dp_tu_config(dp, cfg);
 }
 
+static void tegra_dp_read_sink_cap(struct tegra_dc_dp_data *dp)
+{
+        struct tegra_dc *dc = dp->dc;
+        u32 sink_cap_rd_size = DP_DPCD_SINK_CAP_SIZE;
+        u32 aux_stat = 0;
+        u8 start_offset = 0;
+        int err;
+
+        tegra_dc_io_start(dc);
+
+        dp->sink_cap_valid = false;
+
+        err = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+                                start_offset, dp->sink_cap, &sink_cap_rd_size,
+                                &aux_stat);
+        if (!err)
+                dp->sink_cap_valid = true;
+
+        tegra_dc_io_end(dc);
+}
+
 static void tegra_dp_hpd_op_edid_ready(void *drv_data)
 {
         struct tegra_dc_dp_data *dp = drv_data;
@@ -2187,6 +2218,8 @@ static void tegra_dp_hpd_op_edid_ready(void *drv_data)
          */
         dc->out->width = dc->out->width ? : dc->out->h_size;
         dc->out->height = dc->out->height ? : dc->out->v_size;
+
+        tegra_dp_read_sink_cap(dp);
 }
 
 static void tegra_dp_hpd_op_edid_recheck(void *drv_data)