kernel: video: dc: dp fixes for nvdisp

Fix Dp to work for single channel.
Correction for dp to work with unitfpga.

Change-Id: I656dd39cf37a3aa6f2a997f07f82efff80228e38
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: http://git-master/r/682174
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

1 files changed, 27 insertions, 12 deletions

diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index 75c6dc770..a3ca11737 100644
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -1,7 +1,7 @@
 /*
  * drivers/video/tegra/dc/dp.c
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION, All rights reserved.
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION, All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -456,7 +456,7 @@ static int tegra_dc_dpaux_read_chunk_locked(struct tegra_dc_dp_data *dp,
                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
 
                 /* Ignore I2C errors on fpga */
-                if (tegra_platform_is_fpga())
+                if (!tegra_platform_is_silicon())
                         *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
 
                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
@@ -1811,7 +1811,7 @@ static int tegra_dp_hpd_plug(struct tegra_dc_dp_data *dp)
 
         might_sleep();
 
-        if (tegra_platform_is_fpga()) {
+        if (!tegra_platform_is_silicon()) {
                 msleep(TEGRA_DP_HPD_PLUG_TIMEOUT_MS);
                 return 0;
         }
@@ -1871,6 +1871,9 @@ static void tegra_dp_lt_config(struct tegra_dc_dp_data *dp,
         u32 cnt;
         u32 val;
 
+        /* support for 1 lane */
+        u32 loopcnt = (n_lanes == 1) ? 1 : n_lanes >> 1;
+
         for (cnt = 0; cnt < n_lanes; cnt++) {
                 u32 mask = 0;
                 u32 pe_reg, vs_reg, pc_reg;
@@ -1938,7 +1941,7 @@ static void tegra_dp_lt_config(struct tegra_dc_dp_data *dp,
                         (NV_DPCD_TRAINING_LANE0_SET + cnt), val);
         }
         if (pc_supported) {
-                for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+                for (cnt = 0; cnt < loopcnt; cnt++) {
                         u32 max_pc_flag0 = tegra_dp_is_max_pc(pc[cnt]);
                         u32 max_pc_flag1 = tegra_dp_is_max_pc(pc[cnt + 1]);
                         val = (pc[cnt] << NV_DPCD_LANEX_SET2_PC2_SHIFT) |
@@ -1962,7 +1965,10 @@ static bool tegra_dp_clock_recovery_status(struct tegra_dc_dp_data *dp)
         u32 n_lanes = dp->link_cfg.lane_count;
         u8 data_ptr;
 
-        for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+        /* support for 1 lane */
+        u32 loopcnt = (n_lanes == 1) ? 1 : n_lanes >> 1;
+
+        for (cnt = 0; cnt < loopcnt; cnt++) {
                 tegra_dc_dp_dpcd_read(dp,
                         (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);
 
@@ -1981,11 +1987,14 @@ static void tegra_dp_lt_adjust(struct tegra_dc_dp_data *dp,
                                 u32 pe[4], u32 vs[4], u32 pc[4],
                                 bool pc_supported)
 {
-        size_t cnt;
+        u32 cnt;
         u8 data_ptr;
         u32 n_lanes = dp->link_cfg.lane_count;
 
-        for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+        /* support for 1 lane */
+        u32 loopcnt = (n_lanes == 1) ? 1 : n_lanes >> 1;
+
+        for (cnt = 0; cnt < loopcnt; cnt++) {
                 tegra_dc_dp_dpcd_read(dp,
                         (NV_DPCD_LANE0_1_ADJUST_REQ + cnt), &data_ptr);
                 pe[2 * cnt] = (data_ptr & NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
@@ -2061,7 +2070,10 @@ static bool tegra_dp_channel_eq_status(struct tegra_dc_dp_data *dp)
         u8 data_ptr;
         bool ce_done = true;
 
-        for (cnt = 0; cnt < n_lanes / 2; cnt++) {
+        /* support for 1 lane */
+        u32 loopcnt = (n_lanes == 1) ? 1 : n_lanes >> 1;
+
+        for (cnt = 0; cnt < loopcnt; cnt++) {
                 tegra_dc_dp_dpcd_read(dp,
                         (NV_DPCD_LANE0_1_STATUS + cnt), &data_ptr);
 
@@ -2417,7 +2429,8 @@ static void tegra_dc_dp_enable(struct tegra_dc *dc)
         }
 
         if (dp->dp_edid && !dp->dp_edid->data &&
-                (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP))
+                (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP) &&
+                !tegra_platform_is_linsim())
                 tegra_dp_edid(dp);
 
         tegra_dp_dpcd_init(dp);
@@ -2527,7 +2540,7 @@ static long tegra_dc_dp_setup_clk(struct tegra_dc *dc, struct clk *clk)
         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
         struct clk *dc_parent_clk;
 
-        if (tegra_platform_is_fpga())
+        if (!tegra_platform_is_silicon())
                 return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
 
         if (clk == dc->clk) {
@@ -2550,7 +2563,8 @@ static bool tegra_dc_dp_detect(struct tegra_dc *dc)
         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
         u32 rd;
 
-        if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
+        if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
+                tegra_platform_is_linsim())
                 return  true;
 
         tegra_dc_io_start(dc);
@@ -2575,7 +2589,8 @@ static void tegra_dc_dp_modeset_notifier(struct tegra_dc *dc)
         tegra_dc_sor_modeset_notifier(dp->sor, false);
         /* Pixel clock may be changed in new mode,
          * recalculate link config */
-        tegra_dc_dp_calc_config(dp, dp->mode, &dp->link_cfg);
+        if (!tegra_platform_is_linsim())
+                tegra_dc_dp_calc_config(dp, dp->mode, &dp->link_cfg);
 
 
         tegra_dpaux_clk_disable(dp);