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authorArun Swain <arswain@nvidia.com>2016-09-26 21:51:39 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-12-28 00:34:11 -0500
commitb8950ace1fbbea326d1af84e77441bf81e4c083d (patch)
treee9861f8a8f40c48f3f9b29afbdb033ad990fed06 /drivers/video/tegra/dc/dc.c
parent34e5013f58a0bf0996725e197f4d92692ae3184a (diff)
display: dc: Add wrap_output_delay for dual_dsc
Calculate wrap_output_delay based on the number of dsc modules used. Bug 1839145 Change-Id: I3bfad23374429906d79e773e9f4e3e2cf39725c8 Signed-off-by: Arun Swain <arswain@nvidia.com> Reviewed-on: http://git-master/r/1227533 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Ishwarya Balaji Gururajan <igururajan@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers/video/tegra/dc/dc.c')
-rw-r--r--drivers/video/tegra/dc/dc.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 84ff88cee..20008b2f4 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -4582,7 +4582,13 @@ void tegra_dc_dsc_init(struct tegra_dc *dc)
4582 hblank = mode->h_sync_width + mode->h_front_porch + mode->h_back_porch; 4582 hblank = mode->h_sync_width + mode->h_front_porch + mode->h_back_porch;
4583 output_delay = ((delay_in_slice / slice_width) * 4583 output_delay = ((delay_in_slice / slice_width) *
4584 (mode->h_active + hblank)) + (delay_in_slice % slice_width); 4584 (mode->h_active + hblank)) + (delay_in_slice % slice_width);
4585 wrap_output_delay = output_delay + 20; 4585 if (dc->out->dual_dsc_en) {
4586 wrap_output_delay = output_delay * 2 + mode->h_active / 2 + 28;
4587 if (wrap_output_delay % 2)
4588 wrap_output_delay += 1;
4589 } else {
4590 wrap_output_delay = output_delay + 20;
4591 }
4586 val = DSC_VALID_OUTPUT_DELAY(output_delay); 4592 val = DSC_VALID_OUTPUT_DELAY(output_delay);
4587 val |= DSC_VALID_WRAP_OUTPUT_DELAY(wrap_output_delay); 4593 val |= DSC_VALID_WRAP_OUTPUT_DELAY(wrap_output_delay);
4588 tegra_dc_writel(dc, val, DC_COM_DSC_DELAY); 4594 tegra_dc_writel(dc, val, DC_COM_DSC_DELAY);