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authorkartik <kkartik@nvidia.com>2018-09-03 23:28:14 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-04 09:40:08 -0400
commit53448a2835d96fb84e6dc84d776cde1ccb01fe3d (patch)
treec2e466a3f6a57230a2394724c11a32eadcf4b03e /drivers/tty
parent510ee67fc8114b16317fb010b62288192ed57a2b (diff)
serial: tegra: add driver for no HW flow control
- Add separate driver for no HW flow control support to avoid issues by adding below features to exiting serial-tegra.c - In RX path, use dma cyclic mode with double buffering to avoid latency to stop and start the DMA again in RX path. - This driver only supports receiving data in multiple of 8 bytes as RX path is only in DMA mode, so if any data that is not aligned then that data sits in the FIFO until further data arrives. Bug 1874194 Bug 1997353 Change-Id: I6ca22daac3cb794c666fc45263c1a9aea3191986 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1459931 Signed-off-by: kartik <kkartik@nvidia.com> (cherry picked from k3.18 commit 73e2d4c51839233259176024c33e6ff7eca595da) Reviewed-on: https://git-master.nvidia.com/r/1812156 Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Tested-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/Makefile1
-rw-r--r--drivers/tty/serial/serial-tegra-nohw.c1677
2 files changed, 1678 insertions, 0 deletions
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 11c766cfa..6a83da498 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -1,3 +1,4 @@
1obj-$(CONFIG_TEGRA_COMBINED_UART) += tegra-combined-uart.o 1obj-$(CONFIG_TEGRA_COMBINED_UART) += tegra-combined-uart.o
2obj-$(CONFIG_TEGRA_COMBINED_UART) += tegra-combined-uart-early.o 2obj-$(CONFIG_TEGRA_COMBINED_UART) += tegra-combined-uart-early.o
3obj-$(CONFIG_TEGRA_HV_COMM) += tegra_hv_comm.o 3obj-$(CONFIG_TEGRA_HV_COMM) += tegra_hv_comm.o
4obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra-nohw.o
diff --git a/drivers/tty/serial/serial-tegra-nohw.c b/drivers/tty/serial/serial-tegra-nohw.c
new file mode 100644
index 000000000..1f0212057
--- /dev/null
+++ b/drivers/tty/serial/serial-tegra-nohw.c
@@ -0,0 +1,1677 @@
1/*
2 * serial-tegra-nohw.c
3 *
4 * High-speed serial no hardware flow control driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <linux/clk.h>
24#include <linux/debugfs.h>
25#include <linux/delay.h>
26#include <linux/dmaengine.h>
27#include <linux/dma-mapping.h>
28#include <linux/dmapool.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/irq.h>
32#include <linux/module.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/pagemap.h>
36#include <linux/platform_device.h>
37#include <linux/reset.h>
38#include <linux/serial.h>
39#include <linux/serial_8250.h>
40#include <linux/serial_core.h>
41#include <linux/serial_reg.h>
42#include <linux/slab.h>
43#include <linux/string.h>
44#include <linux/termios.h>
45#include <linux/tty.h>
46#include <linux/tty_flip.h>
47#include <linux/timer.h>
48#include <linux/kthread.h>
49
50#define TEGRA_UART_TYPE "TEGRA_UART"
51#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
52#define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
53
54#define TEGRA_UART_RX_DMA_BUFFER_SIZE (2 * 4096)
55#define TEGRA_UART_LSR_TXFIFO_FULL 0x100
56#define TEGRA_UART_IER_EORD 0x20
57#define TEGRA_UART_MCR_RTS_EN 0x40
58#define TEGRA_UART_MCR_CTS_EN 0x20
59#define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
60 UART_LSR_PE | UART_LSR_FE)
61#define TEGRA_UART_IRDA_CSR 0x08
62#define TEGRA_UART_SIR_ENABLED 0x80
63
64#define TEGRA_UART_TX_PIO 1
65#define TEGRA_UART_TX_DMA 2
66#define TEGRA_UART_MIN_DMA 16
67#define TEGRA_UART_FIFO_SIZE 32
68
69/*
70 * Tx fifo trigger level setting in tegra uart is in
71 * reverse way then conventional uart.
72 */
73#define TEGRA_UART_TX_TRIG_16B 0x00
74#define TEGRA_UART_TX_TRIG_8B 0x10
75#define TEGRA_UART_TX_TRIG_4B 0x20
76#define TEGRA_UART_TX_TRIG_1B 0x30
77
78#define TEGRA_UART_MAXIMUM 5
79
80/* Default UART setting when started: 115200 no parity, stop, 8 data bits */
81#define TEGRA_UART_DEFAULT_BAUD 115200
82#define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
83
84/* Tx transfer mode */
85#define TEGRA_TX_PIO 1
86#define TEGRA_TX_DMA 2
87
88#define TEGRA_UART_FCR_IIR_FIFO_EN 0x40
89
90/**
91 * tegra_uart_chip_data: SOC specific data.
92 *
93 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
94 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
95 * Tegra30 does not allow this.
96 * @support_clk_src_div: Clock source support the clock divider.
97 */
98struct tegra_uart_chip_data {
99 bool tx_fifo_full_status;
100 bool allow_txfifo_reset_fifo_mode;
101 bool support_clk_src_div;
102 bool fifo_mode_enable_status;
103 bool dma_8bytes_burst_only;
104 int error_tolerance_low_range;
105 int error_tolerance_high_range;
106};
107
108struct tegra_baud_tolerance {
109 u32 lower_range_baud;
110 u32 upper_range_baud;
111 s32 tolerance;
112};
113
114struct tegra_uart_port {
115 struct uart_port uport;
116 const struct tegra_uart_chip_data *cdata;
117
118 struct clk *uart_clk;
119 struct reset_control *rst;
120 unsigned int current_baud;
121
122 /* Register shadow */
123 unsigned long fcr_shadow;
124 unsigned long mcr_shadow;
125 unsigned long lcr_shadow;
126 unsigned long ier_shadow;
127 bool rts_active;
128
129 int tx_in_progress;
130 unsigned int tx_bytes;
131
132 bool enable_modem_interrupt;
133
134 bool rx_timeout;
135 int rx_in_progress;
136 int symb_bit;
137
138 struct dma_chan *rx_dma_chan;
139 struct dma_chan *tx_dma_chan;
140 dma_addr_t rx_dma_buf_phys;
141 dma_addr_t rx_ring_dma_buf_phys;
142 dma_addr_t tx_dma_buf_phys;
143 unsigned char *rx_dma_buf_virt;
144 unsigned char *tx_dma_buf_virt;
145 struct dma_async_tx_descriptor *tx_dma_desc;
146 struct dma_async_tx_descriptor *rx_dma_desc;
147 dma_cookie_t tx_cookie;
148 dma_cookie_t rx_cookie;
149 unsigned int tx_bytes_requested;
150 unsigned int rx_period_len;
151 unsigned int rx_total_bytes;
152 struct tegra_baud_tolerance *baud_tolerance;
153 int n_adjustable_baud_rates;
154 struct timer_list timer;
155 int timer_timeout_jiffies;
156 bool is_hw_flow_enabled;
157 int required_rate;
158 int configured_rate;
159 struct dentry *debugfs;
160 bool early_printk_console_instance;
161 bool rt_flush;
162 struct circ_buf rx_ring;
163 u64 prev_xfer_count;
164 u64 curr_xfer_count;
165};
166
167static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
168static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
169
170static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
171 unsigned long reg)
172{
173 return readl(tup->uport.membase + (reg << tup->uport.regshift));
174}
175
176static inline void tegra_uart_write(struct tegra_uart_port *tup,
177 unsigned int val, unsigned long reg)
178{
179 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
180}
181
182static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
183{
184 return container_of(u, struct tegra_uart_port, uport);
185}
186
187static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
188{
189 struct tegra_uart_port *tup = to_tegra_uport(u);
190
191 /*
192 * RI - Ring detector is active
193 * CD/DCD/CAR - Carrier detect is always active. For some reason
194 * linux has different names for carrier detect.
195 * DSR - Data Set ready is active as the hardware doesn't support it.
196 * Don't know if the linux support this yet?
197 * CTS - Clear to send. Always set to active, as the hardware handles
198 * CTS automatically.
199 */
200 if (tup->enable_modem_interrupt)
201 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
202 return TIOCM_CTS;
203}
204
205static void set_rts(struct tegra_uart_port *tup, bool active)
206{
207 unsigned long mcr;
208
209 mcr = tup->mcr_shadow;
210 if (active)
211 mcr |= TEGRA_UART_MCR_RTS_EN;
212 else
213 mcr &= ~TEGRA_UART_MCR_RTS_EN;
214 if (mcr != tup->mcr_shadow) {
215 tegra_uart_write(tup, mcr, UART_MCR);
216 tup->mcr_shadow = mcr;
217 }
218}
219
220static void set_dtr(struct tegra_uart_port *tup, bool active)
221{
222 unsigned long mcr;
223
224 mcr = tup->mcr_shadow;
225 if (active)
226 mcr |= UART_MCR_DTR;
227 else
228 mcr &= ~UART_MCR_DTR;
229 if (mcr != tup->mcr_shadow) {
230 tegra_uart_write(tup, mcr, UART_MCR);
231 tup->mcr_shadow = mcr;
232 }
233}
234
235static void set_loopbk(struct tegra_uart_port *tup, bool active)
236{
237 unsigned long mcr;
238
239 mcr = tup->mcr_shadow;
240 if (active)
241 mcr |= UART_MCR_LOOP;
242 else
243 mcr &= ~UART_MCR_LOOP;
244 if (mcr != tup->mcr_shadow) {
245 tegra_uart_write(tup, mcr, UART_MCR);
246 tup->mcr_shadow = mcr;
247 }
248}
249
250static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
251{
252 struct tegra_uart_port *tup = to_tegra_uport(u);
253 unsigned long mcr;
254 int dtr_enable;
255 int loopbk_enable;
256
257 mcr = tup->mcr_shadow;
258 tup->rts_active = !!(mctrl & TIOCM_RTS);
259 set_rts(tup, tup->rts_active);
260
261 dtr_enable = !!(mctrl & TIOCM_DTR);
262 set_dtr(tup, dtr_enable);
263
264 loopbk_enable = !!(mctrl & TIOCM_LOOP);
265 set_loopbk(tup, loopbk_enable);
266}
267
268static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
269{
270 struct tegra_uart_port *tup = to_tegra_uport(u);
271 unsigned long lcr;
272
273 lcr = tup->lcr_shadow;
274 if (break_ctl)
275 lcr |= UART_LCR_SBC;
276 else
277 lcr &= ~UART_LCR_SBC;
278 tegra_uart_write(tup, lcr, UART_LCR);
279 tup->lcr_shadow = lcr;
280}
281
282/**
283 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
284 *
285 * @tup: Tegra serial port data structure.
286 * @cycles: Number of clock periods to wait.
287 *
288 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
289 * clock speed is 16X the current baud rate.
290 */
291static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
292 unsigned int cycles)
293{
294 if (tup->current_baud)
295 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
296}
297
298/* Wait for a symbol-time. */
299static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
300 unsigned int syms)
301{
302 if (tup->current_baud)
303 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
304 tup->current_baud));
305}
306
307static int tegra_uart_is_fifo_mode_enabled(struct tegra_uart_port *tup)
308{
309 unsigned long iir;
310 unsigned int tmout = 100;
311 int ret = -EIO;
312
313 do {
314 iir = tegra_uart_read(tup, UART_IIR);
315 if (iir & TEGRA_UART_FCR_IIR_FIFO_EN) {
316 ret = 0;
317 break;
318 }
319 if (--tmout == 0)
320 break;
321 udelay(1);
322 } while (1);
323
324 return ret;
325}
326
327static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
328{
329 unsigned long fcr = tup->fcr_shadow;
330 int ret;
331
332 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
333 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
334 tegra_uart_write(tup, fcr, UART_FCR);
335 } else {
336 fcr &= ~UART_FCR_ENABLE_FIFO;
337 tegra_uart_write(tup, fcr, UART_FCR);
338 udelay(60);
339 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
340 tegra_uart_write(tup, fcr, UART_FCR);
341 fcr |= UART_FCR_ENABLE_FIFO;
342 tegra_uart_write(tup, fcr, UART_FCR);
343 if (tup->cdata->fifo_mode_enable_status) {
344 ret = tegra_uart_is_fifo_mode_enabled(tup);
345 if (ret < 0)
346 dev_err(tup->uport.dev, "FIFO mode not enabled\n");
347 }
348 }
349
350 /* Dummy read to ensure the write is posted */
351 tegra_uart_read(tup, UART_SCR);
352
353 /*
354 * For all tegra devices (up to t210), there is a hardware issue that
355 * requires software to wait for 32 UART clock periods for the flush
356 * to propagate, otherwise data could be lost.
357 */
358 tegra_uart_wait_cycle_time(tup, 32);
359}
360
361static long tegra_get_tolerance_rate(struct tegra_uart_port *tup,
362 unsigned int baud, long rate)
363{
364 int i;
365
366 for (i = 0; i < tup->n_adjustable_baud_rates; ++i) {
367 if (baud >= tup->baud_tolerance[i].lower_range_baud &&
368 baud <= tup->baud_tolerance[i].upper_range_baud)
369 return (rate + (rate *
370 tup->baud_tolerance[i].tolerance) / 10000);
371 }
372
373 return rate;
374}
375
376static void tegra_check_rate_in_range(struct tegra_uart_port *tup)
377{
378 int diff;
379 u32 error;
380
381 diff = ((tup->configured_rate - tup->required_rate) * 10000)
382 / tup->required_rate;
383 error = diff < 0 ? -diff : diff;
384 if (diff < (tup->cdata->error_tolerance_low_range * 100) ||
385 diff > (tup->cdata->error_tolerance_high_range * 100))
386 dev_err(tup->uport.dev,
387 "configured rate out of supported range by %c%d.%d %%",
388 (diff < 0) ? '-':'+',
389 (error/100), (error - (error/100) * 100));
390}
391
392static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
393{
394 unsigned long rate;
395 unsigned int divisor;
396 unsigned long lcr;
397 int ret;
398
399 if (tup->current_baud == baud)
400 return 0;
401
402 if (tup->cdata->support_clk_src_div) {
403 rate = baud * 16;
404 tup->required_rate = rate;
405 if (tup->n_adjustable_baud_rates)
406 rate = tegra_get_tolerance_rate(tup, baud, rate);
407
408 ret = clk_set_rate(tup->uart_clk, rate);
409 if (ret < 0) {
410 dev_err(tup->uport.dev,
411 "clk_set_rate() failed for rate %lu\n", rate);
412 return ret;
413 }
414 tup->configured_rate = clk_get_rate(tup->uart_clk);
415 tegra_check_rate_in_range(tup);
416 divisor = 1;
417 } else {
418 rate = clk_get_rate(tup->uart_clk);
419 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
420 }
421
422 lcr = tup->lcr_shadow;
423 lcr |= UART_LCR_DLAB;
424 tegra_uart_write(tup, lcr, UART_LCR);
425
426 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
427 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
428
429 lcr &= ~UART_LCR_DLAB;
430 tegra_uart_write(tup, lcr, UART_LCR);
431
432 /* Dummy read to ensure the write is posted */
433 tegra_uart_read(tup, UART_SCR);
434
435 tup->current_baud = baud;
436
437 /* wait two character intervals at new rate */
438 tegra_uart_wait_sym_time(tup, 2);
439 return 0;
440}
441
442static void tegra_uart_flush_fifo(struct tegra_uart_port *tup, u8 fcr_bits)
443{
444 unsigned long fcr = tup->fcr_shadow;
445 unsigned int lsr, tmout = 10000;
446
447 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
448 tegra_uart_write(tup, fcr, UART_FCR);
449
450 do {
451 lsr = tegra_uart_read(tup, UART_LSR);
452 if (!(lsr & UART_LSR_DR))
453 break;
454 if (--tmout == 0)
455 break;
456 udelay(1);
457 } while (1);
458}
459
460static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
461 unsigned long lsr)
462{
463 char flag = TTY_NORMAL;
464
465 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
466 if (lsr & UART_LSR_BI) {
467 tup->uport.icount.brk++;
468 flag = TTY_BREAK;
469 tegra_uart_flush_fifo(tup, UART_FCR_CLEAR_RCVR);
470
471 if (tup->uport.ignore_status_mask & UART_LSR_BI)
472 goto exit;
473 dev_err(tup->uport.dev, "Got Break\n");
474 } else if (lsr & UART_LSR_PE) {
475 /* Parity error */
476 flag = TTY_PARITY;
477 tup->uport.icount.parity++;
478 dev_err(tup->uport.dev, "Got Parity errors\n");
479 } else if (lsr & UART_LSR_FE) {
480 flag = TTY_FRAME;
481 tup->uport.icount.frame++;
482 tegra_uart_flush_fifo(tup, UART_FCR_CLEAR_RCVR);
483 dev_err(tup->uport.dev, "Got frame errors\n");
484 } else if (lsr & UART_LSR_OE) {
485 /* Overrrun error */
486 flag |= TTY_OVERRUN;
487 tup->uport.icount.overrun++;
488 dev_err(tup->uport.dev, "Got overrun errors\n");
489 }
490 uart_insert_char(&tup->uport, lsr, UART_LSR_OE, 0, flag);
491 }
492
493exit:
494 return flag;
495}
496
497static int tegra_uart_request_port(struct uart_port *u)
498{
499 return 0;
500}
501
502static void tegra_uart_release_port(struct uart_port *u)
503{
504 /* Nothing to do here */
505}
506
507static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
508{
509 struct circ_buf *xmit = &tup->uport.state->xmit;
510 int i;
511
512 for (i = 0; i < max_bytes; i++) {
513 WARN_ON(uart_circ_empty(xmit));
514 if (tup->cdata->tx_fifo_full_status) {
515 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
516
517 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
518 break;
519 }
520 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
521 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
522 tup->uport.icount.tx++;
523 }
524}
525
526static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
527 unsigned int bytes)
528{
529 if (bytes > TEGRA_UART_MIN_DMA)
530 bytes = TEGRA_UART_MIN_DMA;
531
532 tup->tx_in_progress = TEGRA_UART_TX_PIO;
533 tup->tx_bytes = bytes;
534 tup->ier_shadow |= UART_IER_THRI;
535 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
536}
537
538static void tegra_uart_tx_dma_complete(void *args)
539{
540 struct tegra_uart_port *tup = args;
541 struct circ_buf *xmit = &tup->uport.state->xmit;
542 struct dma_tx_state state;
543 unsigned long flags;
544 unsigned int count;
545
546 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
547 count = tup->tx_bytes_requested - state.residue;
548 async_tx_ack(tup->tx_dma_desc);
549 spin_lock_irqsave(&tup->uport.lock, flags);
550 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
551 tup->tx_in_progress = 0;
552 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
553 uart_write_wakeup(&tup->uport);
554 tegra_uart_start_next_tx(tup);
555 spin_unlock_irqrestore(&tup->uport.lock, flags);
556}
557
558static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
559 unsigned long count)
560{
561 struct circ_buf *xmit = &tup->uport.state->xmit;
562 dma_addr_t tx_phys_addr;
563
564 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
565 UART_XMIT_SIZE, DMA_TO_DEVICE);
566
567 tup->tx_bytes = count & ~(0xF);
568 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
569 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
570 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
571 DMA_PREP_INTERRUPT);
572 if (!tup->tx_dma_desc) {
573 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
574 return -EIO;
575 }
576
577 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
578 tup->tx_dma_desc->callback_param = tup;
579 tup->tx_in_progress = TEGRA_UART_TX_DMA;
580 tup->tx_bytes_requested = tup->tx_bytes;
581 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
582 dma_async_issue_pending(tup->tx_dma_chan);
583 return 0;
584}
585
586static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
587{
588 unsigned long tail;
589 unsigned long count;
590 struct circ_buf *xmit = &tup->uport.state->xmit;
591
592 tail = (unsigned long)&xmit->buf[xmit->tail];
593 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
594 if (!count)
595 return;
596
597 if (count < TEGRA_UART_MIN_DMA)
598 tegra_uart_start_pio_tx(tup, count);
599 else if (BYTES_TO_ALIGN(tail) > 0)
600 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
601 else
602 tegra_uart_start_tx_dma(tup, count);
603}
604
605/* Called by serial core driver with u->lock taken. */
606static void tegra_uart_start_tx(struct uart_port *u)
607{
608 struct tegra_uart_port *tup = to_tegra_uport(u);
609 struct circ_buf *xmit = &u->state->xmit;
610
611 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
612 tegra_uart_start_next_tx(tup);
613}
614
615static unsigned int tegra_uart_tx_empty(struct uart_port *u)
616{
617 struct tegra_uart_port *tup = to_tegra_uport(u);
618 unsigned int ret = 0;
619 unsigned long flags;
620
621 spin_lock_irqsave(&u->lock, flags);
622 if (!tup->tx_in_progress) {
623 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
624
625 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
626 ret = TIOCSER_TEMT;
627 }
628 spin_unlock_irqrestore(&u->lock, flags);
629 return ret;
630}
631
632static void tegra_uart_stop_tx(struct uart_port *u)
633{
634 struct tegra_uart_port *tup = to_tegra_uport(u);
635 struct circ_buf *xmit = &tup->uport.state->xmit;
636 struct dma_tx_state state;
637 unsigned int count;
638
639 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
640 return;
641
642 dmaengine_terminate_all(tup->tx_dma_chan);
643 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
644 count = tup->tx_bytes_requested - state.residue;
645 async_tx_ack(tup->tx_dma_desc);
646 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
647 tup->tx_in_progress = 0;
648}
649
650static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
651{
652 struct circ_buf *xmit = &tup->uport.state->xmit;
653
654 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
655 tup->tx_in_progress = 0;
656 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
657 uart_write_wakeup(&tup->uport);
658 tegra_uart_start_next_tx(tup);
659}
660
661static int tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
662 struct tty_port *tty,
663 unsigned char *rx_buf,
664 unsigned int count)
665{
666 int copied;
667 int ret = 0;
668
669 /* If count is zero, then there is no data to be copied */
670 if (!count)
671 return 0;
672
673 tup->uport.icount.rx += count;
674 if (!tty) {
675 dev_err(tup->uport.dev, "No tty port\n");
676 return -EINVAL;
677 }
678
679 if (tup->uport.ignore_status_mask & UART_LSR_DR)
680 return 0;
681
682 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_ring_dma_buf_phys,
683 count, DMA_FROM_DEVICE);
684 copied = tty_insert_flip_string(tty, rx_buf, count);
685 if (copied != count) {
686 dev_err(tup->uport.dev, "RxData DMA copy to tty layer failed\n");
687 ret = -ENOSPC;
688 }
689 dma_sync_single_for_device(tup->uport.dev, tup->rx_ring_dma_buf_phys,
690 count, DMA_TO_DEVICE);
691 return ret;
692}
693
694static int tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
695 unsigned int count)
696{
697 struct tty_port *port = &tup->uport.state->port;
698 struct tty_struct *tty = tty_port_tty_get(port);
699 struct circ_buf *ring = &tup->rx_ring;
700 unsigned char *rx_buf;
701 int ret;
702
703 if (!count)
704 return 0;
705
706 if (ring->head + count > tup->rx_total_bytes)
707 ring->head = ring->head + count - tup->rx_total_bytes;
708 else
709 ring->head += count;
710
711 if (ring->head < ring->tail) {
712 count = tup->rx_total_bytes - ring->tail;
713 rx_buf = ring->buf + ring->tail;
714 tup->rx_ring_dma_buf_phys = tup->rx_dma_buf_phys + ring->tail;
715 ret = tegra_uart_copy_rx_to_tty(tup, port, rx_buf, count);
716 ring->tail = 0;
717 if (ret)
718 return ret;
719 }
720
721 if (ring->tail < ring->head) {
722 count = ring->head - ring->tail;
723 rx_buf = ring->buf + ring->tail;
724 tup->rx_ring_dma_buf_phys = tup->rx_dma_buf_phys + ring->tail;
725 ret = tegra_uart_copy_rx_to_tty(tup, port, rx_buf, count);
726 ring->tail = ring->head;
727 if (ret)
728 return ret;
729 }
730
731 if (tty) {
732 tty_flip_buffer_push(port);
733 tty_kref_put(tty);
734 }
735
736 return ret;
737}
738
739static void tegra_uart_rx_dma_complete(void *args)
740{
741 struct tegra_uart_port *tup = args;
742 struct uart_port *u = &tup->uport;
743 struct dma_tx_state state;
744 unsigned long flags;
745 unsigned int count = 0;
746
747 spin_lock_irqsave(&u->lock, flags);
748 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
749 tup->curr_xfer_count = state.total_bytes_transferred;
750 count = tup->curr_xfer_count - tup->prev_xfer_count;
751 tup->prev_xfer_count = tup->curr_xfer_count;
752
753 if (!count)
754 goto exit;
755
756 tegra_uart_rx_buffer_push(tup, count);
757exit:
758 spin_unlock_irqrestore(&u->lock, flags);
759}
760
761static int tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
762{
763 struct dma_tx_state state;
764 int count = 0;
765
766 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
767 tup->curr_xfer_count = state.total_bytes_transferred;
768 count = tup->curr_xfer_count - tup->prev_xfer_count;
769 tup->prev_xfer_count = tup->curr_xfer_count;
770
771 if (!count)
772 goto exit;
773
774 tegra_uart_rx_buffer_push(tup, count);
775exit:
776 return 0;
777}
778
779static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
780{
781 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
782
783 tup->rx_period_len = count/2;
784 tup->rx_dma_desc = dmaengine_prep_dma_cyclic(tup->rx_dma_chan,
785 tup->rx_dma_buf_phys, count, tup->rx_period_len,
786 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
787
788 if (!tup->rx_dma_desc) {
789 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
790 return -EIO;
791 }
792
793 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
794 tup->rx_dma_desc->callback_param = tup;
795 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
796 count, DMA_TO_DEVICE);
797 tup->rx_total_bytes = count;
798 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
799 dma_async_issue_pending(tup->rx_dma_chan);
800 return 0;
801}
802
803static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
804{
805 struct tegra_uart_port *tup = to_tegra_uport(u);
806 unsigned long msr;
807
808 msr = tegra_uart_read(tup, UART_MSR);
809 if (!(msr & UART_MSR_ANY_DELTA))
810 return;
811
812 if (msr & UART_MSR_TERI)
813 tup->uport.icount.rng++;
814 if (msr & UART_MSR_DDSR)
815 tup->uport.icount.dsr++;
816 /* We may only get DDCD when HW init and reset */
817 if (msr & UART_MSR_DDCD)
818 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
819 /* Will start/stop_tx accordingly */
820 if (msr & UART_MSR_DCTS)
821 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
822}
823
824static irqreturn_t tegra_uart_isr(int irq, void *data)
825{
826 struct tegra_uart_port *tup = data;
827 struct uart_port *u = &tup->uport;
828 unsigned long iir;
829 unsigned long ier;
830 bool is_rx_int = false;
831 unsigned long flags;
832 int ret;
833
834 spin_lock_irqsave(&u->lock, flags);
835 while (1) {
836 iir = tegra_uart_read(tup, UART_IIR);
837 if (iir & UART_IIR_NO_INT) {
838 if (is_rx_int) {
839 ret = tegra_uart_handle_rx_dma(tup);
840 if (ret) {
841 spin_unlock_irqrestore(&u->lock, flags);
842 return IRQ_HANDLED;
843 }
844 if (tup->rx_in_progress) {
845 ier = tup->ier_shadow;
846 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
847 TEGRA_UART_IER_EORD);
848 tup->ier_shadow = ier;
849 tegra_uart_write(tup, ier, UART_IER);
850 }
851 }
852 spin_unlock_irqrestore(&u->lock, flags);
853 return IRQ_HANDLED;
854 }
855
856 switch ((iir >> 1) & 0x7) {
857 case 0: /* Modem signal change interrupt */
858 tegra_uart_handle_modem_signal_change(u);
859 break;
860
861 case 1: /* Transmit interrupt only triggered when using PIO */
862 tup->ier_shadow &= ~UART_IER_THRI;
863 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
864 tegra_uart_handle_tx_pio(tup);
865 break;
866 case 6: /* Rx timeout */
867 case 4: /* End of data */
868 case 2: /* Receive */
869 is_rx_int = true;
870 ier = tup->ier_shadow;
871 ier |= UART_IER_RDI;
872 tegra_uart_write(tup, ier, UART_IER);
873 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
874 TEGRA_UART_IER_EORD);
875 tup->ier_shadow = ier;
876 tegra_uart_write(tup, ier, UART_IER);
877 break;
878
879 case 3: /* Receive error */
880 tegra_uart_decode_rx_error(tup,
881 tegra_uart_read(tup, UART_LSR));
882 break;
883
884 case 5: /* break nothing to handle */
885 case 7: /* break nothing to handle */
886 break;
887 }
888 }
889}
890
891static void tegra_uart_stop_rx(struct uart_port *u)
892{
893 struct tegra_uart_port *tup = to_tegra_uport(u);
894 struct dma_tx_state state;
895 unsigned long ier;
896 unsigned int count = 0;
897
898
899 if (tup->rts_active && tup->is_hw_flow_enabled)
900 set_rts(tup, false);
901
902 if (!tup->rx_in_progress)
903 return;
904
905 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
906
907 ier = tup->ier_shadow;
908 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
909 TEGRA_UART_IER_EORD);
910 tup->ier_shadow = ier;
911 tegra_uart_write(tup, ier, UART_IER);
912 tup->rx_in_progress = 0;
913 if (tup->rx_dma_chan) {
914 dmaengine_terminate_all(tup->rx_dma_chan);
915 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie,
916 &state);
917 tup->curr_xfer_count = state.total_bytes_transferred;
918 count = tup->curr_xfer_count - tup->prev_xfer_count;
919 tup->prev_xfer_count = tup->curr_xfer_count;
920
921 if (!count)
922 return;
923 tegra_uart_rx_buffer_push(tup, count);
924 }
925}
926
927static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
928{
929 unsigned long flags;
930 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
931 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
932 unsigned long wait_time;
933 unsigned long lsr;
934 unsigned long msr;
935 unsigned long mcr;
936
937 /* Disable interrupts */
938 tegra_uart_write(tup, 0, UART_IER);
939
940 lsr = tegra_uart_read(tup, UART_LSR);
941 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
942 msr = tegra_uart_read(tup, UART_MSR);
943 mcr = tegra_uart_read(tup, UART_MCR);
944 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
945 dev_err(tup->uport.dev,
946 "Tx Fifo not empty, CTS disabled, waiting\n");
947
948 /* Wait for Tx fifo to be empty */
949 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
950 wait_time = min(fifo_empty_time, 100lu);
951 udelay(wait_time);
952 fifo_empty_time -= wait_time;
953 if (!fifo_empty_time) {
954 msr = tegra_uart_read(tup, UART_MSR);
955 mcr = tegra_uart_read(tup, UART_MCR);
956 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
957 (msr & UART_MSR_CTS))
958 dev_err(tup->uport.dev,
959 "Slave not ready\n");
960 break;
961 }
962 lsr = tegra_uart_read(tup, UART_LSR);
963 }
964 }
965
966 spin_lock_irqsave(&tup->uport.lock, flags);
967 /* Reset the Rx and Tx FIFOs */
968 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
969 tup->current_baud = 0;
970 spin_unlock_irqrestore(&tup->uport.lock, flags);
971
972 clk_disable_unprepare(tup->uart_clk);
973}
974
975static int tegra_uart_hw_init(struct tegra_uart_port *tup)
976{
977 int ret;
978
979 tup->fcr_shadow = 0;
980 tup->mcr_shadow = 0;
981 tup->lcr_shadow = 0;
982 tup->ier_shadow = 0;
983 tup->current_baud = 0;
984
985 clk_prepare_enable(tup->uart_clk);
986
987 /* Reset the UART controller to clear all previous status.*/
988 reset_control_assert(tup->rst);
989 udelay(10);
990 reset_control_deassert(tup->rst);
991
992 tup->rx_in_progress = 0;
993 tup->tx_in_progress = 0;
994
995 /*
996 * Set the trigger level
997 *
998 * For PIO mode:
999 *
1000 * For receive, this will interrupt the CPU after that many number of
1001 * bytes are received, for the remaining bytes the receive timeout
1002 * interrupt is received. Rx high watermark is set to 4.
1003 *
1004 * For transmit, if the trasnmit interrupt is enabled, this will
1005 * interrupt the CPU when the number of entries in the FIFO reaches the
1006 * low watermark. Tx low watermark is set to 16 bytes.
1007 *
1008 * For DMA mode:
1009 *
1010 * Set the Tx trigger to 16. This should match the DMA burst size that
1011 * programmed in the DMA registers.
1012 */
1013 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
1014
1015 if (tup->cdata->dma_8bytes_burst_only)
1016 tup->fcr_shadow |= UART_FCR_R_TRIG_10;
1017 else
1018 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
1019
1020 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
1021 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1022
1023 /* Dummy read to ensure the write is posted */
1024 tegra_uart_read(tup, UART_SCR);
1025
1026
1027 if (tup->cdata->fifo_mode_enable_status) {
1028 ret = tegra_uart_is_fifo_mode_enabled(tup);
1029 if (ret < 0) {
1030 dev_err(tup->uport.dev, "FIFO mode not enabled\n");
1031 return ret;
1032 }
1033 } else {
1034 /*
1035 * For all tegra devices (up to t210), there is a hardware
1036 * issue that requires software to wait for 3 UART clock
1037 * periods after enabling the TX fifo, otherwise data could
1038 * be lost.
1039 */
1040 tegra_uart_wait_cycle_time(tup, 3);
1041 }
1042
1043 /*
1044 * Initialize the UART with default configuration
1045 * (115200, N, 8, 1) so that the receive DMA buffer may be
1046 * enqueued
1047 */
1048 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
1049 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
1050 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
1051 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
1052
1053 ret = tegra_uart_start_rx_dma(tup);
1054 if (ret < 0) {
1055 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
1056 return ret;
1057 }
1058 tup->rx_in_progress = 1;
1059
1060 /*
1061 * Enable IE_RXS for the receive status interrupts like line errros.
1062 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
1063 *
1064 * If using DMA mode, enable EORD instead of receive interrupt which
1065 * will interrupt after the UART is done with the receive instead of
1066 * the interrupt when the FIFO "threshold" is reached.
1067 *
1068 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
1069 * the DATA is sitting in the FIFO and couldn't be transferred to the
1070 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
1071 * triggered when there is a pause of the incoming data stream for 4
1072 * characters long.
1073 *
1074 * For pauses in the data which is not aligned to 4 bytes, we get
1075 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
1076 * then the EORD.
1077 */
1078 tup->ier_shadow = UART_IER_RLSI | TEGRA_UART_IER_EORD | UART_IER_RTOIE;
1079
1080 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1081 return 0;
1082}
1083
1084static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
1085 bool dma_to_memory)
1086{
1087 if (dma_to_memory) {
1088 dmaengine_terminate_all(tup->rx_dma_chan);
1089 dma_release_channel(tup->rx_dma_chan);
1090 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
1091 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
1092 tup->rx_dma_chan = NULL;
1093 tup->rx_dma_buf_phys = 0;
1094 tup->rx_dma_buf_virt = NULL;
1095 } else {
1096 dmaengine_terminate_all(tup->tx_dma_chan);
1097 dma_release_channel(tup->tx_dma_chan);
1098 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
1099 UART_XMIT_SIZE, DMA_TO_DEVICE);
1100 tup->tx_dma_chan = NULL;
1101 tup->tx_dma_buf_phys = 0;
1102 tup->tx_dma_buf_virt = NULL;
1103 }
1104}
1105
1106static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
1107 bool dma_to_memory)
1108{
1109 struct dma_chan *dma_chan;
1110 unsigned char *dma_buf;
1111 dma_addr_t dma_phys;
1112 int ret;
1113 struct dma_slave_config dma_sconfig;
1114
1115 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
1116 dma_to_memory ? "rx" : "tx");
1117 if (IS_ERR(dma_chan)) {
1118 ret = PTR_ERR(dma_chan);
1119 dev_err(tup->uport.dev,
1120 "DMA channel alloc failed: %d\n", ret);
1121 return ret;
1122 }
1123
1124 if (dma_to_memory) {
1125 dma_buf = dma_alloc_coherent(tup->uport.dev,
1126 TEGRA_UART_RX_DMA_BUFFER_SIZE,
1127 &dma_phys, GFP_KERNEL);
1128 if (!dma_buf) {
1129 dev_err(tup->uport.dev,
1130 "Not able to allocate the dma buffer\n");
1131 dma_release_channel(dma_chan);
1132 return -ENOMEM;
1133 }
1134 dma_sconfig.src_addr = tup->uport.mapbase;
1135 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1136 if (tup->cdata->dma_8bytes_burst_only)
1137 dma_sconfig.src_maxburst = 8;
1138 else
1139 dma_sconfig.src_maxburst = 4;
1140 tup->rx_dma_chan = dma_chan;
1141 tup->rx_dma_buf_virt = dma_buf;
1142 tup->rx_ring.buf = dma_buf;
1143 tup->rx_dma_buf_phys = dma_phys;
1144 tup->rx_ring_dma_buf_phys = dma_phys;
1145 } else {
1146 dma_phys = dma_map_single(tup->uport.dev,
1147 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
1148 DMA_TO_DEVICE);
1149 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
1150 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
1151 dma_release_channel(dma_chan);
1152 return -ENOMEM;
1153 }
1154 dma_buf = tup->uport.state->xmit.buf;
1155 dma_sconfig.dst_addr = tup->uport.mapbase;
1156 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1157 dma_sconfig.dst_maxburst = 16;
1158 tup->tx_dma_chan = dma_chan;
1159 tup->tx_dma_buf_virt = dma_buf;
1160 tup->tx_dma_buf_phys = dma_phys;
1161 }
1162
1163 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
1164 if (ret < 0) {
1165 dev_err(tup->uport.dev,
1166 "Dma slave config failed, err = %d\n", ret);
1167 tegra_uart_dma_channel_free(tup, dma_to_memory);
1168 return ret;
1169 }
1170
1171 return 0;
1172}
1173
1174static int tegra_uart_startup(struct uart_port *u)
1175{
1176 struct tegra_uart_port *tup = to_tegra_uport(u);
1177 int ret;
1178
1179 ret = tegra_uart_dma_channel_allocate(tup, false);
1180 if (ret < 0) {
1181 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n",
1182 ret);
1183 return ret;
1184 }
1185
1186 ret = tegra_uart_dma_channel_allocate(tup, true);
1187 if (ret < 0) {
1188 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n",
1189 ret);
1190 goto fail_rx_dma;
1191 }
1192
1193 ret = tegra_uart_hw_init(tup);
1194 if (ret < 0) {
1195 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1196 goto fail_hw_init;
1197 }
1198
1199 ret = request_irq(u->irq, tegra_uart_isr, 0,
1200 dev_name(u->dev), tup);
1201 if (ret < 0) {
1202 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1203 goto fail_hw_init;
1204 }
1205 tup->rx_ring.head = tup->rx_ring.tail = 0;
1206 tup->prev_xfer_count = tup->curr_xfer_count = 0;
1207 return 0;
1208
1209fail_hw_init:
1210 tegra_uart_dma_channel_free(tup, true);
1211fail_rx_dma:
1212 tegra_uart_dma_channel_free(tup, false);
1213 return ret;
1214}
1215
1216/*
1217 * Flush any TX data submitted for DMA and PIO. Called when the
1218 * TX circular buffer is reset.
1219 */
1220static void tegra_uart_flush_buffer(struct uart_port *u)
1221{
1222 struct tegra_uart_port *tup = to_tegra_uport(u);
1223
1224 tup->tx_bytes = 0;
1225 if (tup->tx_dma_chan)
1226 dmaengine_terminate_all(tup->tx_dma_chan);
1227}
1228
1229static void tegra_uart_shutdown(struct uart_port *u)
1230{
1231 struct tegra_uart_port *tup = to_tegra_uport(u);
1232
1233 tegra_uart_hw_deinit(tup);
1234
1235 tup->rx_in_progress = 0;
1236 tup->tx_in_progress = 0;
1237
1238 tegra_uart_dma_channel_free(tup, true);
1239 tegra_uart_dma_channel_free(tup, false);
1240 free_irq(u->irq, tup);
1241}
1242
1243static void tegra_uart_enable_ms(struct uart_port *u)
1244{
1245 struct tegra_uart_port *tup = to_tegra_uport(u);
1246
1247 if (tup->enable_modem_interrupt) {
1248 tup->ier_shadow |= UART_IER_MSI;
1249 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1250 }
1251}
1252
1253static void tegra_uart_set_termios(struct uart_port *u,
1254 struct ktermios *termios, struct ktermios *oldtermios)
1255{
1256 struct tegra_uart_port *tup = to_tegra_uport(u);
1257 unsigned int baud;
1258 unsigned long flags;
1259 unsigned int lcr;
1260 int symb_bit = 1;
1261 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1262 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1263 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1264
1265 max_divider *= 16;
1266 spin_lock_irqsave(&u->lock, flags);
1267
1268 /* Changing configuration, it is safe to stop any rx now */
1269 if (tup->rts_active)
1270 set_rts(tup, false);
1271
1272 /* Clear all interrupts as configuration is going to be change */
1273 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1274 tegra_uart_read(tup, UART_IER);
1275 tegra_uart_write(tup, 0, UART_IER);
1276 tegra_uart_read(tup, UART_IER);
1277
1278 /* Parity */
1279 lcr = tup->lcr_shadow;
1280 lcr &= ~UART_LCR_PARITY;
1281
1282 /* CMSPAR isn't supported by this driver */
1283 termios->c_cflag &= ~CMSPAR;
1284
1285 if ((termios->c_cflag & PARENB) == PARENB) {
1286 symb_bit++;
1287 if (termios->c_cflag & PARODD) {
1288 lcr |= UART_LCR_PARITY;
1289 lcr &= ~UART_LCR_EPAR;
1290 lcr &= ~UART_LCR_SPAR;
1291 } else {
1292 lcr |= UART_LCR_PARITY;
1293 lcr |= UART_LCR_EPAR;
1294 lcr &= ~UART_LCR_SPAR;
1295 }
1296 }
1297
1298 lcr &= ~UART_LCR_WLEN8;
1299 switch (termios->c_cflag & CSIZE) {
1300 case CS5:
1301 lcr |= UART_LCR_WLEN5;
1302 symb_bit += 5;
1303 break;
1304 case CS6:
1305 lcr |= UART_LCR_WLEN6;
1306 symb_bit += 6;
1307 break;
1308 case CS7:
1309 lcr |= UART_LCR_WLEN7;
1310 symb_bit += 7;
1311 break;
1312 default:
1313 lcr |= UART_LCR_WLEN8;
1314 symb_bit += 8;
1315 break;
1316 }
1317
1318 /* Stop bits */
1319 if (termios->c_cflag & CSTOPB) {
1320 lcr |= UART_LCR_STOP;
1321 symb_bit += 2;
1322 } else {
1323 lcr &= ~UART_LCR_STOP;
1324 symb_bit++;
1325 }
1326
1327 tegra_uart_write(tup, lcr, UART_LCR);
1328 tup->lcr_shadow = lcr;
1329 tup->symb_bit = symb_bit;
1330
1331 /* Baud rate. */
1332 baud = uart_get_baud_rate(u, termios, oldtermios,
1333 parent_clk_rate/max_divider,
1334 parent_clk_rate/16);
1335 spin_unlock_irqrestore(&u->lock, flags);
1336 tegra_set_baudrate(tup, baud);
1337 if (tty_termios_baud_rate(termios))
1338 tty_termios_encode_baud_rate(termios, baud, baud);
1339 spin_lock_irqsave(&u->lock, flags);
1340
1341 /* Flow control */
1342 if (termios->c_cflag & CRTSCTS) {
1343 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1344 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1345 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1346 tup->is_hw_flow_enabled = true;
1347 /* if top layer has asked to set rts active then do so here */
1348 if (tup->rts_active && tup->is_hw_flow_enabled)
1349 set_rts(tup, true);
1350 } else {
1351 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1352 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1353 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1354 tup->is_hw_flow_enabled = false;
1355 }
1356
1357 /* update the port timeout based on new settings */
1358 uart_update_timeout(u, termios->c_cflag, baud);
1359
1360 /* Make sure all write has completed */
1361 tegra_uart_read(tup, UART_IER);
1362
1363 /* Reenable interrupt */
1364 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1365 tegra_uart_read(tup, UART_IER);
1366
1367 tup->uport.ignore_status_mask = 0;
1368 /* Ignore all characters if CREAD is not set */
1369 if ((termios->c_cflag & CREAD) == 0)
1370 tup->uport.ignore_status_mask |= UART_LSR_DR;
1371 if (termios->c_iflag & IGNBRK)
1372 tup->uport.ignore_status_mask |= UART_LSR_BI;
1373
1374 spin_unlock_irqrestore(&u->lock, flags);
1375}
1376
1377static const char *tegra_uart_type(struct uart_port *u)
1378{
1379 return TEGRA_UART_TYPE;
1380}
1381
1382static const struct uart_ops tegra_uart_ops = {
1383 .tx_empty = tegra_uart_tx_empty,
1384 .set_mctrl = tegra_uart_set_mctrl,
1385 .get_mctrl = tegra_uart_get_mctrl,
1386 .stop_tx = tegra_uart_stop_tx,
1387 .start_tx = tegra_uart_start_tx,
1388 .stop_rx = tegra_uart_stop_rx,
1389 .flush_buffer = tegra_uart_flush_buffer,
1390 .enable_ms = tegra_uart_enable_ms,
1391 .break_ctl = tegra_uart_break_ctl,
1392 .startup = tegra_uart_startup,
1393 .shutdown = tegra_uart_shutdown,
1394 .set_termios = tegra_uart_set_termios,
1395 .type = tegra_uart_type,
1396 .request_port = tegra_uart_request_port,
1397 .release_port = tegra_uart_release_port,
1398};
1399
1400static struct uart_driver tegra_uart_driver = {
1401 .owner = THIS_MODULE,
1402 .driver_name = "tegra_hsuart_nohw",
1403 .dev_name = "ttyTHS",
1404 .cons = NULL,
1405 .nr = TEGRA_UART_MAXIMUM,
1406};
1407
1408static int tegra_uart_parse_dt(struct platform_device *pdev,
1409 struct tegra_uart_port *tup)
1410{
1411 struct device_node *np = pdev->dev.of_node;
1412 int port;
1413 int ret;
1414 int index;
1415 u32 pval;
1416 int count;
1417 int n_entries;
1418
1419 port = of_alias_get_id(np, "serial");
1420 if (port < 0) {
1421 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1422 return port;
1423 }
1424 tup->uport.line = port;
1425
1426 tup->enable_modem_interrupt = of_property_read_bool(np,
1427 "nvidia,enable-modem-interrupt");
1428
1429 tup->early_printk_console_instance = of_property_read_bool(np,
1430 "early-print-console-channel");
1431
1432 tup->rt_flush = of_property_read_bool(np, "rt-flush");
1433
1434 n_entries = of_property_count_u32_elems(np, "nvidia,adjust-baud-rates");
1435 if (n_entries > 0) {
1436 tup->n_adjustable_baud_rates = n_entries/3;
1437 tup->baud_tolerance = devm_kzalloc(&pdev->dev,
1438 (tup->n_adjustable_baud_rates) *
1439 sizeof(*tup->baud_tolerance), GFP_KERNEL);
1440 if (!tup->baud_tolerance)
1441 return -ENOMEM;
1442 for (count = 0, index = 0; count < n_entries;
1443 count += 3, index++) {
1444 ret = of_property_read_u32_index(np,
1445 "nvidia,adjust-baud-rates",
1446 count, &pval);
1447 if (!ret)
1448 tup->baud_tolerance[index].lower_range_baud =
1449 pval;
1450 ret = of_property_read_u32_index(np,
1451 "nvidia,adjust-baud-rates",
1452 count + 1, &pval);
1453 if (!ret)
1454 tup->baud_tolerance[index].upper_range_baud =
1455 pval;
1456 ret = of_property_read_u32_index(np,
1457 "nvidia,adjust-baud-rates",
1458 count + 2, &pval);
1459 if (!ret)
1460 tup->baud_tolerance[index].tolerance =
1461 (s32)pval;
1462 }
1463 } else
1464 tup->n_adjustable_baud_rates = 0;
1465
1466 return 0;
1467}
1468
1469#ifdef CONFIG_DEBUG_FS
1470static void tegra_uart_debugfs_init(struct tegra_uart_port *tup)
1471{
1472 tup->debugfs = debugfs_create_dir(dev_name(tup->uport.dev), NULL);
1473 if (IS_ERR_OR_NULL(tup->debugfs))
1474 goto clean;
1475
1476 debugfs_create_u32("required_rate", 0644, tup->debugfs,
1477 &tup->required_rate);
1478 debugfs_create_u32("config_rate", 0644, tup->debugfs,
1479 &tup->configured_rate);
1480 return;
1481clean:
1482 dev_warn(tup->uport.dev, "Failed to create debugfs!\n");
1483 debugfs_remove_recursive(tup->debugfs);
1484}
1485
1486static void tegra_uart_debugfs_deinit(struct tegra_uart_port *tup)
1487{
1488 debugfs_remove_recursive(tup->debugfs);
1489}
1490#else
1491static void tegra_uart_debugfs_init(struct tegra_uart_port *tup) {}
1492static void tegra_uart_debugfs_deinit(struct tegra_uart_port *tup) {}
1493#endif
1494
1495static struct tegra_uart_chip_data tegra186_uart_chip_data = {
1496 .tx_fifo_full_status = true,
1497 .allow_txfifo_reset_fifo_mode = false,
1498 .support_clk_src_div = true,
1499 .fifo_mode_enable_status = true,
1500 .dma_8bytes_burst_only = true,
1501 .error_tolerance_low_range = 0,
1502 .error_tolerance_high_range = 4,
1503};
1504
1505static const struct of_device_id tegra_uart_of_match[] = {
1506 {
1507 .compatible = "nvidia,tegra186-hsuart-nohw",
1508 .data = &tegra186_uart_chip_data,
1509 }, {
1510 },
1511};
1512MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1513
1514static int tegra_uart_probe(struct platform_device *pdev)
1515{
1516 struct tegra_uart_port *tup;
1517 struct uart_port *u;
1518 struct resource *resource;
1519 struct clk *parent_clk;
1520 int ret;
1521 const struct tegra_uart_chip_data *cdata;
1522 const struct of_device_id *match;
1523
1524 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1525 if (!match) {
1526 dev_err(&pdev->dev, "Error: No device match found\n");
1527 return -ENODEV;
1528 }
1529 cdata = match->data;
1530
1531 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1532 if (!tup)
1533 return -ENOMEM;
1534
1535 ret = tegra_uart_parse_dt(pdev, tup);
1536 if (ret < 0)
1537 return ret;
1538
1539 u = &tup->uport;
1540 u->dev = &pdev->dev;
1541 u->ops = &tegra_uart_ops;
1542 u->type = PORT_TEGRA;
1543 u->fifosize = 32;
1544 tup->cdata = cdata;
1545
1546 platform_set_drvdata(pdev, tup);
1547 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1548 if (!resource) {
1549 dev_err(&pdev->dev, "No IO memory resource\n");
1550 return -ENODEV;
1551 }
1552
1553 u->mapbase = resource->start;
1554 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1555 if (IS_ERR(u->membase))
1556 return PTR_ERR(u->membase);
1557
1558 tup->uart_clk = devm_clk_get(&pdev->dev, "serial");
1559 if (IS_ERR(tup->uart_clk)) {
1560 dev_err(&pdev->dev, "Couldn't get the clock\n");
1561 return PTR_ERR(tup->uart_clk);
1562 }
1563
1564 tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1565 if (IS_ERR(tup->rst)) {
1566 dev_err(&pdev->dev, "Couldn't get the reset\n");
1567 return PTR_ERR(tup->rst);
1568 }
1569
1570 if (!tup->early_printk_console_instance) {
1571 reset_control_assert(tup->rst);
1572 udelay(10);
1573 reset_control_deassert(tup->rst);
1574 }
1575
1576 parent_clk = devm_clk_get(&pdev->dev, "parent");
1577 if (IS_ERR(parent_clk))
1578 dev_err(&pdev->dev, "Unable to get parent_clk err: %ld\n",
1579 PTR_ERR(parent_clk));
1580 else {
1581 ret = clk_set_parent(tup->uart_clk, parent_clk);
1582 if (ret < 0)
1583 dev_warn(&pdev->dev,
1584 "Couldn't set the parent clock - %d\n", ret);
1585 }
1586
1587 u->iotype = UPIO_MEM32;
1588 u->irq = platform_get_irq(pdev, 0);
1589 u->regshift = 2;
1590 u->rt_flush = tup->rt_flush;
1591 ret = uart_add_one_port(&tegra_uart_driver, u);
1592 if (ret < 0) {
1593 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1594 return ret;
1595 }
1596
1597 tegra_uart_debugfs_init(tup);
1598
1599 return ret;
1600}
1601
1602static int tegra_uart_remove(struct platform_device *pdev)
1603{
1604 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1605 struct uart_port *u = &tup->uport;
1606
1607 tegra_uart_debugfs_deinit(tup);
1608 uart_remove_one_port(&tegra_uart_driver, u);
1609 return 0;
1610}
1611
1612#ifdef CONFIG_PM_SLEEP
1613static int tegra_uart_suspend(struct device *dev)
1614{
1615 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1616 struct uart_port *u = &tup->uport;
1617
1618 return uart_suspend_port(&tegra_uart_driver, u);
1619}
1620
1621static int tegra_uart_resume(struct device *dev)
1622{
1623 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1624 struct uart_port *u = &tup->uport;
1625
1626 return uart_resume_port(&tegra_uart_driver, u);
1627}
1628#endif
1629
1630static const struct dev_pm_ops tegra_uart_pm_ops = {
1631 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1632};
1633
1634static struct platform_driver tegra_uart_platform_driver = {
1635 .probe = tegra_uart_probe,
1636 .remove = tegra_uart_remove,
1637 .driver = {
1638 .name = "serial-tegra-nohw",
1639 .of_match_table = tegra_uart_of_match,
1640 .pm = &tegra_uart_pm_ops,
1641 },
1642};
1643
1644static int __init tegra_uart_init(void)
1645{
1646 int ret;
1647
1648 ret = uart_register_driver(&tegra_uart_driver);
1649 if (ret < 0) {
1650 pr_err("Could not register %s driver\n",
1651 tegra_uart_driver.driver_name);
1652 return ret;
1653 }
1654
1655 ret = platform_driver_register(&tegra_uart_platform_driver);
1656 if (ret < 0) {
1657 pr_err("Uart platform driver register failed, e = %d\n", ret);
1658 uart_unregister_driver(&tegra_uart_driver);
1659 return ret;
1660 }
1661 return 0;
1662}
1663
1664static void __exit tegra_uart_exit(void)
1665{
1666 pr_info("Unloading tegra uart driver\n");
1667 platform_driver_unregister(&tegra_uart_platform_driver);
1668 uart_unregister_driver(&tegra_uart_driver);
1669}
1670
1671module_init(tegra_uart_init);
1672module_exit(tegra_uart_exit);
1673
1674MODULE_ALIAS("platform:serial-tegra");
1675MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1676MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1677MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-08 03:12:39 -0400