padctl: t186: clear PD2 along with PD2_OVRD_EN

Clearing PD2 is not strictly required (functionally) as clearing
PD2_OVRD_EN can move the control back to HW, but if we clear PD2 as well
we just restore the registers to same state as before.

This change clears PD2 in tegra186_cdp_phy_set_cdp() and in
tegra_phy_xusb_utmi_pad_charger_detect_off() along with clearing
PD2_OVRD_EN bit.

Bug 200248439

Change-Id: Id1992dc8a108fadf82f4489cfdf31a642ebe2706
Signed-off-by: Mark Kuo <mkuo@nvidia.com>
Reviewed-on: http://git-master/r/1245682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
Reviewed-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/pinctrl/pinctrl-tegra186-padctl.c b/drivers/pinctrl/pinctrl-tegra186-padctl.c
index 157e2e88b..1a5338c08 100644
--- a/drivers/pinctrl/pinctrl-tegra186-padctl.c
+++ b/drivers/pinctrl/pinctrl-tegra186-padctl.c
@@ -1677,7 +1677,7 @@ static int tegra186_cdp_phy_set_cdp(struct phy *phy, bool enable)
 
                 reg = padctl_readl(padctl,
                                    XUSB_PADCTL_USB2_OTG_PADX_CTL0(port));
-                reg &= ~USB2_OTG_PD2_OVRD_EN;
+                reg &= ~(USB2_OTG_PD2 | USB2_OTG_PD2_OVRD_EN);
                 padctl_writel(padctl, reg,
                               XUSB_PADCTL_USB2_OTG_PADX_CTL0(port));
 
@@ -3320,7 +3320,7 @@ void tegra_phy_xusb_utmi_pad_charger_detect_off(struct phy *phy)
         padctl_writel(padctl, reg, USB2_BATTERY_CHRG_OTGPADX_CTL0(port));
 
         reg = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(port));
-        reg &= ~USB2_OTG_PD2_OVRD_EN;
+        reg &= ~(USB2_OTG_PD2 | USB2_OTG_PD2_OVRD_EN);
         padctl_writel(padctl, reg, XUSB_PADCTL_USB2_OTG_PADX_CTL0(port));
 
         tegra_phy_xusb_utmi_pad_power_down(phy);