diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2016-04-21 05:20:54 -0400 |
|---|---|---|
| committer | Laxman Dewangan <ldewangan@nvidia.com> | 2016-04-22 15:12:12 -0400 |
| commit | 7cb337fd583e402b8afe6db3e396fd6c933db0ee (patch) | |
| tree | ab7a7e3daccf1ef04db3cb45580b4b446efd3a9c /drivers/pinctrl | |
| parent | 7274cf0af87175345784e59a162919e2d488d199 (diff) | |
pinctrl: tegra: Remove unused register member
Most of the pincontrol bits are part of the mux register
so just using this register and removing the need of other
registers.
Change-Id: I6254215a243fbb18ee9e2713760c597292a9efed
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1130298
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/pinctrl-tegra186.c | 50 |
1 files changed, 18 insertions, 32 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra186.c b/drivers/pinctrl/pinctrl-tegra186.c index fa74c8b6c..3ca884142 100644 --- a/drivers/pinctrl/pinctrl-tegra186.c +++ b/drivers/pinctrl/pinctrl-tegra186.c | |||
| @@ -3253,13 +3253,13 @@ static const struct tegra_function tegra186_functions[] = { | |||
| 3253 | }, \ | 3253 | }, \ |
| 3254 | .mux_reg = PINGROUP_REG_Y(r), \ | 3254 | .mux_reg = PINGROUP_REG_Y(r), \ |
| 3255 | .drvdn_bit = -1, \ | 3255 | .drvdn_bit = -1, \ |
| 3256 | .parked_reg = -1, \ | ||
| 3257 | .drvup_bit = -1, \ | 3256 | .drvup_bit = -1, \ |
| 3258 | .slwr_bit = -1, \ | 3257 | .slwr_bit = -1, \ |
| 3259 | .slwf_bit = -1, \ | 3258 | .slwf_bit = -1, \ |
| 3260 | .lpmd_bit = -1, \ | 3259 | .lpmd_bit = -1, \ |
| 3261 | .lock_reg = -1, \ | 3260 | .lock_bit = -1, \ |
| 3262 | .hsm_reg = -1, \ | 3261 | .hsm_bit = -1, \ |
| 3262 | .parked_bit = -1, \ | ||
| 3263 | .mux_bank = bank, \ | 3263 | .mux_bank = bank, \ |
| 3264 | .mux_bit = 0, \ | 3264 | .mux_bit = 0, \ |
| 3265 | .pupd_reg = PINGROUP_REG_##pupd(r), \ | 3265 | .pupd_reg = PINGROUP_REG_##pupd(r), \ |
| @@ -3268,37 +3268,16 @@ static const struct tegra_function tegra186_functions[] = { | |||
| 3268 | .tri_reg = PINGROUP_REG_Y(r), \ | 3268 | .tri_reg = PINGROUP_REG_Y(r), \ |
| 3269 | .tri_bank = bank, \ | 3269 | .tri_bank = bank, \ |
| 3270 | .tri_bit = 4, \ | 3270 | .tri_bit = 4, \ |
| 3271 | .e_io_hv_reg = PINGROUP_REG_Y(r), \ | ||
| 3272 | .e_io_hv_bank = bank, \ | ||
| 3273 | .e_io_hv_bit = e_io_hv, \ | 3271 | .e_io_hv_bit = e_io_hv, \ |
| 3274 | .einput_reg = PINGROUP_REG_Y(r), \ | ||
| 3275 | .einput_bank = bank, \ | ||
| 3276 | .einput_bit = e_input, \ | 3272 | .einput_bit = e_input, \ |
| 3277 | .gpio_reg = PINGROUP_REG_Y(r), \ | ||
| 3278 | .gpio_bank = bank, \ | ||
| 3279 | .gpio_bit = gpio_sfio_sel, \ | 3273 | .gpio_bit = gpio_sfio_sel, \ |
| 3280 | .odrain_reg = PINGROUP_REG_Y(r), \ | ||
| 3281 | .odrain_bit = e_od, \ | 3274 | .odrain_bit = e_od, \ |
| 3282 | .odrain_bank = bank, \ | ||
| 3283 | .schmitt_bit = schmitt_b, \ | 3275 | .schmitt_bit = schmitt_b, \ |
| 3284 | .schmitt_reg = PINGROUP_REG_Y(r), \ | ||
| 3285 | .drvtype_reg = PINGROUP_REG_##drvtype(r), \ | ||
| 3286 | .drvtype_bank = bank, \ | ||
| 3287 | .drvtype_bit = 13, \ | 3276 | .drvtype_bit = 13, \ |
| 3288 | .drvtype_width = 2, \ | ||
| 3289 | .lpdr_reg = PINGROUP_REG_Y(r), \ | ||
| 3290 | .lpdr_bank = bank, \ | ||
| 3291 | .lpdr_bit = e_lpdr, \ | 3277 | .lpdr_bit = e_lpdr, \ |
| 3292 | .pbias_buf_reg = PINGROUP_REG_Y(r), \ | ||
| 3293 | .pbias_buf_bank = bank, \ | ||
| 3294 | .pbias_buf_bit = e_io_hv, \ | 3278 | .pbias_buf_bit = e_io_hv, \ |
| 3295 | .preemp_reg = PINGROUP_REG_Y(r), \ | ||
| 3296 | .preemp_bank = bank, \ | ||
| 3297 | .preemp_bit = e_io_hv, \ | 3279 | .preemp_bit = e_io_hv, \ |
| 3298 | .rfu_in_reg = PINGROUP_REG_##rfu_in(r), \ | ||
| 3299 | .rfu_in_bank = bank, \ | ||
| 3300 | .rfu_in_bit = 20, \ | 3280 | .rfu_in_bit = 20, \ |
| 3301 | .rfu_in_width = 4, \ | ||
| 3302 | .drv_reg = -1, \ | 3281 | .drv_reg = -1, \ |
| 3303 | } | 3282 | } |
| 3304 | 3283 | ||
| @@ -3313,15 +3292,19 @@ static const struct tegra_function tegra186_functions[] = { | |||
| 3313 | .mux_reg = -1, \ | 3292 | .mux_reg = -1, \ |
| 3314 | .pupd_reg = -1, \ | 3293 | .pupd_reg = -1, \ |
| 3315 | .tri_reg = -1, \ | 3294 | .tri_reg = -1, \ |
| 3316 | .einput_reg = -1, \ | 3295 | .einput_bit = -1, \ |
| 3317 | .e_io_hv_reg = -1, \ | 3296 | .e_io_hv_bit = -1, \ |
| 3318 | .odrain_reg = -1, \ | 3297 | .odrain_bit = -1, \ |
| 3319 | .lock_reg = -1, \ | 3298 | .lock_bit = -1, \ |
| 3320 | .parked_reg = -1, \ | 3299 | .parked_bit = -1, \ |
| 3321 | .lpmd_bit = -1, \ | 3300 | .lpmd_bit = -1, \ |
| 3322 | .drvtype_reg = -1, \ | 3301 | .drvtype_bit = -1, \ |
| 3323 | .drv_reg = DRV_PINGROUP_Y(r), \ | 3302 | .lpdr_bit = -1, \ |
| 3324 | .drv_bank = bank, \ | 3303 | .pbias_buf_bit = -1, \ |
| 3304 | .preemp_bit = -1, \ | ||
| 3305 | .rfu_in_bit = -1, \ | ||
| 3306 | .drv_reg = DRV_PINGROUP_Y(r), \ | ||
| 3307 | .drv_bank = bank, \ | ||
| 3325 | .drvdn_bit = drvdn_b, \ | 3308 | .drvdn_bit = drvdn_b, \ |
| 3326 | .drvdn_width = drvdn_w, \ | 3309 | .drvdn_width = drvdn_w, \ |
| 3327 | .drvup_bit = drvup_b, \ | 3310 | .drvup_bit = drvup_b, \ |
| @@ -3762,6 +3745,9 @@ static const struct tegra_pinctrl_soc_data tegra186_pinctrl = { | |||
| 3762 | .suspend = tegra186_pinctrl_suspend, | 3745 | .suspend = tegra186_pinctrl_suspend, |
| 3763 | .resume = tegra186_pinctrl_resume, | 3746 | .resume = tegra186_pinctrl_resume, |
| 3764 | .gpio_request_enable = tegra186_gpio_request_enable, | 3747 | .gpio_request_enable = tegra186_gpio_request_enable, |
| 3748 | .hsm_in_mux = false, | ||
| 3749 | .schmitt_in_mux = true, | ||
| 3750 | .drvtype_in_mux = true, | ||
| 3765 | }; | 3751 | }; |
| 3766 | 3752 | ||
| 3767 | static int tegra186_pinctrl_probe(struct platform_device *pdev) | 3753 | static int tegra186_pinctrl_probe(struct platform_device *pdev) |
