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authorLaxman Dewangan <ldewangan@nvidia.com>2017-04-26 09:24:24 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-28 01:07:37 -0400
commita4ee04ae3d8c16e7b7af5c3d30afa68f63b047bc (patch)
tree91c8328d9e94df9911567bf05db035776e1dd18c /drivers/pinctrl/pinctrl-tegra186.c
parent228ddfb7c5b466a486f1b944432b3e24b47ad459 (diff)
pinctrl: t186: Use macros to define enums and pins
Currently, there is lots of duplication in the pin names for defining unique ID, pincontrol descriptors, pins, function and function name. Make the table such that it can take the function argument and define the unique ID, pincontrol descriptors and pins. Similarly define the table for function enum and name. This will reduce lots of table/structure initialisation and reduce the code side by 1600 lines. Change-Id: I416370f625b0f28921cd1e7f088101ebdf80335d Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1470503 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/pinctrl/pinctrl-tegra186.c')
-rw-r--r--drivers/pinctrl/pinctrl-tegra186.c2640
1 files changed, 517 insertions, 2123 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra186.c b/drivers/pinctrl/pinctrl-tegra186.c
index 9cec96d1b..3358f8d90 100644
--- a/drivers/pinctrl/pinctrl-tegra186.c
+++ b/drivers/pinctrl/pinctrl-tegra186.c
@@ -25,585 +25,229 @@
25 * Most pins affected by the pinmux can also be GPIOs. Define these first. 25 * Most pins affected by the pinmux can also be GPIOs. Define these first.
26 * These must match how the GPIO driver names/numbers its pins. 26 * These must match how the GPIO driver names/numbers its pins.
27 */ 27 */
28#define _GPIO(offset) (offset) 28#define T186_PIN_TABLE(fname) \
29 29 fname(PEX_L0_RST_N_PA0, pex_l0_rst_n_pa0, _GPIO, 0) \
30#define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0) 30 fname(PEX_L0_CLKREQ_N_PA1, pex_l0_clkreq_n_pa1, _GPIO, 1) \
31#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1) 31 fname(PEX_WAKE_N_PA2, pex_wake_n_pa2, _GPIO, 2) \
32#define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2) 32 fname(PEX_L1_RST_N_PA3, pex_l1_rst_n_pa3, _GPIO, 3) \
33#define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3) 33 fname(PEX_L1_CLKREQ_N_PA4, pex_l1_clkreq_n_pa4, _GPIO, 4) \
34#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4) 34 fname(PEX_L2_RST_N_PA5, pex_l2_rst_n_pa5, _GPIO, 5) \
35#define TEGRA_PIN_PEX_L2_RST_N_PA5 _GPIO(5) 35 fname(PEX_L2_CLKREQ_N_PA6, pex_l2_clkreq_n_pa6, _GPIO, 6) \
36#define TEGRA_PIN_PEX_L2_CLKREQ_N_PA6 _GPIO(6) 36 fname(UART4_TX_PB0, uart4_tx_pb0, _GPIO, 8) \
37#define TEGRA_PIN_UART4_TX_PB0 _GPIO(8) 37 fname(UART4_RX_PB1, uart4_rx_pb1, _GPIO, 9) \
38#define TEGRA_PIN_UART4_RX_PB1 _GPIO(9) 38 fname(UART4_RTS_PB2, uart4_rts_pb2, _GPIO, 10) \
39#define TEGRA_PIN_UART4_RTS_PB2 _GPIO(10) 39 fname(UART4_CTS_PB3, uart4_cts_pb3, _GPIO, 11) \
40#define TEGRA_PIN_UART4_CTS_PB3 _GPIO(11) 40 fname(GPIO_WAN1_PB4, gpio_wan1_pb4, _GPIO, 12) \
41#define TEGRA_PIN_GPIO_WAN1_PB4 _GPIO(12) 41 fname(GPIO_WAN2_PB5, gpio_wan2_pb5, _GPIO, 13) \
42#define TEGRA_PIN_GPIO_WAN2_PB5 _GPIO(13) 42 fname(GPIO_WAN3_PB6, gpio_wan3_pb6, _GPIO, 14) \
43#define TEGRA_PIN_GPIO_WAN3_PB6 _GPIO(14) 43 fname(GPIO_WAN4_PC0, gpio_wan4_pc0, _GPIO, 16) \
44#define TEGRA_PIN_GPIO_WAN4_PC0 _GPIO(16) 44 fname(DAP2_SCLK_PC1, dap2_sclk_pc1, _GPIO, 17) \
45#define TEGRA_PIN_DAP2_SCLK_PC1 _GPIO(17) 45 fname(DAP2_DOUT_PC2, dap2_dout_pc2, _GPIO, 18) \
46#define TEGRA_PIN_DAP2_DOUT_PC2 _GPIO(18) 46 fname(DAP2_DIN_PC3, dap2_din_pc3, _GPIO, 19) \
47#define TEGRA_PIN_DAP2_DIN_PC3 _GPIO(19) 47 fname(DAP2_FS_PC4, dap2_fs_pc4, _GPIO, 20) \
48#define TEGRA_PIN_DAP2_FS_PC4 _GPIO(20) 48 fname(GEN1_I2C_SCL_PC5, gen1_i2c_scl_pc5, _GPIO, 21) \
49#define TEGRA_PIN_GEN1_I2C_SCL_PC5 _GPIO(21) 49 fname(GEN1_I2C_SDA_PC6, gen1_i2c_sda_pc6, _GPIO, 22) \
50#define TEGRA_PIN_GEN1_I2C_SDA_PC6 _GPIO(22) 50 fname(SDMMC1_CLK_PD0, sdmmc1_clk_pd0, _GPIO, 24) \
51#define TEGRA_PIN_SDMMC1_CLK_PD0 _GPIO(24) 51 fname(SDMMC1_CMD_PD1, sdmmc1_cmd_pd1, _GPIO, 25) \
52#define TEGRA_PIN_SDMMC1_CMD_PD1 _GPIO(25) 52 fname(SDMMC1_DAT0_PD2, sdmmc1_dat0_pd2, _GPIO, 26) \
53#define TEGRA_PIN_SDMMC1_DAT0_PD2 _GPIO(26) 53 fname(SDMMC1_DAT1_PD3, sdmmc1_dat1_pd3, _GPIO, 27) \
54#define TEGRA_PIN_SDMMC1_DAT1_PD3 _GPIO(27) 54 fname(SDMMC1_DAT2_PD4, sdmmc1_dat2_pd4, _GPIO, 28) \
55#define TEGRA_PIN_SDMMC1_DAT2_PD4 _GPIO(28) 55 fname(SDMMC1_DAT3_PD5, sdmmc1_dat3_pd5, _GPIO, 29) \
56#define TEGRA_PIN_SDMMC1_DAT3_PD5 _GPIO(29) 56 fname(EQOS_TXC_PE0, eqos_txc_pe0, _GPIO, 32) \
57#define TEGRA_PIN_EQOS_TXC_PE0 _GPIO(32) 57 fname(EQOS_TD0_PE1, eqos_td0_pe1, _GPIO, 33) \
58#define TEGRA_PIN_EQOS_TD0_PE1 _GPIO(33) 58 fname(EQOS_TD1_PE2, eqos_td1_pe2, _GPIO, 34) \
59#define TEGRA_PIN_EQOS_TD1_PE2 _GPIO(34) 59 fname(EQOS_TD2_PE3, eqos_td2_pe3, _GPIO, 35) \
60#define TEGRA_PIN_EQOS_TD2_PE3 _GPIO(35) 60 fname(EQOS_TD3_PE4, eqos_td3_pe4, _GPIO, 36) \
61#define TEGRA_PIN_EQOS_TD3_PE4 _GPIO(36) 61 fname(EQOS_TX_CTL_PE5, eqos_tx_ctl_pe5, _GPIO, 37) \
62#define TEGRA_PIN_EQOS_TX_CTL_PE5 _GPIO(37) 62 fname(EQOS_RD0_PE6, eqos_rd0_pe6, _GPIO, 38) \
63#define TEGRA_PIN_EQOS_RD0_PE6 _GPIO(38) 63 fname(EQOS_RD1_PE7, eqos_rd1_pe7, _GPIO, 39) \
64#define TEGRA_PIN_EQOS_RD1_PE7 _GPIO(39) 64 fname(EQOS_RD2_PF0, eqos_rd2_pf0, _GPIO, 40) \
65#define TEGRA_PIN_EQOS_RD2_PF0 _GPIO(40) 65 fname(EQOS_RD3_PF1, eqos_rd3_pf1, _GPIO, 41) \
66#define TEGRA_PIN_EQOS_RD3_PF1 _GPIO(41) 66 fname(EQOS_RX_CTL_PF2, eqos_rx_ctl_pf2, _GPIO, 42) \
67#define TEGRA_PIN_EQOS_RX_CTL_PF2 _GPIO(42) 67 fname(EQOS_RXC_PF3, eqos_rxc_pf3, _GPIO, 43) \
68#define TEGRA_PIN_EQOS_RXC_PF3 _GPIO(43) 68 fname(EQOS_MDIO_PF4, eqos_mdio_pf4, _GPIO, 44) \
69#define TEGRA_PIN_EQOS_MDIO_PF4 _GPIO(44) 69 fname(EQOS_MDC_PF5, eqos_mdc_pf5, _GPIO, 45) \
70#define TEGRA_PIN_EQOS_MDC_PF5 _GPIO(45) 70 fname(SDMMC3_CLK_PG0, sdmmc3_clk_pg0, _GPIO, 48) \
71#define TEGRA_PIN_SDMMC3_CLK_PG0 _GPIO(48) 71 fname(SDMMC3_CMD_PG1, sdmmc3_cmd_pg1, _GPIO, 49) \
72#define TEGRA_PIN_SDMMC3_CMD_PG1 _GPIO(49) 72 fname(SDMMC3_DAT0_PG2, sdmmc3_dat0_pg2, _GPIO, 50) \
73#define TEGRA_PIN_SDMMC3_DAT0_PG2 _GPIO(50) 73 fname(SDMMC3_DAT1_PG3, sdmmc3_dat1_pg3, _GPIO, 51) \
74#define TEGRA_PIN_SDMMC3_DAT1_PG3 _GPIO(51) 74 fname(SDMMC3_DAT2_PG4, sdmmc3_dat2_pg4, _GPIO, 52) \
75#define TEGRA_PIN_SDMMC3_DAT2_PG4 _GPIO(52) 75 fname(SDMMC3_DAT3_PG5, sdmmc3_dat3_pg5, _GPIO, 53) \
76#define TEGRA_PIN_SDMMC3_DAT3_PG5 _GPIO(53) 76 fname(GPIO_WAN5_PH0, gpio_wan5_ph0, _GPIO, 56) \
77#define TEGRA_PIN_GPIO_WAN5_PH0 _GPIO(56) 77 fname(GPIO_WAN6_PH1, gpio_wan6_ph1, _GPIO, 57) \
78#define TEGRA_PIN_GPIO_WAN6_PH1 _GPIO(57) 78 fname(GPIO_WAN7_PH2, gpio_wan7_ph2, _GPIO, 58) \
79#define TEGRA_PIN_GPIO_WAN7_PH2 _GPIO(58) 79 fname(GPIO_WAN8_PH3, gpio_wan8_ph3, _GPIO, 59) \
80#define TEGRA_PIN_GPIO_WAN8_PH3 _GPIO(59) 80 fname(BCPU_PWR_REQ_PH4, bcpu_pwr_req_ph4, _GPIO, 60) \
81#define TEGRA_PIN_BCPU_PWR_REQ_PH4 _GPIO(60) 81 fname(MCPU_PWR_REQ_PH5, mcpu_pwr_req_ph5, _GPIO, 61) \
82#define TEGRA_PIN_MCPU_PWR_REQ_PH5 _GPIO(61) 82 fname(GPU_PWR_REQ_PH6, gpu_pwr_req_ph6, _GPIO, 62) \
83#define TEGRA_PIN_GPU_PWR_REQ_PH6 _GPIO(62) 83 fname(GPIO_PQ0_PI0, gpio_pq0_pi0, _GPIO, 64) \
84#define TEGRA_PIN_GPIO_PQ0_PI0 _GPIO(64) 84 fname(GPIO_PQ1_PI1, gpio_pq1_pi1, _GPIO, 65) \
85#define TEGRA_PIN_GPIO_PQ1_PI1 _GPIO(65) 85 fname(GPIO_PQ2_PI2, gpio_pq2_pi2, _GPIO, 66) \
86#define TEGRA_PIN_GPIO_PQ2_PI2 _GPIO(66) 86 fname(GPIO_PQ3_PI3, gpio_pq3_pi3, _GPIO, 67) \
87#define TEGRA_PIN_GPIO_PQ3_PI3 _GPIO(67) 87 fname(GPIO_PQ4_PI4, gpio_pq4_pi4, _GPIO, 68) \
88#define TEGRA_PIN_GPIO_PQ4_PI4 _GPIO(68) 88 fname(GPIO_PQ5_PI5, gpio_pq5_pi5, _GPIO, 69) \
89#define TEGRA_PIN_GPIO_PQ5_PI5 _GPIO(69) 89 fname(GPIO_PQ6_PI6, gpio_pq6_pi6, _GPIO, 70) \
90#define TEGRA_PIN_GPIO_PQ6_PI6 _GPIO(70) 90 fname(GPIO_PQ7_PI7, gpio_pq7_pi7, _GPIO, 71) \
91#define TEGRA_PIN_GPIO_PQ7_PI7 _GPIO(71) 91 fname(DAP1_SCLK_PJ0, dap1_sclk_pj0, _GPIO, 72) \
92#define TEGRA_PIN_DAP1_SCLK_PJ0 _GPIO(72) 92 fname(DAP1_DOUT_PJ1, dap1_dout_pj1, _GPIO, 73) \
93#define TEGRA_PIN_DAP1_DOUT_PJ1 _GPIO(73) 93 fname(DAP1_DIN_PJ2, dap1_din_pj2, _GPIO, 74) \
94#define TEGRA_PIN_DAP1_DIN_PJ2 _GPIO(74) 94 fname(DAP1_FS_PJ3, dap1_fs_pj3, _GPIO, 75) \
95#define TEGRA_PIN_DAP1_FS_PJ3 _GPIO(75) 95 fname(AUD_MCLK_PJ4, aud_mclk_pj4, _GPIO, 76) \
96#define TEGRA_PIN_AUD_MCLK_PJ4 _GPIO(76) 96 fname(GPIO_AUD0_PJ5, gpio_aud0_pj5, _GPIO, 77) \
97#define TEGRA_PIN_GPIO_AUD0_PJ5 _GPIO(77) 97 fname(GPIO_AUD1_PJ6, gpio_aud1_pj6, _GPIO, 78) \
98#define TEGRA_PIN_GPIO_AUD1_PJ6 _GPIO(78) 98 fname(GPIO_AUD2_PJ7, gpio_aud2_pj7, _GPIO, 79) \
99#define TEGRA_PIN_GPIO_AUD2_PJ7 _GPIO(79) 99 fname(GPIO_AUD3_PK0, gpio_aud3_pk0, _GPIO, 80) \
100#define TEGRA_PIN_GPIO_AUD3_PK0 _GPIO(80) 100 fname(GEN7_I2C_SCL_PL0, gen7_i2c_scl_pl0, _GPIO, 88) \
101#define TEGRA_PIN_GEN7_I2C_SCL_PL0 _GPIO(88) 101 fname(GEN7_I2C_SDA_PL1, gen7_i2c_sda_pl1, _GPIO, 89) \
102#define TEGRA_PIN_GEN7_I2C_SDA_PL1 _GPIO(89) 102 fname(GEN9_I2C_SCL_PL2, gen9_i2c_scl_pl2, _GPIO, 90) \
103#define TEGRA_PIN_GEN9_I2C_SCL_PL2 _GPIO(90) 103 fname(GEN9_I2C_SDA_PL3, gen9_i2c_sda_pl3, _GPIO, 91) \
104#define TEGRA_PIN_GEN9_I2C_SDA_PL3 _GPIO(91) 104 fname(USB_VBUS_EN0_PL4, usb_vbus_en0_pl4, _GPIO, 92) \
105#define TEGRA_PIN_USB_VBUS_EN0_PL4 _GPIO(92) 105 fname(USB_VBUS_EN1_PL5, usb_vbus_en1_pl5, _GPIO, 93) \
106#define TEGRA_PIN_USB_VBUS_EN1_PL5 _GPIO(93) 106 fname(GP_PWM6_PL6, gp_pwm6_pl6, _GPIO, 94) \
107#define TEGRA_PIN_GP_PWM6_PL6 _GPIO(94) 107 fname(GP_PWM7_PL7, gp_pwm7_pl7, _GPIO, 95) \
108#define TEGRA_PIN_GP_PWM7_PL7 _GPIO(95) 108 fname(DMIC1_DAT_PM0, dmic1_dat_pm0, _GPIO, 96) \
109#define TEGRA_PIN_DMIC1_DAT_PM0 _GPIO(96) 109 fname(DMIC1_CLK_PM1, dmic1_clk_pm1, _GPIO, 97) \
110#define TEGRA_PIN_DMIC1_CLK_PM1 _GPIO(97) 110 fname(DMIC2_DAT_PM2, dmic2_dat_pm2, _GPIO, 98) \
111#define TEGRA_PIN_DMIC2_DAT_PM2 _GPIO(98) 111 fname(DMIC2_CLK_PM3, dmic2_clk_pm3, _GPIO, 99) \
112#define TEGRA_PIN_DMIC2_CLK_PM3 _GPIO(99) 112 fname(DMIC4_DAT_PM4, dmic4_dat_pm4, _GPIO, 100) \
113#define TEGRA_PIN_DMIC4_DAT_PM4 _GPIO(100) 113 fname(DMIC4_CLK_PM5, dmic4_clk_pm5, _GPIO, 101) \
114#define TEGRA_PIN_DMIC4_CLK_PM5 _GPIO(101) 114 fname(GPIO_CAM1_PN0, gpio_cam1_pn0, _GPIO, 104) \
115#define TEGRA_PIN_GPIO_CAM1_PN0 _GPIO(104) 115 fname(GPIO_CAM2_PN1, gpio_cam2_pn1, _GPIO, 105) \
116#define TEGRA_PIN_GPIO_CAM2_PN1 _GPIO(105) 116 fname(GPIO_CAM3_PN2, gpio_cam3_pn2, _GPIO, 106) \
117#define TEGRA_PIN_GPIO_CAM3_PN2 _GPIO(106) 117 fname(GPIO_CAM4_PN3, gpio_cam4_pn3, _GPIO, 107) \
118#define TEGRA_PIN_GPIO_CAM4_PN3 _GPIO(107) 118 fname(GPIO_CAM5_PN4, gpio_cam5_pn4, _GPIO, 108) \
119#define TEGRA_PIN_GPIO_CAM5_PN4 _GPIO(108) 119 fname(GPIO_CAM6_PN5, gpio_cam6_pn5, _GPIO, 109) \
120#define TEGRA_PIN_GPIO_CAM6_PN5 _GPIO(109) 120 fname(GPIO_CAM7_PN6, gpio_cam7_pn6, _GPIO, 110) \
121#define TEGRA_PIN_GPIO_CAM7_PN6 _GPIO(110) 121 fname(EXTPERIPH1_CLK_PO0, extperiph1_clk_po0, _GPIO, 112) \
122#define TEGRA_PIN_EXTPERIPH1_CLK_PO0 _GPIO(112) 122 fname(EXTPERIPH2_CLK_PO1, extperiph2_clk_po1, _GPIO, 113) \
123#define TEGRA_PIN_EXTPERIPH2_CLK_PO1 _GPIO(113) 123 fname(CAM_I2C_SCL_PO2, cam_i2c_scl_po2, _GPIO, 114) \
124#define TEGRA_PIN_CAM_I2C_SCL_PO2 _GPIO(114) 124 fname(CAM_I2C_SDA_PO3, cam_i2c_sda_po3, _GPIO, 115) \
125#define TEGRA_PIN_CAM_I2C_SDA_PO3 _GPIO(115) 125 fname(DP_AUX_CH0_HPD_PP0, dp_aux_ch0_hpd_pp0, _GPIO, 120) \
126#define TEGRA_PIN_DP_AUX_CH0_HPD_PP0 _GPIO(120) 126 fname(DP_AUX_CH1_HPD_PP1, dp_aux_ch1_hpd_pp1, _GPIO, 121) \
127#define TEGRA_PIN_DP_AUX_CH1_HPD_PP1 _GPIO(121) 127 fname(HDMI_CEC_PP2, hdmi_cec_pp2, _GPIO, 122) \
128#define TEGRA_PIN_HDMI_CEC_PP2 _GPIO(122) 128 fname(GPIO_EDP0_PP3, gpio_edp0_pp3, _GPIO, 123) \
129#define TEGRA_PIN_GPIO_EDP0_PP3 _GPIO(123) 129 fname(GPIO_EDP1_PP4, gpio_edp1_pp4, _GPIO, 124) \
130#define TEGRA_PIN_GPIO_EDP1_PP4 _GPIO(124) 130 fname(GPIO_EDP2_PP5, gpio_edp2_pp5, _GPIO, 125) \
131#define TEGRA_PIN_GPIO_EDP2_PP5 _GPIO(125) 131 fname(GPIO_EDP3_PP6, gpio_edp3_pp6, _GPIO, 126) \
132#define TEGRA_PIN_GPIO_EDP3_PP6 _GPIO(126) 132 fname(DIRECTDC1_CLK_PQ0, directdc1_clk_pq0, _GPIO, 128) \
133#define TEGRA_PIN_DIRECTDC1_CLK_PQ0 _GPIO(128) 133 fname(DIRECTDC1_IN_PQ1, directdc1_in_pq1, _GPIO, 129) \
134#define TEGRA_PIN_DIRECTDC1_IN_PQ1 _GPIO(129) 134 fname(DIRECTDC1_OUT0_PQ2, directdc1_out0_pq2, _GPIO, 130) \
135#define TEGRA_PIN_DIRECTDC1_OUT0_PQ2 _GPIO(130) 135 fname(DIRECTDC1_OUT1_PQ3, directdc1_out1_pq3, _GPIO, 131) \
136#define TEGRA_PIN_DIRECTDC1_OUT1_PQ3 _GPIO(131) 136 fname(DIRECTDC1_OUT2_PQ4, directdc1_out2_pq4, _GPIO, 132) \
137#define TEGRA_PIN_DIRECTDC1_OUT2_PQ4 _GPIO(132) 137 fname(DIRECTDC1_OUT3_PQ5, directdc1_out3_pq5, _GPIO, 133) \
138#define TEGRA_PIN_DIRECTDC1_OUT3_PQ5 _GPIO(133) 138 fname(QSPI_SCK_PR0, qspi_sck_pr0, _GPIO, 136) \
139#define TEGRA_PIN_QSPI_SCK_PR0 _GPIO(136) 139 fname(QSPI_IO0_PR1, qspi_io0_pr1, _GPIO, 137) \
140#define TEGRA_PIN_QSPI_IO0_PR1 _GPIO(137) 140 fname(QSPI_IO1_PR2, qspi_io1_pr2, _GPIO, 138) \
141#define TEGRA_PIN_QSPI_IO1_PR2 _GPIO(138) 141 fname(QSPI_IO2_PR3, qspi_io2_pr3, _GPIO, 139) \
142#define TEGRA_PIN_QSPI_IO2_PR3 _GPIO(139) 142 fname(QSPI_IO3_PR4, qspi_io3_pr4, _GPIO, 140) \
143#define TEGRA_PIN_QSPI_IO3_PR4 _GPIO(140) 143 fname(QSPI_CS_N_PR5, qspi_cs_n_pr5, _GPIO, 141) \
144#define TEGRA_PIN_QSPI_CS_N_PR5 _GPIO(141) 144 fname(PWR_I2C_SCL_PS0, pwr_i2c_scl_ps0, _GPIO, 144) \
145#define TEGRA_PIN_PWR_I2C_SCL_PS0 _GPIO(144) 145 fname(PWR_I2C_SDA_PS1, pwr_i2c_sda_ps1, _GPIO, 145) \
146#define TEGRA_PIN_PWR_I2C_SDA_PS1 _GPIO(145) 146 fname(BATT_OC_PS2, batt_oc_ps2, _GPIO, 146) \
147#define TEGRA_PIN_BATT_OC_PS2 _GPIO(146) 147 fname(SAFE_STATE_PS3, safe_state_ps3, _GPIO, 147) \
148#define TEGRA_PIN_SAFE_STATE_PS3 _GPIO(147) 148 fname(VCOMP_ALERT_PS4, vcomp_alert_ps4, _GPIO, 148) \
149#define TEGRA_PIN_VCOMP_ALERT_PS4 _GPIO(148) 149 fname(UART1_TX_PT0, uart1_tx_pt0, _GPIO, 152) \
150#define TEGRA_PIN_UART1_TX_PT0 _GPIO(152) 150 fname(UART1_RX_PT1, uart1_rx_pt1, _GPIO, 153) \
151#define TEGRA_PIN_UART1_RX_PT1 _GPIO(153) 151 fname(UART1_RTS_PT2, uart1_rts_pt2, _GPIO, 154) \
152#define TEGRA_PIN_UART1_RTS_PT2 _GPIO(154) 152 fname(UART1_CTS_PT3, uart1_cts_pt3, _GPIO, 155) \
153#define TEGRA_PIN_UART1_CTS_PT3 _GPIO(155) 153 fname(GPIO_DIS0_PU0, gpio_dis0_pu0, _GPIO, 160) \
154#define TEGRA_PIN_GPIO_DIS0_PU0 _GPIO(160) 154 fname(GPIO_DIS1_PU1, gpio_dis1_pu1, _GPIO, 161) \
155#define TEGRA_PIN_GPIO_DIS1_PU1 _GPIO(161) 155 fname(GPIO_DIS2_PU2, gpio_dis2_pu2, _GPIO, 162) \
156#define TEGRA_PIN_GPIO_DIS2_PU2 _GPIO(162) 156 fname(GPIO_DIS3_PU3, gpio_dis3_pu3, _GPIO, 163) \
157#define TEGRA_PIN_GPIO_DIS3_PU3 _GPIO(163) 157 fname(GPIO_DIS4_PU4, gpio_dis4_pu4, _GPIO, 164) \
158#define TEGRA_PIN_GPIO_DIS4_PU4 _GPIO(164) 158 fname(GPIO_DIS5_PU5, gpio_dis5_pu5, _GPIO, 165) \
159#define TEGRA_PIN_GPIO_DIS5_PU5 _GPIO(165) 159 fname(GPIO_SEN0_PV0, gpio_sen0_pv0, _GPIO, 168) \
160#define TEGRA_PIN_GPIO_SEN0_PV0 _GPIO(168) 160 fname(GPIO_SEN1_PV1, gpio_sen1_pv1, _GPIO, 169) \
161#define TEGRA_PIN_GPIO_SEN1_PV1 _GPIO(169) 161 fname(GPIO_SEN2_PV2, gpio_sen2_pv2, _GPIO, 170) \
162#define TEGRA_PIN_GPIO_SEN2_PV2 _GPIO(170) 162 fname(GPIO_SEN3_PV3, gpio_sen3_pv3, _GPIO, 171) \
163#define TEGRA_PIN_GPIO_SEN3_PV3 _GPIO(171) 163 fname(GPIO_SEN4_PV4, gpio_sen4_pv4, _GPIO, 172) \
164#define TEGRA_PIN_GPIO_SEN4_PV4 _GPIO(172) 164 fname(GPIO_SEN5_PV5, gpio_sen5_pv5, _GPIO, 173) \
165#define TEGRA_PIN_GPIO_SEN5_PV5 _GPIO(173) 165 fname(GPIO_SEN6_PV6, gpio_sen6_pv6, _GPIO, 174) \
166#define TEGRA_PIN_GPIO_SEN6_PV6 _GPIO(174) 166 fname(GPIO_SEN7_PV7, gpio_sen7_pv7, _GPIO, 175) \
167#define TEGRA_PIN_GPIO_SEN7_PV7 _GPIO(175) 167 fname(GEN8_I2C_SCL_PW0, gen8_i2c_scl_pw0, _GPIO, 176) \
168#define TEGRA_PIN_GEN8_I2C_SCL_PW0 _GPIO(176) 168 fname(GEN8_I2C_SDA_PW1, gen8_i2c_sda_pw1, _GPIO, 177) \
169#define TEGRA_PIN_GEN8_I2C_SDA_PW1 _GPIO(177) 169 fname(UART3_TX_PW2, uart3_tx_pw2, _GPIO, 178) \
170#define TEGRA_PIN_UART3_TX_PW2 _GPIO(178) 170 fname(UART3_RX_PW3, uart3_rx_pw3, _GPIO, 179) \
171#define TEGRA_PIN_UART3_RX_PW3 _GPIO(179) 171 fname(UART3_RTS_PW4, uart3_rts_pw4, _GPIO, 180) \
172#define TEGRA_PIN_UART3_RTS_PW4 _GPIO(180) 172 fname(UART3_CTS_PW5, uart3_cts_pw5, _GPIO, 181) \
173#define TEGRA_PIN_UART3_CTS_PW5 _GPIO(181) 173 fname(UART7_TX_PW6, uart7_tx_pw6, _GPIO, 182) \
174#define TEGRA_PIN_UART7_TX_PW6 _GPIO(182) 174 fname(UART7_RX_PW7, uart7_rx_pw7, _GPIO, 183) \
175#define TEGRA_PIN_UART7_RX_PW7 _GPIO(183) 175 fname(UART2_TX_PX0, uart2_tx_px0, _GPIO, 184) \
176#define TEGRA_PIN_UART2_TX_PX0 _GPIO(184) 176 fname(UART2_RX_PX1, uart2_rx_px1, _GPIO, 185) \
177#define TEGRA_PIN_UART2_RX_PX1 _GPIO(185) 177 fname(UART2_RTS_PX2, uart2_rts_px2, _GPIO, 186) \
178#define TEGRA_PIN_UART2_RTS_PX2 _GPIO(186) 178 fname(UART2_CTS_PX3, uart2_cts_px3, _GPIO, 187) \
179#define TEGRA_PIN_UART2_CTS_PX3 _GPIO(187) 179 fname(UART5_TX_PX4, uart5_tx_px4, _GPIO, 188) \
180#define TEGRA_PIN_UART5_TX_PX4 _GPIO(188) 180 fname(UART5_RX_PX5, uart5_rx_px5, _GPIO, 189) \
181#define TEGRA_PIN_UART5_RX_PX5 _GPIO(189) 181 fname(UART5_RTS_PX6, uart5_rts_px6, _GPIO, 190) \
182#define TEGRA_PIN_UART5_RTS_PX6 _GPIO(190) 182 fname(UART5_CTS_PX7, uart5_cts_px7, _GPIO, 191) \
183#define TEGRA_PIN_UART5_CTS_PX7 _GPIO(191) 183 fname(GPIO_MDM1_PY0, gpio_mdm1_py0, _GPIO, 192) \
184#define TEGRA_PIN_GPIO_MDM1_PY0 _GPIO(192) 184 fname(GPIO_MDM2_PY1, gpio_mdm2_py1, _GPIO, 193) \
185#define TEGRA_PIN_GPIO_MDM2_PY1 _GPIO(193) 185 fname(GPIO_MDM3_PY2, gpio_mdm3_py2, _GPIO, 194) \
186#define TEGRA_PIN_GPIO_MDM3_PY2 _GPIO(194) 186 fname(GPIO_MDM4_PY3, gpio_mdm4_py3, _GPIO, 195) \
187#define TEGRA_PIN_GPIO_MDM4_PY3 _GPIO(195) 187 fname(GPIO_MDM5_PY4, gpio_mdm5_py4, _GPIO, 196) \
188#define TEGRA_PIN_GPIO_MDM5_PY4 _GPIO(196) 188 fname(GPIO_MDM6_PY5, gpio_mdm6_py5, _GPIO, 197) \
189#define TEGRA_PIN_GPIO_MDM6_PY5 _GPIO(197) 189 fname(GPIO_MDM7_PY6, gpio_mdm7_py6, _GPIO, 198) \
190#define TEGRA_PIN_GPIO_MDM7_PY6 _GPIO(198) 190 fname(CAN1_DOUT_PZ0, can1_dout_pz0, _GPIO, 200) \
191#define TEGRA_PIN_CAN1_DOUT_PZ0 _GPIO(200) 191 fname(CAN1_DIN_PZ1, can1_din_pz1, _GPIO, 201) \
192#define TEGRA_PIN_CAN1_DIN_PZ1 _GPIO(201) 192 fname(CAN0_DOUT_PZ2, can0_dout_pz2, _GPIO, 202) \
193#define TEGRA_PIN_CAN0_DOUT_PZ2 _GPIO(202) 193 fname(CAN0_DIN_PZ3, can0_din_pz3, _GPIO, 203) \
194#define TEGRA_PIN_CAN0_DIN_PZ3 _GPIO(203) 194 fname(CAN_GPIO0_PAA0, can_gpio0_paa0, _GPIO, 208) \
195#define TEGRA_PIN_CAN_GPIO0_PAA0 _GPIO(208) 195 fname(CAN_GPIO1_PAA1, can_gpio1_paa1, _GPIO, 209) \
196#define TEGRA_PIN_CAN_GPIO1_PAA1 _GPIO(209) 196 fname(CAN_GPIO2_PAA2, can_gpio2_paa2, _GPIO, 210) \
197#define TEGRA_PIN_CAN_GPIO2_PAA2 _GPIO(210) 197 fname(CAN_GPIO3_PAA3, can_gpio3_paa3, _GPIO, 211) \
198#define TEGRA_PIN_CAN_GPIO3_PAA3 _GPIO(211) 198 fname(CAN_GPIO4_PAA4, can_gpio4_paa4, _GPIO, 212) \
199#define TEGRA_PIN_CAN_GPIO4_PAA4 _GPIO(212) 199 fname(CAN_GPIO5_PAA5, can_gpio5_paa5, _GPIO, 213) \
200#define TEGRA_PIN_CAN_GPIO5_PAA5 _GPIO(213) 200 fname(CAN_GPIO6_PAA6, can_gpio6_paa6, _GPIO, 214) \
201#define TEGRA_PIN_CAN_GPIO6_PAA6 _GPIO(214) 201 fname(CAN_GPIO7_PAA7, can_gpio7_paa7, _GPIO, 215) \
202#define TEGRA_PIN_CAN_GPIO7_PAA7 _GPIO(215) 202 fname(UFS0_REF_CLK_PBB0, ufs0_ref_clk_pbb0, _GPIO, 216) \
203#define TEGRA_PIN_UFS0_REF_CLK_PBB0 _GPIO(216) 203 fname(UFS0_RST_PBB1, ufs0_rst_pbb1, _GPIO, 217) \
204#define TEGRA_PIN_UFS0_RST_PBB1 _GPIO(217) 204 fname(DAP4_SCLK_PCC0, dap4_sclk_pcc0, _GPIO, 224) \
205#define TEGRA_PIN_DAP4_SCLK_PCC0 _GPIO(224) 205 fname(DAP4_DOUT_PCC1, dap4_dout_pcc1, _GPIO, 225) \
206#define TEGRA_PIN_DAP4_DOUT_PCC1 _GPIO(225) 206 fname(DAP4_DIN_PCC2, dap4_din_pcc2, _GPIO, 226) \
207#define TEGRA_PIN_DAP4_DIN_PCC2 _GPIO(226) 207 fname(DAP4_FS_PCC3, dap4_fs_pcc3, _GPIO, 227) \
208#define TEGRA_PIN_DAP4_FS_PCC3 _GPIO(227) 208 fname(GPIO_SEN8_PEE0, gpio_sen8_pee0, _GPIO, 240) \
209#define TEGRA_PIN_GPIO_SEN8_PEE0 _GPIO(240) 209 fname(GPIO_SEN9_PEE1, gpio_sen9_pee1, _GPIO, 241) \
210#define TEGRA_PIN_GPIO_SEN9_PEE1 _GPIO(241) 210 fname(TOUCH_CLK_PEE2, touch_clk_pee2, _GPIO, 242) \
211#define TEGRA_PIN_TOUCH_CLK_PEE2 _GPIO(242) 211 fname(POWER_ON_PFF0, power_on_pff0, _GPIO, 248) \
212#define TEGRA_PIN_POWER_ON_PFF0 _GPIO(248) 212 fname(GPIO_SW1_PFF1, gpio_sw1_pff1, _GPIO, 249) \
213#define TEGRA_PIN_GPIO_SW1_PFF1 _GPIO(249) 213 fname(GPIO_SW2_PFF2, gpio_sw2_pff2, _GPIO, 250) \
214#define TEGRA_PIN_GPIO_SW2_PFF2 _GPIO(250) 214 fname(GPIO_SW3_PFF3, gpio_sw3_pff3, _GPIO, 251) \
215#define TEGRA_PIN_GPIO_SW3_PFF3 _GPIO(251) 215 fname(GPIO_SW4_PFF4, gpio_sw4_pff4, _GPIO, 252) \
216#define TEGRA_PIN_GPIO_SW4_PFF4 _GPIO(252) 216 fname(DIRECTDC_COMP, directdc_comp, _PIN, 0) \
217 217 fname(SDMMC1_COMP, sdmmc1_comp, _PIN, 1) \
218/* All non-GPIO pins follow */ 218 fname(EQOS_COMP, eqos_comp, _PIN, 2) \
219#define NUM_GPIOS (TEGRA_PIN_GPIO_SW4_PFF4 + 1) 219 fname(SDMMC3_COMP, sdmmc3_comp, _PIN, 3) \
220#define _PIN(offset) (NUM_GPIOS + (offset)) 220 fname(QSPI_COMP, qspi_comp, _PIN, 4) \
221 221 fname(SHUTDOWN, shutdown, _PIN, 5) \
222/* Non-GPIO pins */ 222 fname(PMU_INT, pmu_int, _PIN, 6) \
223#define TEGRA_PIN_DIRECTDC_COMP _PIN(0) 223 fname(SOC_PWR_REQ, soc_pwr_req, _PIN, 7) \
224#define TEGRA_PIN_SDMMC1_COMP _PIN(1) 224 fname(CLK_32K_IN, clk_32k_in, _PIN, 8) \
225#define TEGRA_PIN_EQOS_COMP _PIN(2) 225
226#define TEGRA_PIN_SDMMC3_COMP _PIN(3) 226
227#define TEGRA_PIN_QSPI_COMP _PIN(4) 227/**** Output **/
228#define TEGRA_PIN_SHUTDOWN _PIN(5) 228#define _GPIO(offset) (offset)
229#define TEGRA_PIN_PMU_INT _PIN(6) 229#define NUM_GPIOS (TEGRA_PIN_GPIO_SW4_PFF4 + 1)
230#define TEGRA_PIN_SOC_PWR_REQ _PIN(7) 230#define _PIN(offset) (NUM_GPIOS + (offset))
231#define TEGRA_PIN_CLK_32K_IN _PIN(8) 231
232 232/* Define unique ID for each pins */
233#define DRV_BANK 0 233#define TEGRA_PINCTRL_PIN_NUM(id, lid, _f, num) \
234#define MUX_BANK 1 234 TEGRA_PIN_##id = _f(num),
235 235enum pin_id {
236static const struct pinctrl_pin_desc tegra186_pins[] = { 236 T186_PIN_TABLE(TEGRA_PINCTRL_PIN_NUM)
237 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N_PA0"), 237};
238 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N_PA1"), 238
239 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N_PA2"), 239/* Table for pin descriptr */
240 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N_PA3"), 240#define TEGRA_PINCTRL_PIN(id, lid, f, num) PINCTRL_PIN(TEGRA_PIN_##id, #id),
241 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N_PA4"), 241static const struct pinctrl_pin_desc tegra186_pins[] = {
242 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PA5, "PEX_L2_RST_N_PA5"), 242 T186_PIN_TABLE(TEGRA_PINCTRL_PIN)
243 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PA6, "PEX_L2_CLKREQ_N_PA6"), 243};
244 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PB0, "UART4_TX_PB0"), 244
245 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PB1, "UART4_RX_PB1"), 245/* Generate pins array for each pin */
246 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PB2, "UART4_RTS_PB2"), 246#define TEGRA_PINCTRL_PINS_STRUCT(id, lid, f, num) \
247 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PB3, "UART4_CTS_PB3"), 247 static const unsigned lid##_pins[] = { \
248 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN1_PB4, "GPIO_WAN1_PB4"), 248 TEGRA_PIN_##id, \
249 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN2_PB5, "GPIO_WAN2_PB5"), 249 };
250 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN3_PB6, "GPIO_WAN3_PB6"), 250T186_PIN_TABLE(TEGRA_PINCTRL_PINS_STRUCT)
251 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN4_PC0, "GPIO_WAN4_PC0"),
252 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PC1, "DAP2_SCLK_PC1"),
253 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PC2, "DAP2_DOUT_PC2"),
254 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PC3, "DAP2_DIN_PC3"),
255 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PC4, "DAP2_FS_PC4"),
256 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC5, "GEN1_I2C_SCL_PC5"),
257 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC6, "GEN1_I2C_SDA_PC6"),
258 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PD0, "SDMMC1_CLK_PD0"),
259 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PD1, "SDMMC1_CMD_PD1"),
260 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PD2, "SDMMC1_DAT0_PD2"),
261 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PD3, "SDMMC1_DAT1_PD3"),
262 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PD4, "SDMMC1_DAT2_PD4"),
263 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PD5, "SDMMC1_DAT3_PD5"),
264 PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
265 PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
266 PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
267 PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
268 PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
269 PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
270 PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
271 PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
272 PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
273 PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
274 PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
275 PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
276 PINCTRL_PIN(TEGRA_PIN_EQOS_MDIO_PF4, "EQOS_MDIO_PF4"),
277 PINCTRL_PIN(TEGRA_PIN_EQOS_MDC_PF5, "EQOS_MDC_PF5"),
278 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PG0, "SDMMC3_CLK_PG0"),
279 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PG1, "SDMMC3_CMD_PG1"),
280 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PG2, "SDMMC3_DAT0_PG2"),
281 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PG3, "SDMMC3_DAT1_PG3"),
282 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PG4, "SDMMC3_DAT2_PG4"),
283 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PG5, "SDMMC3_DAT3_PG5"),
284 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN5_PH0, "GPIO_WAN5_PH0"),
285 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN6_PH1, "GPIO_WAN6_PH1"),
286 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN7_PH2, "GPIO_WAN7_PH2"),
287 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN8_PH3, "GPIO_WAN8_PH3"),
288 PINCTRL_PIN(TEGRA_PIN_BCPU_PWR_REQ_PH4, "BCPU_PWR_REQ_PH4"),
289 PINCTRL_PIN(TEGRA_PIN_MCPU_PWR_REQ_PH5, "MCPU_PWR_REQ_PH5"),
290 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH6, "GPU_PWR_REQ_PH6"),
291 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ0_PI0, "GPIO_PQ0_PI0"),
292 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ1_PI1, "GPIO_PQ1_PI1"),
293 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ2_PI2, "GPIO_PQ2_PI2"),
294 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ3_PI3, "GPIO_PQ3_PI3"),
295 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ4_PI4, "GPIO_PQ4_PI4"),
296 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ5_PI5, "GPIO_PQ5_PI5"),
297 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ6_PI6, "GPIO_PQ6_PI6"),
298 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ7_PI7, "GPIO_PQ7_PI7"),
299 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PJ0, "DAP1_SCLK_PJ0"),
300 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PJ1, "DAP1_DOUT_PJ1"),
301 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PJ2, "DAP1_DIN_PJ2"),
302 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PJ3, "DAP1_FS_PJ3"),
303 PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PJ4, "AUD_MCLK_PJ4"),
304 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD0_PJ5, "GPIO_AUD0_PJ5"),
305 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD1_PJ6, "GPIO_AUD1_PJ6"),
306 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD2_PJ7, "GPIO_AUD2_PJ7"),
307 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD3_PK0, "GPIO_AUD3_PK0"),
308 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PL0, "GEN7_I2C_SCL_PL0"),
309 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PL1, "GEN7_I2C_SDA_PL1"),
310 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PL2, "GEN9_I2C_SCL_PL2"),
311 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PL3, "GEN9_I2C_SDA_PL3"),
312 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PL4, "USB_VBUS_EN0_PL4"),
313 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PL5, "USB_VBUS_EN1_PL5"),
314 PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PL6, "GP_PWM6_PL6"),
315 PINCTRL_PIN(TEGRA_PIN_GP_PWM7_PL7, "GP_PWM7_PL7"),
316 PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PM0, "DMIC1_DAT_PM0"),
317 PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PM1, "DMIC1_CLK_PM1"),
318 PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PM2, "DMIC2_DAT_PM2"),
319 PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PM3, "DMIC2_CLK_PM3"),
320 PINCTRL_PIN(TEGRA_PIN_DMIC4_DAT_PM4, "DMIC4_DAT_PM4"),
321 PINCTRL_PIN(TEGRA_PIN_DMIC4_CLK_PM5, "DMIC4_CLK_PM5"),
322 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM1_PN0, "GPIO_CAM1_PN0"),
323 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM2_PN1, "GPIO_CAM2_PN1"),
324 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM3_PN2, "GPIO_CAM3_PN2"),
325 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM4_PN3, "GPIO_CAM4_PN3"),
326 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM5_PN4, "GPIO_CAM5_PN4"),
327 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM6_PN5, "GPIO_CAM6_PN5"),
328 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM7_PN6, "GPIO_CAM7_PN6"),
329 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PO0, "EXTPERIPH1_CLK_PO0"),
330 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PO1, "EXTPERIPH2_CLK_PO1"),
331 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PO2, "CAM_I2C_SCL_PO2"),
332 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PO3, "CAM_I2C_SDA_PO3"),
333 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PP0, "DP_AUX_CH0_HPD_PP0"),
334 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PP1, "DP_AUX_CH1_HPD_PP1"),
335 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PP2, "HDMI_CEC_PP2"),
336 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP0_PP3, "GPIO_EDP0_PP3"),
337 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP1_PP4, "GPIO_EDP1_PP4"),
338 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP2_PP5, "GPIO_EDP2_PP5"),
339 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP3_PP6, "GPIO_EDP3_PP6"),
340 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PQ0, "DIRECTDC1_CLK_PQ0"),
341 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PQ1, "DIRECTDC1_IN_PQ1"),
342 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PQ2, "DIRECTDC1_OUT0_PQ2"),
343 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PQ3, "DIRECTDC1_OUT1_PQ3"),
344 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PQ4, "DIRECTDC1_OUT2_PQ4"),
345 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PQ5, "DIRECTDC1_OUT3_PQ5"),
346 PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PR0, "QSPI_SCK_PR0"),
347 PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PR1, "QSPI_IO0_PR1"),
348 PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PR2, "QSPI_IO1_PR2"),
349 PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PR3, "QSPI_IO2_PR3"),
350 PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PR4, "QSPI_IO3_PR4"),
351 PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PR5, "QSPI_CS_N_PR5"),
352 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PS0, "PWR_I2C_SCL_PS0"),
353 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PS1, "PWR_I2C_SDA_PS1"),
354 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PS2, "BATT_OC_PS2"),
355 PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PS3, "SAFE_STATE_PS3"),
356 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PS4, "VCOMP_ALERT_PS4"),
357 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PT0, "UART1_TX_PT0"),
358 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PT1, "UART1_RX_PT1"),
359 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PT2, "UART1_RTS_PT2"),
360 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PT3, "UART1_CTS_PT3"),
361 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS0_PU0, "GPIO_DIS0_PU0"),
362 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS1_PU1, "GPIO_DIS1_PU1"),
363 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS2_PU2, "GPIO_DIS2_PU2"),
364 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS3_PU3, "GPIO_DIS3_PU3"),
365 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS4_PU4, "GPIO_DIS4_PU4"),
366 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS5_PU5, "GPIO_DIS5_PU5"),
367 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN0_PV0, "GPIO_SEN0_PV0"),
368 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN1_PV1, "GPIO_SEN1_PV1"),
369 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN2_PV2, "GPIO_SEN2_PV2"),
370 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN3_PV3, "GPIO_SEN3_PV3"),
371 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN4_PV4, "GPIO_SEN4_PV4"),
372 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN5_PV5, "GPIO_SEN5_PV5"),
373 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN6_PV6, "GPIO_SEN6_PV6"),
374 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN7_PV7, "GPIO_SEN7_PV7"),
375 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PW0, "GEN8_I2C_SCL_PW0"),
376 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PW1, "GEN8_I2C_SDA_PW1"),
377 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PW2, "UART3_TX_PW2"),
378 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PW3, "UART3_RX_PW3"),
379 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PW4, "UART3_RTS_PW4"),
380 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PW5, "UART3_CTS_PW5"),
381 PINCTRL_PIN(TEGRA_PIN_UART7_TX_PW6, "UART7_TX_PW6"),
382 PINCTRL_PIN(TEGRA_PIN_UART7_RX_PW7, "UART7_RX_PW7"),
383 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX0, "UART2_TX_PX0"),
384 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX1, "UART2_RX_PX1"),
385 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX2, "UART2_RTS_PX2"),
386 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX3, "UART2_CTS_PX3"),
387 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PX4, "UART5_TX_PX4"),
388 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PX5, "UART5_RX_PX5"),
389 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PX6, "UART5_RTS_PX6"),
390 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PX7, "UART5_CTS_PX7"),
391 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM1_PY0, "GPIO_MDM1_PY0"),
392 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM2_PY1, "GPIO_MDM2_PY1"),
393 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM3_PY2, "GPIO_MDM3_PY2"),
394 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM4_PY3, "GPIO_MDM4_PY3"),
395 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM5_PY4, "GPIO_MDM5_PY4"),
396 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM6_PY5, "GPIO_MDM6_PY5"),
397 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM7_PY6, "GPIO_MDM7_PY6"),
398 PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PZ0, "CAN1_DOUT_PZ0"),
399 PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PZ1, "CAN1_DIN_PZ1"),
400 PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PZ2, "CAN0_DOUT_PZ2"),
401 PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PZ3, "CAN0_DIN_PZ3"),
402 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO0_PAA0, "CAN_GPIO0_PAA0"),
403 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO1_PAA1, "CAN_GPIO1_PAA1"),
404 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO2_PAA2, "CAN_GPIO2_PAA2"),
405 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO3_PAA3, "CAN_GPIO3_PAA3"),
406 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO4_PAA4, "CAN_GPIO4_PAA4"),
407 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO5_PAA5, "CAN_GPIO5_PAA5"),
408 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO6_PAA6, "CAN_GPIO6_PAA6"),
409 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO7_PAA7, "CAN_GPIO7_PAA7"),
410 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PBB0, "UFS0_REF_CLK_PBB0"),
411 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PBB1, "UFS0_RST_PBB1"),
412 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PCC0, "DAP4_SCLK_PCC0"),
413 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PCC1, "DAP4_DOUT_PCC1"),
414 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PCC2, "DAP4_DIN_PCC2"),
415 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PCC3, "DAP4_FS_PCC3"),
416 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN8_PEE0, "GPIO_SEN8_PEE0"),
417 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN9_PEE1, "GPIO_SEN9_PEE1"),
418 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PEE2, "TOUCH_CLK_PEE2"),
419 PINCTRL_PIN(TEGRA_PIN_POWER_ON_PFF0, "POWER_ON_PFF0"),
420 PINCTRL_PIN(TEGRA_PIN_GPIO_SW1_PFF1, "GPIO_SW1_PFF1"),
421 PINCTRL_PIN(TEGRA_PIN_GPIO_SW2_PFF2, "GPIO_SW2_PFF2"),
422 PINCTRL_PIN(TEGRA_PIN_GPIO_SW3_PFF3, "GPIO_SW3_PFF3"),
423 PINCTRL_PIN(TEGRA_PIN_GPIO_SW4_PFF4, "GPIO_SW4_PFF4"),
424 PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
425 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
426 PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
427 PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
428 PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
429 PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
430 PINCTRL_PIN(TEGRA_PIN_PMU_INT, "PMU_INT"),
431 PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
432 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
433
434};
435
436static const unsigned pex_l0_rst_n_pa0_pins[] = {
437 TEGRA_PIN_PEX_L0_RST_N_PA0,
438};
439
440static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
441 TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
442};
443
444static const unsigned pex_wake_n_pa2_pins[] = {
445 TEGRA_PIN_PEX_WAKE_N_PA2,
446};
447
448static const unsigned pex_l1_rst_n_pa3_pins[] = {
449 TEGRA_PIN_PEX_L1_RST_N_PA3,
450};
451
452static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
453 TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
454};
455
456static const unsigned pex_l2_rst_n_pa5_pins[] = {
457 TEGRA_PIN_PEX_L2_RST_N_PA5,
458};
459
460static const unsigned pex_l2_clkreq_n_pa6_pins[] = {
461 TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
462};
463
464static const unsigned uart4_tx_pb0_pins[] = {
465 TEGRA_PIN_UART4_TX_PB0,
466};
467
468static const unsigned uart4_rx_pb1_pins[] = {
469 TEGRA_PIN_UART4_RX_PB1,
470};
471
472static const unsigned uart4_rts_pb2_pins[] = {
473 TEGRA_PIN_UART4_RTS_PB2,
474};
475
476static const unsigned uart4_cts_pb3_pins[] = {
477 TEGRA_PIN_UART4_CTS_PB3,
478};
479
480static const unsigned gpio_wan1_pb4_pins[] = {
481 TEGRA_PIN_GPIO_WAN1_PB4,
482};
483
484static const unsigned gpio_wan2_pb5_pins[] = {
485 TEGRA_PIN_GPIO_WAN2_PB5,
486};
487
488static const unsigned gpio_wan3_pb6_pins[] = {
489 TEGRA_PIN_GPIO_WAN3_PB6,
490};
491
492static const unsigned gpio_wan4_pc0_pins[] = {
493 TEGRA_PIN_GPIO_WAN4_PC0,
494};
495
496static const unsigned dap2_sclk_pc1_pins[] = {
497 TEGRA_PIN_DAP2_SCLK_PC1,
498};
499
500static const unsigned dap2_dout_pc2_pins[] = {
501 TEGRA_PIN_DAP2_DOUT_PC2,
502};
503
504static const unsigned dap2_din_pc3_pins[] = {
505 TEGRA_PIN_DAP2_DIN_PC3,
506};
507
508static const unsigned dap2_fs_pc4_pins[] = {
509 TEGRA_PIN_DAP2_FS_PC4,
510};
511
512static const unsigned gen1_i2c_scl_pc5_pins[] = {
513 TEGRA_PIN_GEN1_I2C_SCL_PC5,
514};
515
516static const unsigned gen1_i2c_sda_pc6_pins[] = {
517 TEGRA_PIN_GEN1_I2C_SDA_PC6,
518};
519
520static const unsigned sdmmc1_clk_pd0_pins[] = {
521 TEGRA_PIN_SDMMC1_CLK_PD0,
522};
523
524static const unsigned sdmmc1_cmd_pd1_pins[] = {
525 TEGRA_PIN_SDMMC1_CMD_PD1,
526};
527
528static const unsigned sdmmc1_comp_pins[] = {
529 TEGRA_PIN_SDMMC1_COMP,
530};
531
532static const unsigned sdmmc1_dat0_pd2_pins[] = {
533 TEGRA_PIN_SDMMC1_DAT0_PD2,
534};
535
536static const unsigned sdmmc1_dat1_pd3_pins[] = {
537 TEGRA_PIN_SDMMC1_DAT1_PD3,
538};
539
540static const unsigned sdmmc1_dat2_pd4_pins[] = {
541 TEGRA_PIN_SDMMC1_DAT2_PD4,
542};
543
544static const unsigned sdmmc1_dat3_pd5_pins[] = {
545TEGRA_PIN_SDMMC1_DAT3_PD5,
546};
547
548static const unsigned eqos_txc_pe0_pins[] = {
549 TEGRA_PIN_EQOS_TXC_PE0,
550};
551
552static const unsigned eqos_td0_pe1_pins[] = {
553 TEGRA_PIN_EQOS_TD0_PE1,
554};
555
556static const unsigned eqos_td1_pe2_pins[] = {
557 TEGRA_PIN_EQOS_TD1_PE2,
558};
559
560static const unsigned eqos_td2_pe3_pins[] = {
561 TEGRA_PIN_EQOS_TD2_PE3,
562};
563
564static const unsigned eqos_td3_pe4_pins[] = {
565 TEGRA_PIN_EQOS_TD3_PE4,
566};
567
568static const unsigned eqos_tx_ctl_pe5_pins[] = {
569 TEGRA_PIN_EQOS_TX_CTL_PE5,
570};
571
572static const unsigned eqos_rd0_pe6_pins[] = {
573 TEGRA_PIN_EQOS_RD0_PE6,
574};
575
576static const unsigned eqos_rd1_pe7_pins[] = {
577 TEGRA_PIN_EQOS_RD1_PE7,
578};
579
580static const unsigned eqos_rd2_pf0_pins[] = {
581 TEGRA_PIN_EQOS_RD2_PF0,
582};
583
584static const unsigned eqos_rd3_pf1_pins[] = {
585 TEGRA_PIN_EQOS_RD3_PF1,
586};
587
588static const unsigned eqos_rx_ctl_pf2_pins[] = {
589 TEGRA_PIN_EQOS_RX_CTL_PF2,
590};
591
592static const unsigned eqos_rxc_pf3_pins[] = {
593 TEGRA_PIN_EQOS_RXC_PF3,
594};
595
596static const unsigned eqos_mdio_pf4_pins[] = {
597 TEGRA_PIN_EQOS_MDIO_PF4,
598};
599
600static const unsigned eqos_mdc_pf5_pins[] = {
601 TEGRA_PIN_EQOS_MDC_PF5,
602};
603
604static const unsigned eqos_comp_pins[] = {
605 TEGRA_PIN_EQOS_COMP,
606};
607 251
608static const unsigned sdmmc4_clk_pins[] = {}; 252static const unsigned sdmmc4_clk_pins[] = {};
609 253
@@ -627,1555 +271,305 @@ static const unsigned sdmmc4_dat1_pins[] = {};
627 271
628static const unsigned sdmmc4_dat0_pins[] = {}; 272static const unsigned sdmmc4_dat0_pins[] = {};
629 273
630static const unsigned sdmmc3_clk_pg0_pins[] = { 274/* Tables for drive pins */
631 TEGRA_PIN_SDMMC3_CLK_PG0, 275#define T186_DRIVE_PINS(fname) \
632}; 276 fname(TOUCH_CLK_PEE2, touch_clk) \
633 277 fname(UART3_TX_PW2, uart3_tx) \
634static const unsigned sdmmc3_cmd_pg1_pins[] = { 278 fname(UART3_RX_PW3, uart3_rx) \
635 TEGRA_PIN_SDMMC3_CMD_PG1, 279 fname(UART3_RTS_PW4, uart3_rts) \
636}; 280 fname(UART3_CTS_PW5, uart3_cts) \
637 281 fname(GEN8_I2C_SCL_PW0, gen8_i2c_scl) \
638static const unsigned sdmmc3_dat0_pg2_pins[] = { 282 fname(GEN8_I2C_SDA_PW1, gen8_i2c_sda) \
639 TEGRA_PIN_SDMMC3_DAT0_PG2, 283 fname(UART7_TX_PW6, uart7_tx) \
640}; 284 fname(UART7_RX_PW7, uart7_rx) \
641 285 fname(GPIO_SEN0_PV0, gpio_sen0) \
642static const unsigned sdmmc3_comp_pins[] = { 286 fname(GPIO_SEN1_PV1, gpio_sen1) \
643 TEGRA_PIN_SDMMC3_COMP, 287 fname(GPIO_SEN2_PV2, gpio_sen2) \
644}; 288 fname(GPIO_SEN3_PV3, gpio_sen3) \
645 289 fname(GPIO_SEN4_PV4, gpio_sen4) \
646static const unsigned sdmmc3_dat1_pg3_pins[] = { 290 fname(GPIO_SEN5_PV5, gpio_sen5) \
647 TEGRA_PIN_SDMMC3_DAT1_PG3, 291 fname(GPIO_SEN6_PV6, gpio_sen6) \
648}; 292 fname(GPIO_SEN7_PV7, gpio_sen7) \
649 293 fname(GPIO_SEN8_PEE0, gpio_sen8) \
650static const unsigned sdmmc3_dat2_pg4_pins[] = { 294 fname(GPIO_SEN9_PEE1, gpio_sen9) \
651 TEGRA_PIN_SDMMC3_DAT2_PG4, 295 fname(CAN1_DOUT_PZ0, can1_dout) \
652}; 296 fname(CAN1_DIN_PZ1, can1_din) \
653 297 fname(CAN0_DOUT_PZ2, can0_dout) \
654static const unsigned sdmmc3_dat3_pg5_pins[] = { 298 fname(CAN0_DIN_PZ3, can0_din) \
655 TEGRA_PIN_SDMMC3_DAT3_PG5, 299 fname(CAN_GPIO0_PAA0, can_gpio0) \
656}; 300 fname(CAN_GPIO1_PAA1, can_gpio1) \
657 301 fname(CAN_GPIO2_PAA2, can_gpio2) \
658static const unsigned gpio_wan5_ph0_pins[] = { 302 fname(CAN_GPIO3_PAA3, can_gpio3) \
659 TEGRA_PIN_GPIO_WAN5_PH0, 303 fname(CAN_GPIO4_PAA4, can_gpio4) \
660}; 304 fname(CAN_GPIO5_PAA5, can_gpio5) \
661 305 fname(CAN_GPIO6_PAA6, can_gpio6) \
662static const unsigned gpio_wan6_ph1_pins[] = { 306 fname(CAN_GPIO7_PAA7, can_gpio7) \
663 TEGRA_PIN_GPIO_WAN6_PH1, 307 fname(GPIO_AUD0_PJ5, gpio_aud0) \
664}; 308 fname(GPIO_AUD1_PJ6, gpio_aud1) \
665 309 fname(GPIO_AUD2_PJ7, gpio_aud2) \
666static const unsigned gpio_wan7_ph2_pins[] = { 310 fname(GPIO_AUD3_PK0, gpio_aud3) \
667 TEGRA_PIN_GPIO_WAN7_PH2, 311 fname(AUD_MCLK_PJ4, aud_mclk) \
668}; 312 fname(DAP1_SCLK_PJ0, dap1_sclk) \
669 313 fname(DAP1_DOUT_PJ1, dap1_dout) \
670static const unsigned gpio_wan8_ph3_pins[] = { 314 fname(DAP1_DIN_PJ2, dap1_din) \
671 TEGRA_PIN_GPIO_WAN8_PH3, 315 fname(DAP1_FS_PJ3, dap1_fs) \
672}; 316 fname(DMIC1_DAT_PM0, dmic1_dat) \
673 317 fname(DMIC1_CLK_PM1, dmic1_clk) \
674static const unsigned bcpu_pwr_req_ph4_pins[] = { 318 fname(DMIC2_DAT_PM2, dmic2_dat) \
675 TEGRA_PIN_BCPU_PWR_REQ_PH4, 319 fname(DMIC2_CLK_PM3, dmic2_clk) \
676}; 320 fname(DMIC4_DAT_PM4, dmic4_dat) \
677 321 fname(DMIC4_CLK_PM5, dmic4_clk) \
678static const unsigned mcpu_pwr_req_ph5_pins[] = { 322 fname(DAP4_SCLK_PCC0, dap4_sclk) \
679 TEGRA_PIN_MCPU_PWR_REQ_PH5, 323 fname(DAP4_DOUT_PCC1, dap4_dout) \
680}; 324 fname(DAP4_DIN_PCC2, dap4_din) \
681 325 fname(DAP4_FS_PCC3, dap4_fs) \
682static const unsigned gpu_pwr_req_ph6_pins[] = { 326 fname(EXTPERIPH1_CLK_PO0, extperiph1_clk) \
683 TEGRA_PIN_GPU_PWR_REQ_PH6, 327 fname(EXTPERIPH2_CLK_PO1, extperiph2_clk) \
684}; 328 fname(CAM_I2C_SCL_PO2, cam_i2c_scl) \
685 329 fname(CAM_I2C_SDA_PO3, cam_i2c_sda) \
686static const unsigned gpio_pq0_pi0_pins[] = { 330 fname(GPIO_CAM1_PN0, gpio_cam1) \
687 TEGRA_PIN_GPIO_PQ0_PI0, 331 fname(GPIO_CAM2_PN1, gpio_cam2) \
688}; 332 fname(GPIO_CAM3_PN2, gpio_cam3) \
689 333 fname(GPIO_CAM4_PN3, gpio_cam4) \
690static const unsigned gpio_pq1_pi1_pins[] = { 334 fname(GPIO_CAM5_PN4, gpio_cam5) \
691 TEGRA_PIN_GPIO_PQ1_PI1, 335 fname(GPIO_CAM6_PN5, gpio_cam6) \
692}; 336 fname(GPIO_CAM7_PN6, gpio_cam7) \
693 337 fname(DAP2_SCLK_PC1, dap2_sclk) \
694static const unsigned gpio_pq2_pi2_pins[] = { 338 fname(DAP2_DOUT_PC2, dap2_dout) \
695 TEGRA_PIN_GPIO_PQ2_PI2, 339 fname(DAP2_DIN_PC3, dap2_din) \
696}; 340 fname(DAP2_FS_PC4, dap2_fs) \
697 341 fname(UART4_TX_PB0, uart4_tx) \
698static const unsigned gpio_pq3_pi3_pins[] = { 342 fname(UART4_RX_PB1, uart4_rx) \
699 TEGRA_PIN_GPIO_PQ3_PI3, 343 fname(UART4_RTS_PB2, uart4_rts) \
700}; 344 fname(UART4_CTS_PB3, uart4_cts) \
701 345 fname(GPIO_WAN1_PB4, gpio_wan1) \
702static const unsigned gpio_pq4_pi4_pins[] = { 346 fname(GPIO_WAN2_PB5, gpio_wan2) \
703 TEGRA_PIN_GPIO_PQ4_PI4, 347 fname(GPIO_WAN3_PB6, gpio_wan3) \
704}; 348 fname(GPIO_WAN4_PC0, gpio_wan4) \
705 349 fname(GEN1_I2C_SCL_PC5, gen1_i2c_scl) \
706static const unsigned gpio_pq5_pi5_pins[] = { 350 fname(GEN1_I2C_SDA_PC6, gen1_i2c_sda) \
707 TEGRA_PIN_GPIO_PQ5_PI5, 351 fname(UART1_TX_PT0, uart1_tx) \
708}; 352 fname(UART1_RX_PT1, uart1_rx) \
709 353 fname(UART1_RTS_PT2, uart1_rts) \
710static const unsigned gpio_pq6_pi6_pins[] = { 354 fname(UART1_CTS_PT3, uart1_cts) \
711 TEGRA_PIN_GPIO_PQ6_PI6, 355 fname(DIRECTDC1_CLK_PQ0, directdc1_clk) \
712}; 356 fname(DIRECTDC1_IN_PQ1, directdc1_in) \
713 357 fname(DIRECTDC1_OUT0_PQ2, directdc1_out0) \
714static const unsigned gpio_pq7_pi7_pins[] = { 358 fname(DIRECTDC1_OUT1_PQ3, directdc1_out1) \
715 TEGRA_PIN_GPIO_PQ7_PI7, 359 fname(DIRECTDC1_OUT2_PQ4, directdc1_out2) \
716}; 360 fname(DIRECTDC1_OUT3_PQ5, directdc1_out3) \
717 361 fname(GPIO_PQ0_PI0, gpio_pq0) \
718static const unsigned dap1_sclk_pj0_pins[] = { 362 fname(GPIO_PQ1_PI1, gpio_pq1) \
719 TEGRA_PIN_DAP1_SCLK_PJ0, 363 fname(GPIO_PQ2_PI2, gpio_pq2) \
720}; 364 fname(GPIO_PQ3_PI3, gpio_pq3) \
721 365 fname(GPIO_PQ4_PI4, gpio_pq4) \
722static const unsigned dap1_dout_pj1_pins[] = { 366 fname(GPIO_PQ5_PI5, gpio_pq5) \
723 TEGRA_PIN_DAP1_DOUT_PJ1, 367 fname(GPIO_PQ6_PI6, gpio_pq6) \
724}; 368 fname(GPIO_PQ7_PI7, gpio_pq7) \
725 369 fname(GPIO_EDP0_PP3, gpio_edp0) \
726static const unsigned dap1_din_pj2_pins[] = { 370 fname(GPIO_EDP1_PP4, gpio_edp1) \
727 TEGRA_PIN_DAP1_DIN_PJ2, 371 fname(GPIO_EDP2_PP5, gpio_edp2) \
728}; 372 fname(GPIO_EDP3_PP6, gpio_edp3) \
729 373 fname(DP_AUX_CH0_HPD_PP0, dp_aux_ch0_hpd) \
730static const unsigned dap1_fs_pj3_pins[] = { 374 fname(DP_AUX_CH1_HPD_PP1, dp_aux_ch1_hpd) \
731 TEGRA_PIN_DAP1_FS_PJ3, 375 fname(HDMI_CEC_PP2, hdmi_cec) \
732}; 376 fname(PEX_L2_CLKREQ_N_PA6, pex_l2_clkreq_n) \
733 377 fname(PEX_WAKE_N_PA2, pex_wake_n) \
734static const unsigned aud_mclk_pj4_pins[] = { 378 fname(PEX_L1_CLKREQ_N_PA4, pex_l1_clkreq_n) \
735 TEGRA_PIN_AUD_MCLK_PJ4, 379 fname(PEX_L1_RST_N_PA3, pex_l1_rst_n) \
736}; 380 fname(PEX_L0_CLKREQ_N_PA1, pex_l0_clkreq_n) \
737 381 fname(PEX_L0_RST_N_PA0, pex_l0_rst_n) \
738static const unsigned gpio_aud0_pj5_pins[] = { 382 fname(PEX_L2_RST_N_PA5, pex_l2_rst_n) \
739 TEGRA_PIN_GPIO_AUD0_PJ5, 383 fname(SDMMC1_CLK_PD0, sdmmc1_clk) \
740}; 384 fname(SDMMC1_CMD_PD1, sdmmc1_cmd) \
741 385 fname(SDMMC1_DAT3_PD5, sdmmc1_dat3) \
742static const unsigned gpio_aud1_pj6_pins[] = { 386 fname(SDMMC1_DAT2_PD4, sdmmc1_dat2) \
743 TEGRA_PIN_GPIO_AUD1_PJ6, 387 fname(SDMMC1_DAT1_PD3, sdmmc1_dat1) \
744}; 388 fname(SDMMC1_DAT0_PD2, sdmmc1_dat0) \
745 389 fname(EQOS_TD3_PE4, eqos_td3) \
746static const unsigned gpio_aud2_pj7_pins[] = { 390 fname(EQOS_TD2_PE3, eqos_td2) \
747 TEGRA_PIN_GPIO_AUD2_PJ7, 391 fname(EQOS_TD1_PE2, eqos_td1) \
748}; 392 fname(EQOS_TD0_PE1, eqos_td0) \
749 393 fname(EQOS_RD3_PF1, eqos_rd3) \
750static const unsigned gpio_aud3_pk0_pins[] = { 394 fname(EQOS_RD2_PF0, eqos_rd2) \
751 TEGRA_PIN_GPIO_AUD3_PK0, 395 fname(EQOS_RD1_PE7, eqos_rd1) \
752}; 396 fname(EQOS_MDIO_PF4, eqos_mdio) \
753 397 fname(EQOS_RD0_PE6, eqos_rd0) \
754static const unsigned gen7_i2c_scl_pl0_pins[] = { 398 fname(EQOS_MDC_PF5, eqos_mdc) \
755 TEGRA_PIN_GEN7_I2C_SCL_PL0, 399 fname(EQOS_TXC_PE0, eqos_txc) \
756}; 400 fname(EQOS_RXC_PF3, eqos_rxc) \
757 401 fname(EQOS_TX_CTL_PE5, eqos_tx_ctl) \
758static const unsigned gen7_i2c_sda_pl1_pins[] = { 402 fname(EQOS_RX_CTL_PF2, eqos_rx_ctl) \
759 TEGRA_PIN_GEN7_I2C_SDA_PL1, 403 fname(SDMMC3_DAT3_PG5, sdmmc3_dat3) \
760}; 404 fname(SDMMC3_DAT2_PG4, sdmmc3_dat2) \
761 405 fname(SDMMC3_DAT1_PG3, sdmmc3_dat1) \
762static const unsigned gen9_i2c_scl_pl2_pins[] = { 406 fname(SDMMC3_DAT0_PG2, sdmmc3_dat0) \
763 TEGRA_PIN_GEN9_I2C_SCL_PL2, 407 fname(SDMMC3_CMD_PG1, sdmmc3_cmd) \
764}; 408 fname(SDMMC3_CLK_PG0, sdmmc3_clk) \
765 409 fname(QSPI_IO3_PR4, qspi_io3) \
766static const unsigned gen9_i2c_sda_pl3_pins[] = { 410 fname(QSPI_IO2_PR3, qspi_io2) \
767 TEGRA_PIN_GEN9_I2C_SDA_PL3, 411 fname(QSPI_IO1_PR2, qspi_io1) \
768}; 412 fname(QSPI_IO0_PR1, qspi_io0) \
769 413 fname(QSPI_SCK_PR0, qspi_sck) \
770static const unsigned usb_vbus_en0_pl4_pins[] = { 414 fname(QSPI_CS_N_PR5, qspi_cs_n) \
771 TEGRA_PIN_USB_VBUS_EN0_PL4, 415 fname(GPIO_SW1_PFF1, gpio_sw1) \
772}; 416 fname(GPIO_SW2_PFF2, gpio_sw2) \
773 417 fname(GPIO_SW3_PFF3, gpio_sw3) \
774static const unsigned usb_vbus_en1_pl5_pins[] = { 418 fname(GPIO_SW4_PFF4, gpio_sw4) \
775 TEGRA_PIN_USB_VBUS_EN1_PL5, 419 fname(SHUTDOWN, shutdown) \
776}; 420 fname(PMU_INT, pmu_int) \
777 421 fname(SAFE_STATE_PS3, safe_state) \
778static const unsigned gp_pwm6_pl6_pins[] = { 422 fname(VCOMP_ALERT_PS4, vcomp_alert) \
779 TEGRA_PIN_GP_PWM6_PL6, 423 fname(SOC_PWR_REQ, soc_pwr_req) \
780}; 424 fname(BATT_OC_PS2, batt_oc) \
781 425 fname(CLK_32K_IN, clk_32k_in) \
782static const unsigned gp_pwm7_pl7_pins[] = { 426 fname(POWER_ON_PFF0, power_on) \
783 TEGRA_PIN_GP_PWM7_PL7, 427 fname(PWR_I2C_SCL_PS0, pwr_i2c_scl) \
784}; 428 fname(PWR_I2C_SDA_PS1, pwr_i2c_sda) \
785 429 fname(GPIO_DIS0_PU0, gpio_dis0) \
786static const unsigned dmic1_dat_pm0_pins[] = { 430 fname(GPIO_DIS1_PU1, gpio_dis1) \
787 TEGRA_PIN_DMIC1_DAT_PM0, 431 fname(GPIO_DIS2_PU2, gpio_dis2) \
788}; 432 fname(GPIO_DIS3_PU3, gpio_dis3) \
789 433 fname(GPIO_DIS4_PU4, gpio_dis4) \
790static const unsigned dmic1_clk_pm1_pins[] = { 434 fname(GPIO_DIS5_PU5, gpio_dis5) \
791 TEGRA_PIN_DMIC1_CLK_PM1, 435 fname(GPIO_WAN8_PH3, gpio_wan8) \
792}; 436 fname(GPIO_WAN7_PH2, gpio_wan7) \
793 437 fname(GPIO_WAN6_PH1, gpio_wan6) \
794static const unsigned dmic2_dat_pm2_pins[] = { 438 fname(GPIO_WAN5_PH0, gpio_wan5) \
795 TEGRA_PIN_DMIC2_DAT_PM2, 439 fname(UART2_TX_PX0, uart2_tx) \
796}; 440 fname(UART2_RX_PX1, uart2_rx) \
797 441 fname(UART2_RTS_PX2, uart2_rts) \
798static const unsigned dmic2_clk_pm3_pins[] = { 442 fname(UART2_CTS_PX3, uart2_cts) \
799 TEGRA_PIN_DMIC2_CLK_PM3, 443 fname(UART5_RX_PX5, uart5_rx) \
800}; 444 fname(UART5_TX_PX4, uart5_tx) \
801 445 fname(UART5_RTS_PX6, uart5_rts) \
802static const unsigned dmic4_dat_pm4_pins[] = { 446 fname(UART5_CTS_PX7, uart5_cts) \
803 TEGRA_PIN_DMIC4_DAT_PM4, 447 fname(GPIO_MDM1_PY0, gpio_mdm1) \
804}; 448 fname(GPIO_MDM2_PY1, gpio_mdm2) \
805 449 fname(GPIO_MDM3_PY2, gpio_mdm3) \
806static const unsigned dmic4_clk_pm5_pins[] = { 450 fname(GPIO_MDM4_PY3, gpio_mdm4) \
807 TEGRA_PIN_DMIC4_CLK_PM5, 451 fname(GPIO_MDM5_PY4, gpio_mdm5) \
808}; 452 fname(GPIO_MDM6_PY5, gpio_mdm6) \
809 453 fname(GPIO_MDM7_PY6, gpio_mdm7) \
810static const unsigned gpio_cam1_pn0_pins[] = { 454 fname(BCPU_PWR_REQ_PH4, bcpu_pwr_req) \
811 TEGRA_PIN_GPIO_CAM1_PN0, 455 fname(MCPU_PWR_REQ_PH5, mcpu_pwr_req) \
812}; 456 fname(GPU_PWR_REQ_PH6, gpu_pwr_req) \
813 457 fname(GEN7_I2C_SCL_PL0, gen7_i2c_scl) \
814static const unsigned gpio_cam2_pn1_pins[] = { 458 fname(GEN7_I2C_SDA_PL1, gen7_i2c_sda) \
815 TEGRA_PIN_GPIO_CAM2_PN1, 459 fname(GEN9_I2C_SCL_PL2, gen9_i2c_scl) \
816}; 460 fname(GEN9_I2C_SDA_PL3, gen9_i2c_sda) \
817 461 fname(USB_VBUS_EN0_PL4, usb_vbus_en0) \
818static const unsigned gpio_cam3_pn2_pins[] = { 462 fname(USB_VBUS_EN1_PL5, usb_vbus_en1) \
819 TEGRA_PIN_GPIO_CAM3_PN2, 463 fname(GP_PWM7_PL7, gp_pwm7) \
820}; 464 fname(GP_PWM6_PL6, gp_pwm6) \
821 465 fname(UFS0_RST_PBB1, ufs0_rst) \
822static const unsigned gpio_cam4_pn3_pins[] = { 466 fname(UFS0_REF_CLK_PBB0, ufs0_ref_clk)
823 TEGRA_PIN_GPIO_CAM4_PN3, 467
824}; 468#define T186_DRIVE_PINS_STRUCT(_id, _name) \
825 469 static const unsigned drive_##_name##_pins[] = { \
826static const unsigned gpio_cam5_pn4_pins[] = { 470 TEGRA_PIN_##_id, \
827 TEGRA_PIN_GPIO_CAM5_PN4, 471 };
828}; 472
829 473T186_DRIVE_PINS(T186_DRIVE_PINS_STRUCT)
830static const unsigned gpio_cam6_pn5_pins[] = { 474
831 TEGRA_PIN_GPIO_CAM6_PN5, 475#define T186_FUNCTION_TABLE(fname) \
832}; 476 fname(RSVD0, rsvd0) \
833 477 fname(RSVD1, rsvd1) \
834static const unsigned gpio_cam7_pn6_pins[] = { 478 fname(RSVD2, rsvd2) \
835 TEGRA_PIN_GPIO_CAM7_PN6, 479 fname(RSVD3, rsvd3) \
836}; 480 fname(TOUCH, touch) \
837 481 fname(UARTC, uartc) \
838static const unsigned extperiph1_clk_po0_pins[] = { 482 fname(I2C8, i2c8) \
839 TEGRA_PIN_EXTPERIPH1_CLK_PO0, 483 fname(UARTG, uartg) \
840}; 484 fname(SPI2, spi2) \
841 485 fname(GP, gp) \
842static const unsigned extperiph2_clk_po1_pins[] = { 486 fname(DCA, dca) \
843 TEGRA_PIN_EXTPERIPH2_CLK_PO1, 487 fname(WDT, wdt) \
844}; 488 fname(I2C2, i2c2) \
845 489 fname(CAN1, can1) \
846static const unsigned cam_i2c_scl_po2_pins[] = { 490 fname(CAN0, can0) \
847 TEGRA_PIN_CAM_I2C_SCL_PO2, 491 fname(DMIC3, dmic3) \
848}; 492 fname(DMIC5, dmic5) \
849 493 fname(GPIO, gpio) \
850static const unsigned cam_i2c_sda_po3_pins[] = { 494 fname(DSPK1, dspk1) \
851 TEGRA_PIN_CAM_I2C_SDA_PO3, 495 fname(DSPK0, dspk0) \
852}; 496 fname(SPDIF, spdif) \
853 497 fname(AUD, aud) \
854static const unsigned dp_aux_ch0_hpd_pp0_pins[] = { 498 fname(I2S1, i2s1) \
855 TEGRA_PIN_DP_AUX_CH0_HPD_PP0, 499 fname(DMIC1, dmic1) \
856}; 500 fname(DMIC2, dmic2) \
857 501 fname(I2S3, i2s3) \
858static const unsigned dp_aux_ch1_hpd_pp1_pins[] = { 502 fname(DMIC4, dmic4) \
859 TEGRA_PIN_DP_AUX_CH1_HPD_PP1, 503 fname(I2S4, i2s4) \
860}; 504 fname(EXTPERIPH2, extperiph2) \
861 505 fname(EXTPERIPH1, extperiph1) \
862static const unsigned hdmi_cec_pp2_pins[] = { 506 fname(I2C3, i2c3) \
863 TEGRA_PIN_HDMI_CEC_PP2, 507 fname(VGP1, vgp1) \
864}; 508 fname(VGP2, vgp2) \
865 509 fname(VGP3, vgp3) \
866static const unsigned gpio_edp0_pp3_pins[] = { 510 fname(VGP4, vgp4) \
867 TEGRA_PIN_GPIO_EDP0_PP3, 511 fname(VGP5, vgp5) \
868}; 512 fname(VGP6, vgp6) \
869 513 fname(EXTPERIPH3, extperiph3) \
870static const unsigned gpio_edp1_pp4_pins[] = { 514 fname(EXTPERIPH4, extperiph4) \
871 TEGRA_PIN_GPIO_EDP1_PP4, 515 fname(SPI4, spi4) \
872}; 516 fname(I2S2, i2s2) \
873 517 fname(UARTD, uartd) \
874static const unsigned gpio_edp2_pp5_pins[] = { 518 fname(I2C1, i2c1) \
875 TEGRA_PIN_GPIO_EDP2_PP5, 519 fname(UARTA, uarta) \
876}; 520 fname(DIRECTDC1, directdc1) \
877 521 fname(DIRECTDC, directdc) \
878static const unsigned gpio_edp3_pp6_pins[] = { 522 fname(IQC0, iqc0) \
879 TEGRA_PIN_GPIO_EDP3_PP6, 523 fname(IQC1, iqc1) \
880}; 524 fname(I2S6, i2s6) \
881 525 fname(DTV, dtv) \
882static const unsigned directdc1_clk_pq0_pins[] = { 526 fname(UARTF, uartf) \
883 TEGRA_PIN_DIRECTDC1_CLK_PQ0, 527 fname(SDMMC3, sdmmc3) \
884}; 528 fname(SDMMC4, sdmmc4) \
885 529 fname(SDMMC1, sdmmc1) \
886static const unsigned directdc_comp_pins[] = { 530 fname(DP, dp) \
887 TEGRA_PIN_DIRECTDC_COMP, 531 fname(HDMI, hdmi) \
888}; 532 fname(PE2, pe2) \
889 533 fname(SATA, sata) \
890static const unsigned directdc1_in_pq1_pins[] = { 534 fname(PE, pe) \
891 TEGRA_PIN_DIRECTDC1_IN_PQ1, 535 fname(PE1, pe1) \
892}; 536 fname(PE0, pe0) \
893 537 fname(SOC, soc) \
894static const unsigned directdc1_out0_pq2_pins[] = { 538 fname(EQOS, eqos) \
895 TEGRA_PIN_DIRECTDC1_OUT0_PQ2, 539 fname(SDMMC2, sdmmc2) \
896}; 540 fname(QSPI, qspi) \
897 541 fname(SCE, sce) \
898static const unsigned directdc1_out1_pq3_pins[] = { 542 fname(I2C5, i2c5) \
899 TEGRA_PIN_DIRECTDC1_OUT1_PQ3, 543 fname(DISPLAYA, displaya) \
900}; 544 fname(DISPLAYB, displayb) \
901 545 fname(DCC, dcc) \
902static const unsigned directdc1_out2_pq4_pins[] = { 546 fname(DCB, dcb) \
903 TEGRA_PIN_DIRECTDC1_OUT2_PQ4, 547 fname(SPI1, spi1) \
904}; 548 fname(UARTB, uartb) \
905 549 fname(UARTE, uarte) \
906static const unsigned directdc1_out3_pq5_pins[] = { 550 fname(SPI3, spi3) \
907 TEGRA_PIN_DIRECTDC1_OUT3_PQ5, 551 fname(NV, nv) \
908}; 552 fname(CCLA, ccla) \
909 553 fname(I2C7, i2c7) \
910static const unsigned qspi_sck_pr0_pins[] = { 554 fname(I2C9, i2c9) \
911 TEGRA_PIN_QSPI_SCK_PR0, 555 fname(I2S5, i2s5) \
912}; 556 fname(USB, usb) \
913 557 fname(UFS0, ufs0)
914static const unsigned qspi_io0_pr1_pins[] = { 558
915 TEGRA_PIN_QSPI_IO0_PR1, 559/* Define unique ID for each function */
916}; 560#define TEGRA_PIN_FUNCTION_MUX_ENUM(id, lid) \
917 561 TEGRA_MUX_##id,
918static const unsigned qspi_io1_pr2_pins[] = {
919 TEGRA_PIN_QSPI_IO1_PR2,
920};
921
922static const unsigned qspi_io2_pr3_pins[] = {
923 TEGRA_PIN_QSPI_IO2_PR3,
924};
925
926static const unsigned qspi_io3_pr4_pins[] = {
927 TEGRA_PIN_QSPI_IO3_PR4,
928};
929
930static const unsigned qspi_cs_n_pr5_pins[] = {
931 TEGRA_PIN_QSPI_CS_N_PR5,
932};
933
934static const unsigned qspi_comp_pins[] = {
935 TEGRA_PIN_QSPI_COMP,
936};
937
938static const unsigned pwr_i2c_scl_ps0_pins[] = {
939 TEGRA_PIN_PWR_I2C_SCL_PS0,
940};
941
942static const unsigned pwr_i2c_sda_ps1_pins[] = {
943 TEGRA_PIN_PWR_I2C_SDA_PS1,
944};
945
946static const unsigned batt_oc_ps2_pins[] = {
947 TEGRA_PIN_BATT_OC_PS2,
948};
949
950static const unsigned safe_state_ps3_pins[] = {
951 TEGRA_PIN_SAFE_STATE_PS3,
952};
953
954static const unsigned vcomp_alert_ps4_pins[] = {
955 TEGRA_PIN_VCOMP_ALERT_PS4,
956};
957
958static const unsigned soc_pwr_req_pins[] = {
959 TEGRA_PIN_SOC_PWR_REQ,
960};
961
962static const unsigned uart1_tx_pt0_pins[] = {
963 TEGRA_PIN_UART1_TX_PT0,
964};
965
966static const unsigned uart1_rx_pt1_pins[] = {
967 TEGRA_PIN_UART1_RX_PT1,
968};
969
970static const unsigned uart1_rts_pt2_pins[] = {
971 TEGRA_PIN_UART1_RTS_PT2,
972};
973
974static const unsigned uart1_cts_pt3_pins[] = {
975 TEGRA_PIN_UART1_CTS_PT3,
976};
977
978static const unsigned gpio_dis0_pu0_pins[] = {
979 TEGRA_PIN_GPIO_DIS0_PU0,
980};
981
982static const unsigned gpio_dis1_pu1_pins[] = {
983 TEGRA_PIN_GPIO_DIS1_PU1,
984};
985
986static const unsigned gpio_dis2_pu2_pins[] = {
987 TEGRA_PIN_GPIO_DIS2_PU2,
988};
989
990static const unsigned gpio_dis3_pu3_pins[] = {
991 TEGRA_PIN_GPIO_DIS3_PU3,
992};
993
994static const unsigned gpio_dis4_pu4_pins[] = {
995 TEGRA_PIN_GPIO_DIS4_PU4,
996};
997
998static const unsigned gpio_dis5_pu5_pins[] = {
999 TEGRA_PIN_GPIO_DIS5_PU5,
1000};
1001
1002static const unsigned gpio_sen0_pv0_pins[] = {
1003 TEGRA_PIN_GPIO_SEN0_PV0,
1004};
1005
1006static const unsigned gpio_sen1_pv1_pins[] = {
1007 TEGRA_PIN_GPIO_SEN1_PV1,
1008};
1009
1010static const unsigned gpio_sen2_pv2_pins[] = {
1011 TEGRA_PIN_GPIO_SEN2_PV2,
1012};
1013
1014static const unsigned gpio_sen3_pv3_pins[] = {
1015 TEGRA_PIN_GPIO_SEN3_PV3,
1016};
1017
1018static const unsigned gpio_sen4_pv4_pins[] = {
1019 TEGRA_PIN_GPIO_SEN4_PV4,
1020};
1021
1022static const unsigned gpio_sen5_pv5_pins[] = {
1023 TEGRA_PIN_GPIO_SEN5_PV5,
1024};
1025
1026static const unsigned gpio_sen6_pv6_pins[] = {
1027 TEGRA_PIN_GPIO_SEN6_PV6,
1028};
1029
1030static const unsigned gpio_sen7_pv7_pins[] = {
1031 TEGRA_PIN_GPIO_SEN7_PV7,
1032};
1033
1034static const unsigned gen8_i2c_scl_pw0_pins[] = {
1035 TEGRA_PIN_GEN8_I2C_SCL_PW0,
1036};
1037
1038static const unsigned gen8_i2c_sda_pw1_pins[] = {
1039 TEGRA_PIN_GEN8_I2C_SDA_PW1,
1040};
1041
1042static const unsigned uart3_tx_pw2_pins[] = {
1043 TEGRA_PIN_UART3_TX_PW2,
1044};
1045
1046static const unsigned uart3_rx_pw3_pins[] = {
1047 TEGRA_PIN_UART3_RX_PW3,
1048};
1049
1050static const unsigned uart3_rts_pw4_pins[] = {
1051 TEGRA_PIN_UART3_RTS_PW4,
1052};
1053
1054static const unsigned uart3_cts_pw5_pins[] = {
1055 TEGRA_PIN_UART3_CTS_PW5,
1056};
1057
1058static const unsigned uart7_tx_pw6_pins[] = {
1059 TEGRA_PIN_UART7_TX_PW6,
1060};
1061
1062static const unsigned uart7_rx_pw7_pins[] = {
1063 TEGRA_PIN_UART7_RX_PW7,
1064};
1065
1066static const unsigned uart2_tx_px0_pins[] = {
1067 TEGRA_PIN_UART2_TX_PX0,
1068};
1069
1070static const unsigned uart2_rx_px1_pins[] = {
1071 TEGRA_PIN_UART2_RX_PX1,
1072};
1073
1074static const unsigned uart2_rts_px2_pins[] = {
1075 TEGRA_PIN_UART2_RTS_PX2,
1076};
1077
1078static const unsigned uart2_cts_px3_pins[] = {
1079 TEGRA_PIN_UART2_CTS_PX3,
1080};
1081
1082static const unsigned uart5_tx_px4_pins[] = {
1083 TEGRA_PIN_UART5_TX_PX4,
1084};
1085
1086static const unsigned uart5_rx_px5_pins[] = {
1087 TEGRA_PIN_UART5_RX_PX5,
1088};
1089
1090static const unsigned uart5_rts_px6_pins[] = {
1091 TEGRA_PIN_UART5_RTS_PX6,
1092};
1093
1094static const unsigned uart5_cts_px7_pins[] = {
1095 TEGRA_PIN_UART5_CTS_PX7,
1096};
1097
1098static const unsigned gpio_mdm1_py0_pins[] = {
1099 TEGRA_PIN_GPIO_MDM1_PY0,
1100};
1101
1102static const unsigned gpio_mdm2_py1_pins[] = {
1103 TEGRA_PIN_GPIO_MDM2_PY1,
1104};
1105
1106static const unsigned gpio_mdm3_py2_pins[] = {
1107 TEGRA_PIN_GPIO_MDM3_PY2,
1108};
1109
1110static const unsigned gpio_mdm4_py3_pins[] = {
1111 TEGRA_PIN_GPIO_MDM4_PY3,
1112};
1113
1114static const unsigned gpio_mdm5_py4_pins[] = {
1115 TEGRA_PIN_GPIO_MDM5_PY4,
1116};
1117
1118static const unsigned gpio_mdm6_py5_pins[] = {
1119 TEGRA_PIN_GPIO_MDM6_PY5,
1120};
1121
1122static const unsigned gpio_mdm7_py6_pins[] = {
1123 TEGRA_PIN_GPIO_MDM7_PY6,
1124};
1125
1126static const unsigned can1_dout_pz0_pins[] = {
1127 TEGRA_PIN_CAN1_DOUT_PZ0,
1128};
1129
1130static const unsigned can1_din_pz1_pins[] = {
1131 TEGRA_PIN_CAN1_DIN_PZ1,
1132};
1133
1134static const unsigned can0_dout_pz2_pins[] = {
1135 TEGRA_PIN_CAN0_DOUT_PZ2,
1136};
1137
1138static const unsigned can0_din_pz3_pins[] = {
1139 TEGRA_PIN_CAN0_DIN_PZ3,
1140};
1141
1142static const unsigned can_gpio0_paa0_pins[] = {
1143 TEGRA_PIN_CAN_GPIO0_PAA0,
1144};
1145
1146static const unsigned can_gpio1_paa1_pins[] = {
1147 TEGRA_PIN_CAN_GPIO1_PAA1,
1148};
1149
1150static const unsigned can_gpio2_paa2_pins[] = {
1151 TEGRA_PIN_CAN_GPIO2_PAA2,
1152};
1153
1154static const unsigned can_gpio3_paa3_pins[] = {
1155 TEGRA_PIN_CAN_GPIO3_PAA3,
1156};
1157
1158static const unsigned can_gpio4_paa4_pins[] = {
1159 TEGRA_PIN_CAN_GPIO4_PAA4,
1160};
1161
1162static const unsigned can_gpio5_paa5_pins[] = {
1163 TEGRA_PIN_CAN_GPIO5_PAA5,
1164};
1165
1166static const unsigned can_gpio6_paa6_pins[] = {
1167 TEGRA_PIN_CAN_GPIO6_PAA6,
1168};
1169
1170static const unsigned can_gpio7_paa7_pins[] = {
1171 TEGRA_PIN_CAN_GPIO7_PAA7,
1172};
1173
1174static const unsigned ufs0_ref_clk_pbb0_pins[] = {
1175 TEGRA_PIN_UFS0_REF_CLK_PBB0,
1176};
1177
1178static const unsigned ufs0_rst_pbb1_pins[] = {
1179 TEGRA_PIN_UFS0_RST_PBB1,
1180};
1181
1182static const unsigned dap4_sclk_pcc0_pins[] = {
1183 TEGRA_PIN_DAP4_SCLK_PCC0,
1184};
1185
1186static const unsigned dap4_dout_pcc1_pins[] = {
1187 TEGRA_PIN_DAP4_DOUT_PCC1,
1188};
1189
1190static const unsigned dap4_din_pcc2_pins[] = {
1191 TEGRA_PIN_DAP4_DIN_PCC2,
1192};
1193
1194static const unsigned dap4_fs_pcc3_pins[] = {
1195 TEGRA_PIN_DAP4_FS_PCC3,
1196};
1197
1198static const unsigned gpio_sen8_pee0_pins[] = {
1199 TEGRA_PIN_GPIO_SEN8_PEE0,
1200};
1201
1202static const unsigned gpio_sen9_pee1_pins[] = {
1203 TEGRA_PIN_GPIO_SEN9_PEE1,
1204};
1205
1206
1207static const unsigned touch_clk_pee2_pins[] = {
1208 TEGRA_PIN_TOUCH_CLK_PEE2,
1209};
1210
1211static const unsigned power_on_pff0_pins[] = {
1212 TEGRA_PIN_POWER_ON_PFF0,
1213};
1214
1215static const unsigned gpio_sw1_pff1_pins[] = {
1216 TEGRA_PIN_GPIO_SW1_PFF1,
1217};
1218
1219static const unsigned gpio_sw2_pff2_pins[] = {
1220 TEGRA_PIN_GPIO_SW2_PFF2,
1221};
1222
1223static const unsigned gpio_sw3_pff3_pins[] = {
1224 TEGRA_PIN_GPIO_SW3_PFF3,
1225};
1226
1227static const unsigned gpio_sw4_pff4_pins[] = {
1228 TEGRA_PIN_GPIO_SW4_PFF4,
1229};
1230
1231static const unsigned clk_32k_in_pins[] = {
1232 TEGRA_PIN_CLK_32K_IN,
1233};
1234
1235static const unsigned shutdown_pins[] = {
1236 TEGRA_PIN_SHUTDOWN,
1237};
1238
1239static const unsigned pmu_int_pins[] = {
1240 TEGRA_PIN_PMU_INT,
1241};
1242
1243static const unsigned drive_ufs0_rst_pins[] = {
1244 TEGRA_PIN_UFS0_RST_PBB1,
1245};
1246
1247static const unsigned drive_ufs0_ref_clk_pins[] = {
1248 TEGRA_PIN_UFS0_REF_CLK_PBB0,
1249};
1250
1251static const unsigned drive_gpio_wan8_pins[] = {
1252 TEGRA_PIN_GPIO_WAN8_PH3,
1253};
1254
1255static const unsigned drive_gpio_wan7_pins[] = {
1256 TEGRA_PIN_GPIO_WAN7_PH2,
1257};
1258
1259static const unsigned drive_gpio_wan6_pins[] = {
1260 TEGRA_PIN_GPIO_WAN6_PH1,
1261};
1262
1263static const unsigned drive_gpio_wan5_pins[] = {
1264 TEGRA_PIN_GPIO_WAN5_PH0,
1265};
1266
1267static const unsigned drive_uart2_tx_pins[] = {
1268 TEGRA_PIN_UART2_TX_PX0,
1269};
1270
1271static const unsigned drive_uart2_rx_pins[] = {
1272 TEGRA_PIN_UART2_RX_PX1,
1273};
1274
1275static const unsigned drive_uart2_rts_pins[] = {
1276 TEGRA_PIN_UART2_RTS_PX2,
1277};
1278
1279static const unsigned drive_uart2_cts_pins[] = {
1280 TEGRA_PIN_UART2_CTS_PX3,
1281};
1282
1283static const unsigned drive_uart5_rx_pins[] = {
1284 TEGRA_PIN_UART5_RX_PX5,
1285};
1286
1287static const unsigned drive_uart5_tx_pins[] = {
1288 TEGRA_PIN_UART5_TX_PX4,
1289};
1290
1291static const unsigned drive_uart5_rts_pins[] = {
1292 TEGRA_PIN_UART5_RTS_PX6,
1293};
1294
1295static const unsigned drive_uart5_cts_pins[] = {
1296 TEGRA_PIN_UART5_CTS_PX7,
1297};
1298
1299static const unsigned drive_gpio_mdm1_pins[] = {
1300 TEGRA_PIN_GPIO_MDM1_PY0,
1301};
1302
1303static const unsigned drive_gpio_mdm2_pins[] = {
1304 TEGRA_PIN_GPIO_MDM2_PY1,
1305};
1306
1307static const unsigned drive_gpio_mdm3_pins[] = {
1308 TEGRA_PIN_GPIO_MDM3_PY2,
1309};
1310
1311static const unsigned drive_gpio_mdm4_pins[] = {
1312 TEGRA_PIN_GPIO_MDM4_PY3,
1313};
1314
1315static const unsigned drive_gpio_mdm5_pins[] = {
1316 TEGRA_PIN_GPIO_MDM5_PY4,
1317};
1318
1319static const unsigned drive_gpio_mdm6_pins[] = {
1320 TEGRA_PIN_GPIO_MDM6_PY5,
1321};
1322
1323static const unsigned drive_gpio_mdm7_pins[] = {
1324 TEGRA_PIN_GPIO_MDM7_PY6,
1325};
1326
1327static const unsigned drive_bcpu_pwr_req_pins[] = {
1328 TEGRA_PIN_BCPU_PWR_REQ_PH4,
1329};
1330
1331static const unsigned drive_mcpu_pwr_req_pins[] = {
1332 TEGRA_PIN_MCPU_PWR_REQ_PH5,
1333};
1334
1335static const unsigned drive_gpu_pwr_req_pins[] = {
1336 TEGRA_PIN_GPU_PWR_REQ_PH6,
1337};
1338
1339static const unsigned drive_gen7_i2c_scl_pins[] = {
1340 TEGRA_PIN_GEN7_I2C_SCL_PL0,
1341};
1342
1343static const unsigned drive_gen7_i2c_sda_pins[] = {
1344 TEGRA_PIN_GEN7_I2C_SDA_PL1,
1345};
1346
1347static const unsigned drive_gen9_i2c_sda_pins[] = {
1348 TEGRA_PIN_GEN9_I2C_SDA_PL3,
1349};
1350
1351static const unsigned drive_gen9_i2c_scl_pins[] = {
1352 TEGRA_PIN_GEN9_I2C_SCL_PL2,
1353};
1354
1355static const unsigned drive_usb_vbus_en0_pins[] = {
1356 TEGRA_PIN_USB_VBUS_EN0_PL4,
1357};
1358
1359static const unsigned drive_usb_vbus_en1_pins[] = {
1360 TEGRA_PIN_USB_VBUS_EN1_PL5,
1361};
1362
1363static const unsigned drive_gp_pwm7_pins[] = {
1364 TEGRA_PIN_GP_PWM7_PL7,
1365};
1366
1367static const unsigned drive_gp_pwm6_pins[] = {
1368 TEGRA_PIN_GP_PWM6_PL6,
1369};
1370
1371static const unsigned drive_gpio_sw1_pins[] = {
1372 TEGRA_PIN_GPIO_SW1_PFF1,
1373};
1374
1375static const unsigned drive_gpio_sw2_pins[] = {
1376 TEGRA_PIN_GPIO_SW2_PFF2,
1377};
1378
1379static const unsigned drive_gpio_sw3_pins[] = {
1380 TEGRA_PIN_GPIO_SW3_PFF3,
1381};
1382
1383static const unsigned drive_gpio_sw4_pins[] = {
1384 TEGRA_PIN_GPIO_SW4_PFF4,
1385};
1386
1387static const unsigned drive_shutdown_pins[] = {
1388 TEGRA_PIN_SHUTDOWN,
1389};
1390
1391static const unsigned drive_pmu_int_pins[] = {
1392};
1393
1394static const unsigned drive_safe_state_pins[] = {
1395 TEGRA_PIN_SAFE_STATE_PS3,
1396};
1397
1398static const unsigned drive_vcomp_alert_pins[] = {
1399 TEGRA_PIN_VCOMP_ALERT_PS4,
1400};
1401
1402static const unsigned drive_soc_pwr_req_pins[] = {
1403 TEGRA_PIN_SOC_PWR_REQ,
1404};
1405
1406static const unsigned drive_batt_oc_pins[] = {
1407 TEGRA_PIN_BATT_OC_PS2,
1408};
1409
1410static const unsigned drive_clk_32k_in_pins[] = {
1411 TEGRA_PIN_CLK_32K_IN,
1412};
1413
1414static const unsigned drive_power_on_pins[] = {
1415 TEGRA_PIN_POWER_ON_PFF0,
1416};
1417
1418static const unsigned drive_pwr_i2c_scl_pins[] = {
1419 TEGRA_PIN_PWR_I2C_SCL_PS0,
1420};
1421
1422static const unsigned drive_pwr_i2c_sda_pins[] = {
1423 TEGRA_PIN_PWR_I2C_SDA_PS1,
1424};
1425
1426static const unsigned drive_gpio_dis0_pins[] = {
1427 TEGRA_PIN_GPIO_DIS0_PU0,
1428};
1429
1430static const unsigned drive_gpio_dis1_pins[] = {
1431 TEGRA_PIN_GPIO_DIS1_PU1,
1432};
1433
1434static const unsigned drive_gpio_dis2_pins[] = {
1435 TEGRA_PIN_GPIO_DIS2_PU2,
1436};
1437
1438static const unsigned drive_gpio_dis3_pins[] = {
1439 TEGRA_PIN_GPIO_DIS3_PU3,
1440};
1441
1442static const unsigned drive_gpio_dis4_pins[] = {
1443 TEGRA_PIN_GPIO_DIS4_PU4,
1444};
1445
1446static const unsigned drive_gpio_dis5_pins[] = {
1447 TEGRA_PIN_GPIO_DIS5_PU5,
1448};
1449
1450static const unsigned drive_qspi_io3_pins[] = {
1451 TEGRA_PIN_QSPI_IO3_PR4,
1452};
1453
1454static const unsigned drive_qspi_io2_pins[] = {
1455 TEGRA_PIN_QSPI_IO2_PR3,
1456};
1457
1458static const unsigned drive_qspi_io1_pins[] = {
1459 TEGRA_PIN_QSPI_IO1_PR2,
1460};
1461
1462static const unsigned drive_qspi_io0_pins[] = {
1463 TEGRA_PIN_QSPI_IO0_PR1,
1464};
1465
1466static const unsigned drive_qspi_sck_pins[] = {
1467 TEGRA_PIN_QSPI_SCK_PR0,
1468};
1469
1470static const unsigned drive_qspi_cs_n_pins[] = {
1471 TEGRA_PIN_QSPI_CS_N_PR5,
1472};
1473
1474static const unsigned drive_sdmmc3_dat3_pins[] = {
1475 TEGRA_PIN_SDMMC3_DAT3_PG5,
1476};
1477
1478static const unsigned drive_sdmmc3_dat2_pins[] = {
1479 TEGRA_PIN_SDMMC3_DAT2_PG4,
1480};
1481
1482static const unsigned drive_sdmmc3_dat1_pins[] = {
1483 TEGRA_PIN_SDMMC3_DAT1_PG3,
1484};
1485
1486static const unsigned drive_sdmmc3_dat0_pins[] = {
1487 TEGRA_PIN_SDMMC3_DAT0_PG2,
1488};
1489
1490static const unsigned drive_sdmmc3_cmd_pins[] = {
1491 TEGRA_PIN_SDMMC3_CMD_PG1,
1492};
1493
1494static const unsigned drive_sdmmc3_clk_pins[] = {
1495 TEGRA_PIN_SDMMC3_CLK_PG0,
1496};
1497
1498static const unsigned drive_eqos_td3_pins[] = {
1499 TEGRA_PIN_EQOS_TD3_PE4,
1500};
1501
1502static const unsigned drive_eqos_td2_pins[] = {
1503 TEGRA_PIN_EQOS_TD2_PE3,
1504};
1505
1506static const unsigned drive_eqos_td1_pins[] = {
1507 TEGRA_PIN_EQOS_TD1_PE2,
1508};
1509
1510static const unsigned drive_eqos_td0_pins[] = {
1511 TEGRA_PIN_EQOS_TD0_PE1,
1512};
1513
1514static const unsigned drive_eqos_rd3_pins[] = {
1515 TEGRA_PIN_EQOS_RD3_PF1,
1516};
1517
1518static const unsigned drive_eqos_rd2_pins[] = {
1519 TEGRA_PIN_EQOS_RD2_PF0,
1520};
1521
1522static const unsigned drive_eqos_rd1_pins[] = {
1523 TEGRA_PIN_EQOS_RD1_PE7,
1524};
1525
1526static const unsigned drive_eqos_mdio_pins[] = {
1527 TEGRA_PIN_EQOS_MDIO_PF4,
1528};
1529
1530static const unsigned drive_eqos_rd0_pins[] = {
1531 TEGRA_PIN_EQOS_RD0_PE6,
1532};
1533
1534static const unsigned drive_eqos_mdc_pins[] = {
1535 TEGRA_PIN_EQOS_MDC_PF5,
1536};
1537
1538static const unsigned drive_eqos_txc_pins[] = {
1539 TEGRA_PIN_EQOS_TXC_PE0,
1540};
1541
1542static const unsigned drive_eqos_rxc_pins[] = {
1543 TEGRA_PIN_EQOS_RXC_PF3,
1544};
1545
1546static const unsigned drive_eqos_tx_ctl_pins[] = {
1547 TEGRA_PIN_EQOS_TX_CTL_PE5,
1548};
1549
1550static const unsigned drive_eqos_rx_ctl_pins[] = {
1551 TEGRA_PIN_EQOS_RX_CTL_PF2,
1552};
1553
1554static const unsigned drive_sdmmc1_clk_pins[] = {
1555 TEGRA_PIN_SDMMC1_CLK_PD0,
1556};
1557
1558static const unsigned drive_sdmmc1_cmd_pins[] = {
1559 TEGRA_PIN_SDMMC1_CMD_PD1,
1560};
1561
1562static const unsigned drive_sdmmc1_dat3_pins[] = {
1563 TEGRA_PIN_SDMMC1_DAT3_PD5,
1564};
1565
1566static const unsigned drive_sdmmc1_dat2_pins[] = {
1567 TEGRA_PIN_SDMMC1_DAT2_PD4,
1568};
1569
1570static const unsigned drive_sdmmc1_dat1_pins[] = {
1571 TEGRA_PIN_SDMMC1_DAT1_PD3,
1572};
1573
1574static const unsigned drive_sdmmc1_dat0_pins[] = {
1575 TEGRA_PIN_SDMMC1_DAT0_PD2,
1576};
1577
1578static const unsigned drive_pex_l2_clkreq_n_pins[] = {
1579 TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
1580};
1581
1582static const unsigned drive_pex_wake_n_pins[] = {
1583 TEGRA_PIN_PEX_WAKE_N_PA2,
1584};
1585
1586static const unsigned drive_pex_l1_clkreq_n_pins[] = {
1587 TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
1588};
1589
1590static const unsigned drive_pex_l1_rst_n_pins[] = {
1591 TEGRA_PIN_PEX_L1_RST_N_PA3,
1592};
1593
1594static const unsigned drive_pex_l0_clkreq_n_pins[] = {
1595 TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
1596};
1597
1598static const unsigned drive_pex_l0_rst_n_pins[] = {
1599 TEGRA_PIN_PEX_L0_RST_N_PA0,
1600};
1601
1602static const unsigned drive_pex_l2_rst_n_pins[] = {
1603 TEGRA_PIN_PEX_L2_RST_N_PA5,
1604};
1605
1606static const unsigned drive_gpio_edp2_pins[] = {
1607 TEGRA_PIN_GPIO_EDP2_PP5,
1608};
1609
1610static const unsigned drive_gpio_edp3_pins[] = {
1611 TEGRA_PIN_GPIO_EDP3_PP6,
1612};
1613
1614static const unsigned drive_gpio_edp0_pins[] = {
1615 TEGRA_PIN_GPIO_EDP0_PP3,
1616};
1617
1618static const unsigned drive_gpio_edp1_pins[] = {
1619 TEGRA_PIN_GPIO_EDP1_PP4,
1620};
1621
1622static const unsigned drive_dp_aux_ch0_hpd_pins[] = {
1623 TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
1624};
1625
1626static const unsigned drive_dp_aux_ch1_hpd_pins[] = {
1627 TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
1628};
1629
1630static const unsigned drive_hdmi_cec_pins[] = {
1631 TEGRA_PIN_HDMI_CEC_PP2,
1632};
1633
1634static const unsigned drive_gpio_pq0_pins[] = {
1635 TEGRA_PIN_GPIO_PQ0_PI0,
1636};
1637
1638static const unsigned drive_gpio_pq1_pins[] = {
1639 TEGRA_PIN_GPIO_PQ1_PI1,
1640};
1641
1642static const unsigned drive_gpio_pq2_pins[] = {
1643 TEGRA_PIN_GPIO_PQ2_PI2,
1644};
1645
1646static const unsigned drive_gpio_pq3_pins[] = {
1647 TEGRA_PIN_GPIO_PQ3_PI3,
1648};
1649
1650static const unsigned drive_gpio_pq4_pins[] = {
1651 TEGRA_PIN_GPIO_PQ4_PI4,
1652};
1653
1654static const unsigned drive_gpio_pq5_pins[] = {
1655 TEGRA_PIN_GPIO_PQ5_PI5,
1656};
1657
1658static const unsigned drive_gpio_pq6_pins[] = {
1659 TEGRA_PIN_GPIO_PQ6_PI6,
1660};
1661
1662static const unsigned drive_gpio_pq7_pins[] = {
1663 TEGRA_PIN_GPIO_PQ7_PI7,
1664};
1665
1666static const unsigned drive_dap2_din_pins[] = {
1667 TEGRA_PIN_DAP2_DIN_PC3,
1668};
1669
1670static const unsigned drive_dap2_dout_pins[] = {
1671 TEGRA_PIN_DAP2_DOUT_PC2,
1672};
1673
1674static const unsigned drive_dap2_fs_pins[] = {
1675 TEGRA_PIN_DAP2_FS_PC4,
1676};
1677
1678static const unsigned drive_dap2_sclk_pins[] = {
1679 TEGRA_PIN_DAP2_SCLK_PC1,
1680};
1681
1682static const unsigned drive_uart4_cts_pins[] = {
1683 TEGRA_PIN_UART4_CTS_PB3,
1684};
1685
1686static const unsigned drive_uart4_rts_pins[] = {
1687 TEGRA_PIN_UART4_RTS_PB2,
1688};
1689
1690static const unsigned drive_uart4_rx_pins[] = {
1691 TEGRA_PIN_UART4_RX_PB1,
1692};
1693
1694static const unsigned drive_uart4_tx_pins[] = {
1695 TEGRA_PIN_UART4_TX_PB0,
1696};
1697
1698static const unsigned drive_gpio_wan4_pins[] = {
1699 TEGRA_PIN_GPIO_WAN4_PC0,
1700};
1701
1702static const unsigned drive_gpio_wan3_pins[] = {
1703 TEGRA_PIN_GPIO_WAN3_PB6,
1704};
1705
1706static const unsigned drive_gpio_wan2_pins[] = {
1707 TEGRA_PIN_GPIO_WAN2_PB5,
1708};
1709
1710static const unsigned drive_gpio_wan1_pins[] = {
1711 TEGRA_PIN_GPIO_WAN1_PB4,
1712};
1713
1714static const unsigned drive_gen1_i2c_scl_pins[] = {
1715 TEGRA_PIN_GEN1_I2C_SCL_PC5,
1716};
1717
1718static const unsigned drive_gen1_i2c_sda_pins[] = {
1719 TEGRA_PIN_GEN1_I2C_SDA_PC6,
1720};
1721
1722static const unsigned drive_extperiph2_clk_pins[] = {
1723 TEGRA_PIN_EXTPERIPH1_CLK_PO0,
1724};
1725
1726static const unsigned drive_extperiph1_clk_pins[] = {
1727 TEGRA_PIN_EXTPERIPH2_CLK_PO1,
1728};
1729
1730static const unsigned drive_cam_i2c_sda_pins[] = {
1731 TEGRA_PIN_CAM_I2C_SDA_PO3,
1732};
1733
1734static const unsigned drive_cam_i2c_scl_pins[] = {
1735 TEGRA_PIN_CAM_I2C_SCL_PO2,
1736};
1737
1738static const unsigned drive_gpio_cam1_pins[] = {
1739 TEGRA_PIN_GPIO_CAM1_PN0,
1740};
1741
1742static const unsigned drive_gpio_cam2_pins[] = {
1743 TEGRA_PIN_GPIO_CAM2_PN1,
1744};
1745
1746static const unsigned drive_gpio_cam3_pins[] = {
1747 TEGRA_PIN_GPIO_CAM3_PN2,
1748};
1749
1750static const unsigned drive_gpio_cam4_pins[] = {
1751 TEGRA_PIN_GPIO_CAM4_PN3,
1752};
1753
1754static const unsigned drive_gpio_cam5_pins[] = {
1755 TEGRA_PIN_GPIO_CAM5_PN4,
1756};
1757
1758static const unsigned drive_gpio_cam6_pins[] = {
1759 TEGRA_PIN_GPIO_CAM6_PN5,
1760};
1761
1762static const unsigned drive_gpio_cam7_pins[] = {
1763 TEGRA_PIN_GPIO_CAM7_PN6,
1764};
1765
1766static const unsigned drive_dmic1_clk_pins[] = {
1767 TEGRA_PIN_DMIC1_CLK_PM1,
1768};
1769
1770static const unsigned drive_dmic1_dat_pins[] = {
1771 TEGRA_PIN_DMIC1_DAT_PM0,
1772};
1773
1774static const unsigned drive_dmic2_dat_pins[] = {
1775 TEGRA_PIN_DMIC2_DAT_PM2,
1776};
1777
1778static const unsigned drive_dmic2_clk_pins[] = {
1779 TEGRA_PIN_DMIC2_CLK_PM3,
1780};
1781
1782static const unsigned drive_dmic4_dat_pins[] = {
1783 TEGRA_PIN_DMIC4_DAT_PM4,
1784};
1785
1786static const unsigned drive_dmic4_clk_pins[] = {
1787 TEGRA_PIN_DMIC4_CLK_PM5,
1788};
1789
1790static const unsigned drive_dap4_fs_pins[] = {
1791 TEGRA_PIN_DAP4_FS_PCC3,
1792};
1793
1794static const unsigned drive_dap4_din_pins[] = {
1795 TEGRA_PIN_DAP4_DIN_PCC2,
1796};
1797
1798static const unsigned drive_dap4_dout_pins[] = {
1799 TEGRA_PIN_DAP4_DOUT_PCC1,
1800};
1801
1802static const unsigned drive_dap4_sclk_pins[] = {
1803 TEGRA_PIN_DAP4_SCLK_PCC0,
1804};
1805
1806static const unsigned drive_gpio_aud3_pins[] = {
1807 TEGRA_PIN_GPIO_AUD3_PK0,
1808};
1809
1810static const unsigned drive_gpio_aud2_pins[] = {
1811 TEGRA_PIN_GPIO_AUD2_PJ7,
1812};
1813
1814static const unsigned drive_gpio_aud1_pins[] = {
1815 TEGRA_PIN_GPIO_AUD1_PJ6,
1816};
1817
1818static const unsigned drive_gpio_aud0_pins[] = {
1819 TEGRA_PIN_GPIO_AUD0_PJ5,
1820};
1821
1822static const unsigned drive_aud_mclk_pins[] = {
1823 TEGRA_PIN_AUD_MCLK_PJ4,
1824};
1825
1826static const unsigned drive_dap1_fs_pins[] = {
1827 TEGRA_PIN_DAP1_FS_PJ3,
1828};
1829
1830static const unsigned drive_dap1_din_pins[] = {
1831 TEGRA_PIN_DAP1_DIN_PJ2,
1832};
1833
1834static const unsigned drive_dap1_dout_pins[] = {
1835 TEGRA_PIN_DAP1_DOUT_PJ1,
1836};
1837
1838static const unsigned drive_dap1_sclk_pins[] = {
1839 TEGRA_PIN_DAP1_SCLK_PJ0,
1840};
1841
1842static const unsigned drive_touch_clk_pins[] = {
1843 TEGRA_PIN_TOUCH_CLK_PEE2,
1844};
1845
1846static const unsigned drive_uart3_cts_pins[] = {
1847 TEGRA_PIN_UART3_CTS_PW5,
1848};
1849
1850static const unsigned drive_uart3_rts_pins[] = {
1851 TEGRA_PIN_UART3_RTS_PW4,
1852};
1853
1854static const unsigned drive_uart3_rx_pins[] = {
1855 TEGRA_PIN_UART3_RX_PW3,
1856};
1857
1858static const unsigned drive_uart3_tx_pins[] = {
1859 TEGRA_PIN_UART3_TX_PW2,
1860};
1861
1862static const unsigned drive_gen8_i2c_sda_pins[] = {
1863 TEGRA_PIN_GEN8_I2C_SDA_PW1,
1864};
1865
1866static const unsigned drive_gen8_i2c_scl_pins[] = {
1867 TEGRA_PIN_GEN8_I2C_SCL_PW0,
1868};
1869
1870static const unsigned drive_uart7_rx_pins[] = {
1871 TEGRA_PIN_UART7_RX_PW7,
1872};
1873
1874static const unsigned drive_uart7_tx_pins[] = {
1875 TEGRA_PIN_UART7_TX_PW6,
1876};
1877
1878static const unsigned drive_gpio_sen0_pins[] = {
1879 TEGRA_PIN_GPIO_SEN0_PV0,
1880};
1881
1882static const unsigned drive_gpio_sen1_pins[] = {
1883 TEGRA_PIN_GPIO_SEN1_PV1,
1884};
1885
1886static const unsigned drive_gpio_sen2_pins[] = {
1887 TEGRA_PIN_GPIO_SEN2_PV2,
1888};
1889
1890static const unsigned drive_gpio_sen3_pins[] = {
1891 TEGRA_PIN_GPIO_SEN3_PV3,
1892};
1893
1894static const unsigned drive_gpio_sen4_pins[] = {
1895 TEGRA_PIN_GPIO_SEN4_PV4,
1896};
1897
1898static const unsigned drive_gpio_sen5_pins[] = {
1899 TEGRA_PIN_GPIO_SEN5_PV5,
1900};
1901
1902static const unsigned drive_gpio_sen6_pins[] = {
1903 TEGRA_PIN_GPIO_SEN6_PV6,
1904};
1905
1906static const unsigned drive_gpio_sen7_pins[] = {
1907 TEGRA_PIN_GPIO_SEN7_PV7,
1908};
1909
1910static const unsigned drive_gpio_sen8_pins[] = {
1911 TEGRA_PIN_GPIO_SEN8_PEE0,
1912};
1913
1914static const unsigned drive_gpio_sen9_pins[] = {
1915 TEGRA_PIN_GPIO_SEN9_PEE1,
1916};
1917
1918static const unsigned drive_can_gpio7_pins[] = {
1919 TEGRA_PIN_CAN_GPIO7_PAA7,
1920};
1921
1922static const unsigned drive_can1_dout_pins[] = {
1923 TEGRA_PIN_CAN1_DOUT_PZ0,
1924};
1925
1926static const unsigned drive_can1_din_pins[] = {
1927 TEGRA_PIN_CAN1_DIN_PZ1,
1928};
1929
1930static const unsigned drive_can0_dout_pins[] = {
1931 TEGRA_PIN_CAN0_DOUT_PZ2,
1932};
1933
1934static const unsigned drive_can0_din_pins[] = {
1935 TEGRA_PIN_CAN0_DIN_PZ3,
1936};
1937
1938static const unsigned drive_can_gpio0_pins[] = {
1939 TEGRA_PIN_CAN_GPIO0_PAA0,
1940};
1941
1942static const unsigned drive_can_gpio1_pins[] = {
1943 TEGRA_PIN_CAN_GPIO1_PAA1,
1944};
1945
1946static const unsigned drive_can_gpio2_pins[] = {
1947 TEGRA_PIN_CAN_GPIO2_PAA2,
1948};
1949
1950static const unsigned drive_can_gpio3_pins[] = {
1951 TEGRA_PIN_CAN_GPIO3_PAA3,
1952};
1953
1954static const unsigned drive_can_gpio4_pins[] = {
1955 TEGRA_PIN_CAN_GPIO4_PAA4,
1956};
1957
1958static const unsigned drive_can_gpio5_pins[] = {
1959 TEGRA_PIN_CAN_GPIO5_PAA5,
1960};
1961
1962static const unsigned drive_can_gpio6_pins[] = {
1963 TEGRA_PIN_CAN_GPIO6_PAA6,
1964};
1965
1966static const unsigned drive_uart1_cts_pins[] = {
1967 TEGRA_PIN_UART1_CTS_PT3,
1968};
1969
1970static const unsigned drive_uart1_rts_pins[] = {
1971 TEGRA_PIN_UART1_RTS_PT2,
1972};
1973
1974static const unsigned drive_uart1_rx_pins[] = {
1975 TEGRA_PIN_UART1_RX_PT1,
1976};
1977
1978static const unsigned drive_uart1_tx_pins[] = {
1979 TEGRA_PIN_UART1_TX_PT0,
1980};
1981
1982static const unsigned drive_directdc1_out3_pins[] = {
1983 TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
1984};
1985
1986static const unsigned drive_directdc1_out2_pins[] = {
1987 TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
1988};
1989
1990static const unsigned drive_directdc1_out1_pins[] = {
1991 TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
1992};
1993
1994static const unsigned drive_directdc1_out0_pins[] = {
1995 TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
1996};
1997
1998static const unsigned drive_directdc1_clk_pins[] = {
1999 TEGRA_PIN_DIRECTDC1_CLK_PQ0,
2000};
2001
2002static const unsigned drive_directdc1_in_pins[] = {
2003 TEGRA_PIN_DIRECTDC1_IN_PQ1,
2004};
2005
2006enum tegra_mux_dt { 562enum tegra_mux_dt {
2007 TEGRA_MUX_RSVD0, 563 T186_FUNCTION_TABLE(TEGRA_PIN_FUNCTION_MUX_ENUM)
2008 TEGRA_MUX_RSVD1,
2009 TEGRA_MUX_RSVD2,
2010 TEGRA_MUX_RSVD3,
2011 TEGRA_MUX_TOUCH,
2012 TEGRA_MUX_UARTC,
2013 TEGRA_MUX_I2C8,
2014 TEGRA_MUX_UARTG,
2015 TEGRA_MUX_SPI2,
2016 TEGRA_MUX_GP,
2017 TEGRA_MUX_DCA,
2018 TEGRA_MUX_WDT,
2019 TEGRA_MUX_I2C2,
2020 TEGRA_MUX_CAN1,
2021 TEGRA_MUX_CAN0,
2022 TEGRA_MUX_DMIC3,
2023 TEGRA_MUX_DMIC5,
2024 TEGRA_MUX_GPIO,
2025 TEGRA_MUX_DSPK1,
2026 TEGRA_MUX_DSPK0,
2027 TEGRA_MUX_SPDIF,
2028 TEGRA_MUX_AUD,
2029 TEGRA_MUX_I2S1,
2030 TEGRA_MUX_DMIC1,
2031 TEGRA_MUX_DMIC2,
2032 TEGRA_MUX_I2S3,
2033 TEGRA_MUX_DMIC4,
2034 TEGRA_MUX_I2S4,
2035 TEGRA_MUX_EXTPERIPH2,
2036 TEGRA_MUX_EXTPERIPH1,
2037 TEGRA_MUX_I2C3,
2038 TEGRA_MUX_VGP1,
2039 TEGRA_MUX_VGP2,
2040 TEGRA_MUX_VGP3,
2041 TEGRA_MUX_VGP4,
2042 TEGRA_MUX_VGP5,
2043 TEGRA_MUX_VGP6,
2044 TEGRA_MUX_EXTPERIPH3,
2045 TEGRA_MUX_EXTPERIPH4,
2046 TEGRA_MUX_SPI4,
2047 TEGRA_MUX_I2S2,
2048 TEGRA_MUX_UARTD,
2049 TEGRA_MUX_I2C1,
2050 TEGRA_MUX_UARTA,
2051 TEGRA_MUX_DIRECTDC1,
2052 TEGRA_MUX_DIRECTDC,
2053 TEGRA_MUX_IQC0,
2054 TEGRA_MUX_IQC1,
2055 TEGRA_MUX_I2S6,
2056 TEGRA_MUX_DTV,
2057 TEGRA_MUX_UARTF,
2058 TEGRA_MUX_SDMMC3,
2059 TEGRA_MUX_SDMMC4,
2060 TEGRA_MUX_SDMMC1,
2061 TEGRA_MUX_DP,
2062 TEGRA_MUX_HDMI,
2063 TEGRA_MUX_PE2,
2064 TEGRA_MUX_SATA,
2065 TEGRA_MUX_PE,
2066 TEGRA_MUX_PE1,
2067 TEGRA_MUX_PE0,
2068 TEGRA_MUX_SOC,
2069 TEGRA_MUX_EQOS,
2070 TEGRA_MUX_SDMMC2,
2071 TEGRA_MUX_QSPI,
2072 TEGRA_MUX_SCE,
2073 TEGRA_MUX_I2C5,
2074 TEGRA_MUX_DISPLAYA,
2075 TEGRA_MUX_DISPLAYB,
2076 TEGRA_MUX_DCC,
2077 TEGRA_MUX_DCB,
2078 TEGRA_MUX_SPI1,
2079 TEGRA_MUX_UARTB,
2080 TEGRA_MUX_UARTE,
2081 TEGRA_MUX_SPI3,
2082 TEGRA_MUX_NV,
2083 TEGRA_MUX_CCLA,
2084 TEGRA_MUX_I2C7,
2085 TEGRA_MUX_I2C9,
2086 TEGRA_MUX_I2S5,
2087 TEGRA_MUX_USB,
2088 TEGRA_MUX_UFS0,
2089}; 564};
2090 565
2091#define FUNCTION(fname) \ 566/* Make list of each function name */
567#define TEGRA_PIN_FUNCTION(id, lid) \
2092 { \ 568 { \
2093 .name = #fname, \ 569 .name = #lid, \
2094 } \ 570 },
2095
2096static struct tegra_function tegra186_functions[] = { 571static struct tegra_function tegra186_functions[] = {
2097 FUNCTION(rsvd0), 572 T186_FUNCTION_TABLE(TEGRA_PIN_FUNCTION)
2098 FUNCTION(rsvd1),
2099 FUNCTION(rsvd2),
2100 FUNCTION(rsvd3),
2101 FUNCTION(touch),
2102 FUNCTION(uartc),
2103 FUNCTION(i2c8),
2104 FUNCTION(uartg),
2105 FUNCTION(spi2),
2106 FUNCTION(gp),
2107 FUNCTION(dca),
2108 FUNCTION(wdt),
2109 FUNCTION(i2c2),
2110 FUNCTION(can1),
2111 FUNCTION(can0),
2112 FUNCTION(dmic3),
2113 FUNCTION(dmic5),
2114 FUNCTION(gpio),
2115 FUNCTION(dspk1),
2116 FUNCTION(dspk0),
2117 FUNCTION(spdif),
2118 FUNCTION(aud),
2119 FUNCTION(i2s1),
2120 FUNCTION(dmic1),
2121 FUNCTION(dmic2),
2122 FUNCTION(i2s3),
2123 FUNCTION(dmic4),
2124 FUNCTION(i2s4),
2125 FUNCTION(extperiph2),
2126 FUNCTION(extperiph1),
2127 FUNCTION(i2c3),
2128 FUNCTION(vgp1),
2129 FUNCTION(vgp2),
2130 FUNCTION(vgp3),
2131 FUNCTION(vgp4),
2132 FUNCTION(vgp5),
2133 FUNCTION(vgp6),
2134 FUNCTION(extperiph3),
2135 FUNCTION(extperiph4),
2136 FUNCTION(spi4),
2137 FUNCTION(i2s2),
2138 FUNCTION(uartd),
2139 FUNCTION(i2c1),
2140 FUNCTION(uarta),
2141 FUNCTION(directdc1),
2142 FUNCTION(directdc),
2143 FUNCTION(iqc0),
2144 FUNCTION(iqc1),
2145 FUNCTION(i2s6),
2146 FUNCTION(dtv),
2147 FUNCTION(uartf),
2148 FUNCTION(sdmmc3),
2149 FUNCTION(sdmmc4),
2150 FUNCTION(sdmmc1),
2151 FUNCTION(dp),
2152 FUNCTION(hdmi),
2153 FUNCTION(pe2),
2154 FUNCTION(sata),
2155 FUNCTION(pe),
2156 FUNCTION(pe1),
2157 FUNCTION(pe0),
2158 FUNCTION(soc),
2159 FUNCTION(eqos),
2160 FUNCTION(sdmmc2),
2161 FUNCTION(qspi),
2162 FUNCTION(sce),
2163 FUNCTION(i2c5),
2164 FUNCTION(displaya),
2165 FUNCTION(displayb),
2166 FUNCTION(dcc),
2167 FUNCTION(dcb),
2168 FUNCTION(spi1),
2169 FUNCTION(uartb),
2170 FUNCTION(uarte),
2171 FUNCTION(spi3),
2172 FUNCTION(nv),
2173 FUNCTION(ccla),
2174 FUNCTION(i2c7),
2175 FUNCTION(i2c9),
2176 FUNCTION(i2s5),
2177 FUNCTION(usb),
2178 FUNCTION(ufs0),
2179}; 573};
2180 574
2181#define PINGROUP_REG_Y(r) ((r)) 575#define PINGROUP_REG_Y(r) ((r))
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 23:59:16 -0500