phy: tegra: pcie: Enale P2U intr based on DT prop

One of the lane margining test requirements is to disable ASPM states.
P2U registers are not accessible when link is in L1SS state. If driver
enables P2U interrupts, P2U isr cannot read INT status when link is in L1SS.
Enable P2U interrupts based on nvidia,enable-lm DT property to avoid this
issue. Enable nvidia,enable-lm when lane margining test is planned.

bug 200385039

Change-Id: I98b998799aac89809c8debaadbf5baeb27a0a657
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1655840
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 11 insertions, 5 deletions

diff --git a/drivers/phy/phy-tegra-p2u.c b/drivers/phy/phy-tegra-p2u.c
index cfdd4c829..08d3b07de 100644
--- a/drivers/phy/phy-tegra-p2u.c
+++ b/drivers/phy/phy-tegra-p2u.c
@@ -76,6 +76,7 @@ struct tegra_p2u {
         struct work_struct      rx_margin_work;
         u32                     next_state;
         spinlock_t              next_state_lock; /* lock for next_state */
+        bool                    enable_lm;
 };
 
 struct margin_ctrl {
@@ -96,11 +97,13 @@ static int tegra_p2u_power_on(struct phy *x)
         u32 val;
         struct tegra_p2u *phy = phy_get_drvdata(x);
 
-        val = P2U_RX_MARGIN_SW_INT_EN_READINESS |
-              P2U_RX_MARGIN_SW_INT_EN_MARGIN_START |
-              P2U_RX_MARGIN_SW_INT_EN_MARGIN_CHANGE |
-              P2U_RX_MARGIN_SW_INT_EN_MARGIN_STOP;
-        writel(val, phy->base + P2U_RX_MARGIN_SW_INT_EN);
+        if (phy->enable_lm) {
+                val = P2U_RX_MARGIN_SW_INT_EN_READINESS |
+                      P2U_RX_MARGIN_SW_INT_EN_MARGIN_START |
+                      P2U_RX_MARGIN_SW_INT_EN_MARGIN_CHANGE |
+                      P2U_RX_MARGIN_SW_INT_EN_MARGIN_STOP;
+                writel(val, phy->base + P2U_RX_MARGIN_SW_INT_EN);
+        }
 
         val = readl(phy->base + P2U_PERIODIC_EQ_CTRL_GEN3);
         val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
@@ -335,6 +338,9 @@ static int tegra_p2u_probe(struct platform_device *pdev)
         }
         phy->id = val;
 
+        phy->enable_lm = of_property_read_bool(dev->of_node,
+                                               "nvidia,enable-lm");
+
         spin_lock_init(&phy->next_state_lock);
         INIT_WORK(&phy->rx_margin_work, rx_margin_work_fn);