net:eqos: Check power state in thermal and PHY API

Bug 200186948

Change-Id: I5912c22d449f47c709da82b540471b88dc2be487
Signed-off-by: anirban ray <aray@nvidia.com>
Reviewed-on: http://git-master/r/1120502
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Lim <dlim@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>

2 files changed, 79 insertions, 31 deletions

diff --git a/drivers/net/ethernet/nvidia/eqos/init.c b/drivers/net/ethernet/nvidia/eqos/init.c
index 4867dd4aa..86fb73c95 100644
--- a/drivers/net/ethernet/nvidia/eqos/init.c
+++ b/drivers/net/ethernet/nvidia/eqos/init.c
@@ -581,7 +581,11 @@ static int tegra_eqos_max_state(struct thermal_cooling_device *tcd,
                                    unsigned long *state)
 {
         struct eqos_prv_data *pdata = tcd->devdata;
-
+        /*
+         * NOTE: There is no locking here. Therefore any HW manipulation code
+         * added in the future will need to employ concurrency control just
+         * like tegra_eqos_set_state()
+         */
         pr_info("%s state=%d\n", __func__, pdata->therm_state.counter);
         *state = TEGRA_EQOS_THERM_MAX_STATE;
 
@@ -593,6 +597,11 @@ static int tegra_eqos_cur_state(struct thermal_cooling_device *tcd,
 {
         struct eqos_prv_data *pdata = tcd->devdata;
 
+        /*
+         * NOTE: There is no locking here. Therefore any HW manipulation code
+         * added in the future will need to employ concurrency control just
+         * like tegra_eqos_set_state()
+         */
         pr_info("%s state=%d\n", __func__, pdata->therm_state.counter);
         *state = (unsigned long)atomic_read(&pdata->therm_state);
 
@@ -604,6 +613,17 @@ static int tegra_eqos_set_state(struct thermal_cooling_device *tcd,
 {
         struct eqos_prv_data *pdata = tcd->devdata;
         struct hw_if_struct *hw_if = &(pdata->hw_if);
+        int hw_chg_count;
+
+        hw_chg_count = EQOS_HW_CHG_MAX_COUNT;
+        while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs) &&
+            hw_chg_count--)
+                usleep_range(20000, 40000);
+
+        if (pdata->suspended || hw_chg_count == 0) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
+                return -ENODEV;
+        }
 
         pr_info("%s cur state=%d new state=%ld, recalibrating eqos pads\n",
                 __func__, pdata->therm_state.counter, state);
@@ -621,6 +641,8 @@ static int tegra_eqos_set_state(struct thermal_cooling_device *tcd,
         /* read-to-clear error counters */
         hw_if->read_err_counter(pdata, false);
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
+
         return 0;
 }
 
@@ -1247,27 +1269,6 @@ static void eqos_shutdown(struct platform_device *pdev)
         return;
 }
 
-#if 0
-static INT eqos_suspend_late(struct platform_device *pdev, pm_message_t state)
-{
-        pr_err("-->eqos_suspend_late\n");
-        pr_err("Handle the suspend_late\n");
-        pr_err("<--eqos_suspend_late\n");
-
-        return 0;
-}
-
-static INT eqos_resume_early(struct platform_device *pdev)
-{
-        pr_err("-->eqos_resume_early\n");
-        pr_err("Handle the resume_early\n");
-        pr_err("<--eqos_resume_early\n");
-
-        return 0;
-}
-
-#endif
-
 #ifdef CONFIG_PM
 
 /*!
@@ -1289,18 +1290,19 @@ static INT eqos_suspend(struct platform_device *pdev, pm_message_t state)
         struct net_device *dev = platform_get_drvdata(pdev);
         struct eqos_prv_data *pdata = netdev_priv(dev);
 
+        while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs))
+                usleep_range(1000, 2000);
+
         if (pdata->suspended) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
                 pr_err("eqos already suspended\n");
                 return -EINVAL;
         }
-        pdata->suspended = 1;
 
+        pdata->suspended = 1;
         if (netif_running(dev)) {
-                while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs))
-                        usleep_range(1000, 2000);
                 eqos_stop_dev(pdata);
                 pdata->hw_state_flgs |= (1 << HW_STOPPED);
-                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
         }
 
         /* disable clocks */
@@ -1308,6 +1310,8 @@ static INT eqos_suspend(struct platform_device *pdev, pm_message_t state)
         /* disable regulators */
         eqos_regulator_deinit(pdata);
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
+
         return 0;
 }
 
@@ -1330,7 +1334,10 @@ static INT eqos_resume(struct platform_device *pdev)
         struct net_device *dev = platform_get_drvdata(pdev);
         struct eqos_prv_data *pdata = netdev_priv(dev);
 
+        while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs))
+                usleep_range(1000, 2000);
         if (!pdata->suspended) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
                 pr_err("eqos already resumed\n");
                 return -EINVAL;
         }
@@ -1346,6 +1353,8 @@ static INT eqos_resume(struct platform_device *pdev)
         pdata->suspended = 0;
         pdata->hw_state_flgs &= ~(1 << HW_STOPPED);
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
+
         return 0;
 }
 
diff --git a/drivers/net/ethernet/nvidia/eqos/mdio.c b/drivers/net/ethernet/nvidia/eqos/mdio.c
index 3312c6fa7..16835db20 100644
--- a/drivers/net/ethernet/nvidia/eqos/mdio.c
+++ b/drivers/net/ethernet/nvidia/eqos/mdio.c
@@ -30,7 +30,7 @@
  * =========================================================================
  */
 /*
- * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -70,10 +70,19 @@ INT eqos_mdio_read_direct(struct eqos_prv_data *pdata,
 {
         struct hw_if_struct *hw_if = &(pdata->hw_if);
         int phy_reg_read_status;
+        int hw_chg_count;
 
         DBGPR_MDIO("--> eqos_mdio_read_direct\n");
-        if (pdata->suspended)
+
+        hw_chg_count = EQOS_HW_CHG_MAX_COUNT;
+        while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs) &&
+            hw_chg_count--)
+                usleep_range(20000, 40000);
+
+        if (pdata->suspended || hw_chg_count == 0) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
                 return -ENODEV;
+        }
 
         if (hw_if->read_phy_regs) {
                 phy_reg_read_status =
@@ -83,8 +92,8 @@ INT eqos_mdio_read_direct(struct eqos_prv_data *pdata,
                 pr_err("%s: hw_if->read_phy_regs not defined", DEV_NAME);
         }
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
         DBGPR_MDIO("<-- eqos_mdio_read_direct\n");
-
         return phy_reg_read_status;
 }
 
@@ -111,9 +120,17 @@ INT eqos_mdio_write_direct(struct eqos_prv_data *pdata,
 {
         struct hw_if_struct *hw_if = &(pdata->hw_if);
         int phy_reg_write_status;
+        int hw_chg_count;
 
-        if (pdata->suspended)
+        hw_chg_count = EQOS_HW_CHG_MAX_COUNT;
+        while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs) &&
+            hw_chg_count--)
+                usleep_range(20000, 40000);
+
+        if (pdata->suspended || hw_chg_count == 0) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
                 return -ENODEV;
+        }
 
         DBGPR_MDIO("--> eqos_mdio_write_direct\n");
 
@@ -125,8 +142,8 @@ INT eqos_mdio_write_direct(struct eqos_prv_data *pdata,
                 pr_err("%s: hw_if->write_phy_regs not defined", DEV_NAME);
         }
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
         DBGPR_MDIO("<-- eqos_mdio_write_direct\n");
-
         return phy_reg_write_status;
 }
 
@@ -151,10 +168,20 @@ static INT eqos_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
         struct eqos_prv_data *pdata = netdev_priv(dev);
         struct hw_if_struct *hw_if = &(pdata->hw_if);
         int phydata = 0;
+        int hw_chg_count;
 
         DBGPR_MDIO("--> eqos_mdio_read: phyaddr = %d, phyreg = %d\n",
                    phyaddr, phyreg);
 
+        hw_chg_count = EQOS_HW_CHG_MAX_COUNT;
+        if (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs))
+                return -ENODEV;
+
+        if (pdata->suspended) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
+                return -ENODEV;
+        }
+
         if (hw_if->read_phy_regs)
                 hw_if->read_phy_regs(phyaddr, phyreg, &phydata);
         else
@@ -162,6 +189,7 @@ static INT eqos_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
 
         DBGPR_MDIO("<-- eqos_mdio_read: phydata = %#x\n", phydata);
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
         return phydata;
 }
 
@@ -187,8 +215,18 @@ static INT eqos_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
         struct eqos_prv_data *pdata = netdev_priv(dev);
         struct hw_if_struct *hw_if = &(pdata->hw_if);
         INT ret = Y_SUCCESS;
+        int hw_chg_count;
 
         DBGPR_MDIO("--> eqos_mdio_write\n");
+        hw_chg_count = EQOS_HW_CHG_MAX_COUNT;
+        while (test_and_set_bit(HW_CHANGING, &pdata->hw_state_flgs) &&
+            hw_chg_count--)
+                usleep_range(20000, 40000);
+
+        if (pdata->suspended || hw_chg_count == 0) {
+                clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
+                return -ENODEV;
+        }
 
         if (hw_if->write_phy_regs) {
                 hw_if->write_phy_regs(phyaddr, phyreg, phydata);
@@ -199,6 +237,7 @@ static INT eqos_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
 
         DBGPR_MDIO("<-- eqos_mdio_write\n");
 
+        clear_bit(HW_CHANGING, &pdata->hw_state_flgs);
         return ret;
 }