net: eqos: Improve sc7 resume time

Modify phy read/write routines to minimize delays.
Modified wait loops for car reset and mtl reset to
minimize delays.
Instead of hardcoding MDC, it needs to be derived from
axi_cbb.

Bug 200180215

Change-Id: I4d1f5bf95948bd012de11b04acae70c94c8adc2a
Signed-off-by: Dave Lim <dlim@nvidia.com>
Reviewed-on: http://git-master/r/1190510
Reviewed-by: Anirban Ray <aray@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

4 files changed, 127 insertions, 134 deletions

diff --git a/drivers/net/ethernet/nvidia/eqos/dev.c b/drivers/net/ethernet/nvidia/eqos/dev.c
index b2118d06a..2e62ca8b6 100644
--- a/drivers/net/ethernet/nvidia/eqos/dev.c
+++ b/drivers/net/ethernet/nvidia/eqos/dev.c
@@ -2465,63 +2465,54 @@ static INT set_promiscuous_mode(void)
 * \retval -1 Failure
 */
 
-static INT write_phy_regs(INT phy_id, INT phy_reg, INT phy_reg_data)
+static INT mdio_poll(void)
 {
-        ULONG retry_cnt = 1000;
-        ULONG vy_count;
-        volatile ULONG mac_gmiiar;
+        /* half sec timeout */
+        ULONG retry_cnt = (500 * 100);
+        ULONG vy_count = 0;
 
-        /* wait for any previous MII read/write operation to complete */
+        ULONG mac_gmiiar;
 
-        /*Poll Until Poll Condition */
-        vy_count = 0;
-        while (1) {
-                if (vy_count > retry_cnt) {
-                        return -Y_FAILURE;
-                } else {
-                        vy_count++;
-                        mdelay(1);
-                }
+        while (vy_count < retry_cnt) {
                 MAC_GMIIAR_RD(mac_gmiiar);
-                if (GET_VALUE
-                    (mac_gmiiar, MAC_GMIIAR_GB_LPOS, MAC_GMIIAR_GB_HPOS) == 0) {
-                        break;
-                }
+                if (GET_VALUE(mac_gmiiar, MAC_GMIIAR_GB_LPOS,
+                              MAC_GMIIAR_GB_HPOS) == 0)
+                        return Y_SUCCESS;
+                vy_count++;
+                udelay(10);
         }
+        return -Y_FAILURE;
+}
+
+static INT write_phy_regs(INT phy_id, INT phy_reg, INT phy_reg_data,
+                                INT mdc_cr)
+{
+        ULONG mac_gmiiar;
+
+        /* wait for any previous MII read/write operation to complete */
+        if (mdio_poll() == -Y_FAILURE)
+                return -Y_FAILURE;
+
         /* write the data */
         MAC_GMIIDR_GD_WR(phy_reg_data);
+
         /* initiate the MII write operation by updating desired */
         /* phy address/id (0 - 31) */
         /* phy register offset */
         /* CSR Clock Range (20 - 35MHz) */
         /* Select write operation */
         /* set busy bit */
-        MAC_GMIIAR_RD(mac_gmiiar);
-        mac_gmiiar = mac_gmiiar & (ULONG) (0x12);
-        mac_gmiiar =
-            mac_gmiiar | ((phy_id) << 21) | ((phy_reg) << 16) | ((0x2) << 8)
-            | ((0x1) << 2) | ((0x1) << 0);
+        mdc_cr <<= 8;
+        mac_gmiiar = ((phy_id) << 21) | ((phy_reg) << 16) | mdc_cr |
+                        ((0x1) << 2) | ((0x1) << 0);
         MAC_GMIIAR_WR(mac_gmiiar);
 
-        /*DELAY IMPLEMENTATION USING udelay() */
-        udelay(10);
-        /* wait for MII write operation to complete */
+        /* delay some to allow mac to set busy bit */
+        udelay(2);
 
-        /*Poll Until Poll Condition */
-        vy_count = 0;
-        while (1) {
-                if (vy_count > retry_cnt) {
-                        return -Y_FAILURE;
-                } else {
-                        vy_count++;
-                        mdelay(1);
-                }
-                MAC_GMIIAR_RD(mac_gmiiar);
-                if (GET_VALUE
-                    (mac_gmiiar, MAC_GMIIAR_GB_LPOS, MAC_GMIIAR_GB_HPOS) == 0) {
-                        break;
-                }
-        }
+        /* wait for MII write operation to complete */
+        if (mdio_poll() == -Y_FAILURE)
+                return -Y_FAILURE;
 
         return Y_SUCCESS;
 }
@@ -2536,62 +2527,36 @@ static INT write_phy_regs(INT phy_id, INT phy_reg, INT phy_reg_data)
 * \retval -1 Failure
 */
 
-static INT read_phy_regs(INT phy_id, INT phy_reg, INT *phy_reg_data)
+static INT read_phy_regs(INT phy_id, INT phy_reg, INT *phy_reg_data,
+                                INT mdc_cr)
 {
         ULONG retry_cnt = 1000;
         ULONG vy_count;
-        volatile ULONG mac_gmiiar;
+        ULONG mac_gmiiar;
         ULONG mac_gmiidr;
 
         /* wait for any previous MII read/write operation to complete */
+        if (mdio_poll() == -Y_FAILURE)
+                return -Y_FAILURE;
 
-        /*Poll Until Poll Condition */
-        vy_count = 0;
-        while (1) {
-                if (vy_count > retry_cnt) {
-                        return -Y_FAILURE;
-                } else {
-                        vy_count++;
-                        mdelay(1);
-                }
-                MAC_GMIIAR_RD(mac_gmiiar);
-                if (GET_VALUE
-                    (mac_gmiiar, MAC_GMIIAR_GB_LPOS, MAC_GMIIAR_GB_HPOS) == 0) {
-                        break;
-                }
-        }
         /* initiate the MII read operation by updating desired */
         /* phy address/id (0 - 31) */
         /* phy register offset */
         /* CSR Clock Range (20 - 35MHz) */
         /* Select read operation */
         /* set busy bit */
-        MAC_GMIIAR_RD(mac_gmiiar);
-        mac_gmiiar = mac_gmiiar & (ULONG) (0x12);
-        mac_gmiiar =
-            mac_gmiiar | ((phy_id) << 21) | ((phy_reg) << 16) | ((0x2) << 8)
-            | ((0x3) << 2) | ((0x1) << 0);
+        mdc_cr <<= 8;
+        mac_gmiiar = ((phy_id) << 21) | ((phy_reg) << 16) | mdc_cr |
+                        ((0x3) << 2) | ((0x1) << 0);
         MAC_GMIIAR_WR(mac_gmiiar);
 
-        /*DELAY IMPLEMENTATION USING udelay() */
-        udelay(10);
-        /* wait for MII write operation to complete */
+        /* delay some to allow mac to set busy bit */
+        udelay(2);
+
+        /* wait for MII read operation to complete */
+        if (mdio_poll() == -Y_FAILURE)
+                return -Y_FAILURE;
 
-        /*Poll Until Poll Condition */
-        vy_count = 0;
-        while (1) {
-                if (vy_count > retry_cnt) {
-                        return -Y_FAILURE;
-                } else {
-                        vy_count++;
-                        mdelay(1);
-                }
-                MAC_GMIIAR_RD(mac_gmiiar);
-                if (GET_VALUE
-                    (mac_gmiiar, MAC_GMIIAR_GB_LPOS, MAC_GMIIAR_GB_HPOS) == 0) {
-                        break;
-                }
-        }
         /* read the data */
         MAC_GMIIDR_RD(mac_gmiidr);
         *phy_reg_data =
@@ -3322,11 +3287,11 @@ static INT eqos_pad_calibrate(struct eqos_prv_data *pdata)
 
 static INT eqos_car_reset(struct eqos_prv_data *pdata)
 {
-        ULONG retry_cnt = 1000;
-        ULONG vy_count;
-        volatile ULONG dma_bmr;
+        /* one sec timeout */
+        ULONG retry_cnt = (500 * 1000);
+        ULONG vy_count = 0;
 
-        DBGPR("-->eqos_car_reset\n");
+        ULONG dma_bmr;
 
         /* Issue a CAR reset */
         if (!IS_ERR_OR_NULL(pdata->eqos_rst))
@@ -3335,27 +3300,16 @@ static INT eqos_car_reset(struct eqos_prv_data *pdata)
         /* add delay of 10 usec */
         udelay(10);
 
-        /* Poll Until Poll Condition */
-        vy_count = 0;
-        while (1) {
-                if (vy_count > retry_cnt) {
-                        dev_err(&pdata->pdev->dev,
-                                "%s():%d: Timed out polling on DMA_BMR_SWR\n",
-                                __func__, __LINE__);
-                        return -Y_FAILURE;
-                } else {
-                        vy_count++;
-                        mdelay(1);
-                }
+        while (vy_count < retry_cnt) {
                 DMA_BMR_RD(dma_bmr);
-                if (GET_VALUE(dma_bmr, DMA_BMR_SWR_LPOS, DMA_BMR_SWR_HPOS) == 0) {
-                        break;
+                if (GET_VALUE(dma_bmr,
+                        DMA_BMR_SWR_LPOS, DMA_BMR_SWR_HPOS) == 0) {
+                        return Y_SUCCESS;
                 }
+                vy_count++;
+                udelay(10);
         }
-
-        DBGPR("<--eqos_car_reset\n");
-
-        return Y_SUCCESS;
+        return -Y_FAILURE;
 }
 
 /*!
@@ -3540,7 +3494,7 @@ static UINT calculate_per_queue_fifo(ULONG fifo_size, UCHAR queue_count)
 static INT configure_mtl_queue(UINT qinx, struct eqos_prv_data *pdata)
 {
         struct eqos_tx_queue *queue_data = GET_TX_QUEUE_PTR(qinx);
-        ULONG retry_cnt = 1000;
+        ULONG retry_cnt;
         ULONG vy_count;
         volatile ULONG mtl_qtomr;
         UINT p_rx_fifo = EQOS_256, p_tx_fifo = EQOS_256;
@@ -3551,20 +3505,21 @@ static INT configure_mtl_queue(UINT qinx, struct eqos_prv_data *pdata)
         /*Flush Tx Queue */
         MTL_QTOMR_FTQ_WR(qinx, 0x1);
 
-        /*Poll Until Poll Condition */
+        /* half sec timeout */
+        retry_cnt = (500 * 1000);
         vy_count = 0;
-        while (1) {
-                if (vy_count > retry_cnt) {
-                        return -Y_FAILURE;
-                } else {
-                        vy_count++;
-                        mdelay(1);
-                }
+
+        /* add delay of 10 usec */
+        udelay(10);
+
+        while (vy_count < retry_cnt) {
                 MTL_QTOMR_RD(qinx, mtl_qtomr);
                 if (GET_VALUE(mtl_qtomr, MTL_QTOMR_FTQ_LPOS, MTL_QTOMR_FTQ_HPOS)
                     == 0) {
                         break;
                 }
+                vy_count++;
+                udelay(10);
         }
 
         /*Enable Store and Forward mode for TX */
diff --git a/drivers/net/ethernet/nvidia/eqos/init.c b/drivers/net/ethernet/nvidia/eqos/init.c
index 8a312a88d..d95198676 100644
--- a/drivers/net/ethernet/nvidia/eqos/init.c
+++ b/drivers/net/ethernet/nvidia/eqos/init.c
@@ -661,6 +661,35 @@ static int eqos_therm_init(struct eqos_prv_data *pdata)
         return 0;
 }
 
+/* Converts csr clock to MDC clock.
+ * Values come from CR field in MAC_MDIO_Address register
+ */
+static void save_mdc(struct eqos_prv_data *pdata)
+{
+        if (pdata->csr_clock_speed > 250) {
+                pdata->mdc_cr = 5;
+                return;
+        }
+        if (pdata->csr_clock_speed > 150) {
+                pdata->mdc_cr = 4;
+                return;
+        }
+        if (pdata->csr_clock_speed > 100) {
+                pdata->mdc_cr = 1;
+                return;
+        }
+        if (pdata->csr_clock_speed > 60) {
+                pdata->mdc_cr = 0;
+                return;
+        }
+        if (pdata->csr_clock_speed > 35) {
+                pdata->mdc_cr = 3;
+                return;
+        }
+        /* for CSR < 35mhz */
+        pdata->mdc_cr = 2;
+}
+
 /*!
 * \brief API to initialize the device.
 *
@@ -934,19 +963,6 @@ int eqos_probe(struct platform_device *pdev)
                 pchinfo->int_mask |= VIRT_INTR_CH_CRTL_TX_WR_MASK;
         }
 
-        pdata->interface = eqos_get_phy_interface(pdata);
-        /* Bypass PHYLIB for TBI, RTBI and SGMII interface */
-        if (1 == pdata->hw_feat.sma_sel) {
-                ret = eqos_mdio_register(ndev);
-                if (ret < 0) {
-                        pr_err("MDIO bus (id %d) registration failed\n",
-                               pdata->bus_id);
-                        goto err_out_mdio_reg;
-                }
-        } else {
-                pr_err("%s: MDIO is not present\n\n", DEV_NAME);
-        }
-
         /* csr_clock_speed is axi_cbb_clk rate */
         pdata->csr_clock_speed = clk_get_rate(pdata->axi_cbb_clk) / 1000000;
         if (pdata->csr_clock_speed <= 0) {
@@ -956,6 +972,7 @@ int eqos_probe(struct platform_device *pdev)
                         pdata->csr_clock_speed);
                         MAC_1US_TIC_WR(pdata->csr_clock_speed - 1);
         }
+        save_mdc(pdata);
 
         ret = eqos_get_mac_address_dtb("/chosen", "nvidia,ether-mac", mac_addr);
         if (ret < 0) {
@@ -972,6 +989,19 @@ int eqos_probe(struct platform_device *pdev)
                 ndev->dev_addr[4] = mac_addr[4];
                 ndev->dev_addr[5] = mac_addr[5];
         }
+        pdata->interface = eqos_get_phy_interface(pdata);
+        /* Bypass PHYLIB for TBI, RTBI and SGMII interface */
+        if (1 == pdata->hw_feat.sma_sel) {
+                ret = eqos_mdio_register(ndev);
+                if (ret < 0) {
+                        pr_err("MDIO bus (id %d) registration failed\n",
+                               pdata->bus_id);
+                        goto err_out_mdio_reg;
+                }
+        } else {
+                pr_err("%s: MDIO is not present\n\n", DEV_NAME);
+        }
+
         /* enabling and registration of irq with magic wakeup */
         if (1 == pdata->hw_feat.mgk_sel) {
                 device_set_wakeup_capable(&pdev->dev, 1);
diff --git a/drivers/net/ethernet/nvidia/eqos/mdio.c b/drivers/net/ethernet/nvidia/eqos/mdio.c
index cf0e75c3e..3fe78ab40 100644
--- a/drivers/net/ethernet/nvidia/eqos/mdio.c
+++ b/drivers/net/ethernet/nvidia/eqos/mdio.c
@@ -77,7 +77,8 @@ INT eqos_mdio_read_direct(struct eqos_prv_data *pdata,
 
         if (hw_if->read_phy_regs) {
                 phy_reg_read_status =
-                    hw_if->read_phy_regs(phyaddr, phyreg, phydata);
+                    hw_if->read_phy_regs(phyaddr, phyreg, phydata,
+                        pdata->mdc_cr);
         } else {
                 phy_reg_read_status = 1;
                 pr_err("%s: hw_if->read_phy_regs not defined", DEV_NAME);
@@ -119,7 +120,8 @@ INT eqos_mdio_write_direct(struct eqos_prv_data *pdata,
 
         if (hw_if->write_phy_regs) {
                 phy_reg_write_status =
-                    hw_if->write_phy_regs(phyaddr, phyreg, phydata);
+                    hw_if->write_phy_regs(phyaddr, phyreg,
+                        phydata, pdata->mdc_cr);
         } else {
                 phy_reg_write_status = 1;
                 pr_err("%s: hw_if->write_phy_regs not defined", DEV_NAME);
@@ -156,7 +158,8 @@ static INT eqos_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
                    phyaddr, phyreg);
 
         if (hw_if->read_phy_regs)
-                hw_if->read_phy_regs(phyaddr, phyreg, &phydata);
+                hw_if->read_phy_regs(phyaddr, phyreg, &phydata,
+                        pdata->mdc_cr);
         else
                 pr_err("%s: hw_if->read_phy_regs not defined", DEV_NAME);
 
@@ -191,7 +194,8 @@ static INT eqos_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
         DBGPR_MDIO("--> eqos_mdio_write\n");
 
         if (hw_if->write_phy_regs) {
-                hw_if->write_phy_regs(phyaddr, phyreg, phydata);
+                hw_if->write_phy_regs(phyaddr, phyreg, phydata,
+                        pdata->mdc_cr);
         } else {
                 ret = -1;
                 pr_err("%s: hw_if->write_phy_regs not defined", DEV_NAME);
@@ -222,18 +226,21 @@ static INT eqos_mdio_reset(struct mii_bus *bus)
 
         DBGPR_MDIO("-->eqos_mdio_reset: phyaddr : %d\n", pdata->phyaddr);
 
-        hw_if->read_phy_regs(pdata->phyaddr, MII_BMCR, &phydata);
+        hw_if->read_phy_regs(pdata->phyaddr, MII_BMCR, &phydata,
+                pdata->mdc_cr);
 
         if (phydata < 0)
                 return 0;
 
         /* issue soft reset to PHY */
         phydata |= BMCR_RESET;
-        hw_if->write_phy_regs(pdata->phyaddr, MII_BMCR, phydata);
+        hw_if->write_phy_regs(pdata->phyaddr, MII_BMCR, phydata,
+                pdata->mdc_cr);
 
         /* wait until software reset completes */
         do {
-                hw_if->read_phy_regs(pdata->phyaddr, MII_BMCR, &phydata);
+                hw_if->read_phy_regs(pdata->phyaddr, MII_BMCR, &phydata,
+                        pdata->mdc_cr);
         } while ((phydata >= 0) && (phydata & BMCR_RESET));
 
         DBGPR_MDIO("<--eqos_mdio_reset\n");
diff --git a/drivers/net/ethernet/nvidia/eqos/yheader.h b/drivers/net/ethernet/nvidia/eqos/yheader.h
index bc1cb7823..821e8bfdc 100644
--- a/drivers/net/ethernet/nvidia/eqos/yheader.h
+++ b/drivers/net/ethernet/nvidia/eqos/yheader.h
@@ -724,8 +724,8 @@ struct hw_if_struct {
         INT(*disable_rx_csum) (void);
         INT(*get_rx_csum_status) (void);
 
-        INT(*read_phy_regs) (INT, INT, INT*);
-        INT(*write_phy_regs) (INT, INT, INT);
+        INT(*read_phy_regs) (INT, INT, INT*, INT);
+        INT(*write_phy_regs) (INT, INT, INT, INT);
         INT(*set_full_duplex) (VOID);
         INT(*set_half_duplex) (VOID);
         INT(*set_mii_speed_100) (struct eqos_prv_data *);
@@ -1538,6 +1538,7 @@ struct eqos_prv_data {
         int tcp_pkt;
 
         u32 csr_clock_speed;
+        u32 mdc_cr;
 
         struct workqueue_struct *fbe_wq;
         struct work_struct fbe_work;