diff options
| author | hayeswang <hayeswang@realtek.com> | 2014-02-18 08:49:04 -0500 |
|---|---|---|
| committer | Vladislav Zhurba <vzhurba@nvidia.com> | 2018-02-01 16:57:59 -0500 |
| commit | 51a17b917f628007441c77291a248c416755c0b7 (patch) | |
| tree | eb4f61b5d63c0a5b1102514c10c342f64017a24b /drivers/net/usb | |
| parent | 5fd359ff53e9795097cc4e6fe08fd5ee31dc0835 (diff) | |
r8152: combine PHY reset with set_speed
PHY reset is necessary after some hw settings. However, it would
cause the linking down, and so does the set_speed function. Combine
the PHY reset with set_speed function. That could reduce the frequency
of linking down and accessing the PHY register.
Signed-off-by: Hayes Wang <hayeswang@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
(cherry picked from commit aa66a5f1af163b6c90fca5a06c7fdab121b70cd2)
Change-Id: I51c55d1baa42df4a4474053291884813fae213c7
Reviewed-on: http://git-master/r/370020
Tested-by: Aly Hirani <ahirani@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'drivers/net/usb')
| -rw-r--r-- | drivers/net/usb/r8152_shield.c | 57 |
1 files changed, 45 insertions, 12 deletions
diff --git a/drivers/net/usb/r8152_shield.c b/drivers/net/usb/r8152_shield.c index 4c5c81ea3..a22171f4f 100644 --- a/drivers/net/usb/r8152_shield.c +++ b/drivers/net/usb/r8152_shield.c | |||
| @@ -437,6 +437,7 @@ enum rtl8152_flags { | |||
| 437 | RTL8152_SET_RX_MODE, | 437 | RTL8152_SET_RX_MODE, |
| 438 | WORK_ENABLE, | 438 | WORK_ENABLE, |
| 439 | RTL8152_LINK_CHG, | 439 | RTL8152_LINK_CHG, |
| 440 | PHY_RESET, | ||
| 440 | }; | 441 | }; |
| 441 | 442 | ||
| 442 | /* Define these values to match your device */ | 443 | /* Define these values to match your device */ |
| @@ -1794,6 +1795,29 @@ static void r8152_power_cut_en(struct r8152 *tp, bool enable) | |||
| 1794 | 1795 | ||
| 1795 | } | 1796 | } |
| 1796 | 1797 | ||
| 1798 | static void rtl_phy_reset(struct r8152 *tp) | ||
| 1799 | { | ||
| 1800 | u16 data; | ||
| 1801 | int i; | ||
| 1802 | |||
| 1803 | clear_bit(PHY_RESET, &tp->flags); | ||
| 1804 | |||
| 1805 | data = r8152_mdio_read(tp, MII_BMCR); | ||
| 1806 | |||
| 1807 | /* don't reset again before the previous one complete */ | ||
| 1808 | if (data & BMCR_RESET) | ||
| 1809 | return; | ||
| 1810 | |||
| 1811 | data |= BMCR_RESET; | ||
| 1812 | r8152_mdio_write(tp, MII_BMCR, data); | ||
| 1813 | |||
| 1814 | for (i = 0; i < 50; i++) { | ||
| 1815 | msleep(20); | ||
| 1816 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | ||
| 1817 | break; | ||
| 1818 | } | ||
| 1819 | } | ||
| 1820 | |||
| 1797 | static void rtl_clear_bp(struct r8152 *tp) | 1821 | static void rtl_clear_bp(struct r8152 *tp) |
| 1798 | { | 1822 | { |
| 1799 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | 1823 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); |
| @@ -1852,6 +1876,7 @@ static void r8152b_hw_phy_cfg(struct r8152 *tp) | |||
| 1852 | } | 1876 | } |
| 1853 | 1877 | ||
| 1854 | r8152b_disable_aldps(tp); | 1878 | r8152b_disable_aldps(tp); |
| 1879 | set_bit(PHY_RESET, &tp->flags); | ||
| 1855 | } | 1880 | } |
| 1856 | 1881 | ||
| 1857 | static void r8152b_exit_oob(struct r8152 *tp) | 1882 | static void r8152b_exit_oob(struct r8152 *tp) |
| @@ -2040,6 +2065,8 @@ static void r8153_hw_phy_cfg(struct r8152 *tp) | |||
| 2040 | data = sram_read(tp, SRAM_10M_AMP2); | 2065 | data = sram_read(tp, SRAM_10M_AMP2); |
| 2041 | data |= AMP_DN; | 2066 | data |= AMP_DN; |
| 2042 | sram_write(tp, SRAM_10M_AMP2, data); | 2067 | sram_write(tp, SRAM_10M_AMP2, data); |
| 2068 | |||
| 2069 | set_bit(PHY_RESET, &tp->flags); | ||
| 2043 | } | 2070 | } |
| 2044 | 2071 | ||
| 2045 | static void r8153_u1u2en(struct r8152 *tp, bool enable) | 2072 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
| @@ -2293,12 +2320,26 @@ static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) | |||
| 2293 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | 2320 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
| 2294 | } | 2321 | } |
| 2295 | 2322 | ||
| 2323 | if (test_bit(PHY_RESET, &tp->flags)) | ||
| 2324 | bmcr |= BMCR_RESET; | ||
| 2325 | |||
| 2296 | if (tp->mii.supports_gmii) | 2326 | if (tp->mii.supports_gmii) |
| 2297 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | 2327 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); |
| 2298 | 2328 | ||
| 2299 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | 2329 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
| 2300 | r8152_mdio_write(tp, MII_BMCR, bmcr); | 2330 | r8152_mdio_write(tp, MII_BMCR, bmcr); |
| 2301 | 2331 | ||
| 2332 | if (test_bit(PHY_RESET, &tp->flags)) { | ||
| 2333 | int i; | ||
| 2334 | |||
| 2335 | clear_bit(PHY_RESET, &tp->flags); | ||
| 2336 | for (i = 0; i < 50; i++) { | ||
| 2337 | msleep(20); | ||
| 2338 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | ||
| 2339 | break; | ||
| 2340 | } | ||
| 2341 | } | ||
| 2342 | |||
| 2302 | out: | 2343 | out: |
| 2303 | 2344 | ||
| 2304 | return ret; | 2345 | return ret; |
| @@ -2362,6 +2403,10 @@ static void rtl_work_func_t(struct work_struct *work) | |||
| 2362 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | 2403 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
| 2363 | _rtl8152_set_rx_mode(tp->netdev); | 2404 | _rtl8152_set_rx_mode(tp->netdev); |
| 2364 | 2405 | ||
| 2406 | |||
| 2407 | if (test_bit(PHY_RESET, &tp->flags)) | ||
| 2408 | rtl_phy_reset(tp); | ||
| 2409 | |||
| 2365 | out1: | 2410 | out1: |
| 2366 | return; | 2411 | return; |
| 2367 | } | 2412 | } |
| @@ -2457,7 +2502,6 @@ static void r8152b_enable_fc(struct r8152 *tp) | |||
| 2457 | static void r8152b_init(struct r8152 *tp) | 2502 | static void r8152b_init(struct r8152 *tp) |
| 2458 | { | 2503 | { |
| 2459 | u32 ocp_data; | 2504 | u32 ocp_data; |
| 2460 | int i; | ||
| 2461 | 2505 | ||
| 2462 | rtl_clear_bp(tp); | 2506 | rtl_clear_bp(tp); |
| 2463 | 2507 | ||
| @@ -2489,14 +2533,6 @@ static void r8152b_init(struct r8152 *tp) | |||
| 2489 | r8152b_enable_aldps(tp); | 2533 | r8152b_enable_aldps(tp); |
| 2490 | r8152b_enable_fc(tp); | 2534 | r8152b_enable_fc(tp); |
| 2491 | 2535 | ||
| 2492 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | | ||
| 2493 | BMCR_ANRESTART); | ||
| 2494 | for (i = 0; i < 100; i++) { | ||
| 2495 | udelay(100); | ||
| 2496 | if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) | ||
| 2497 | break; | ||
| 2498 | } | ||
| 2499 | |||
| 2500 | /* enable rx aggregation */ | 2536 | /* enable rx aggregation */ |
| 2501 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | 2537 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
| 2502 | ocp_data &= ~RX_AGG_DISABLE; | 2538 | ocp_data &= ~RX_AGG_DISABLE; |
| @@ -2567,9 +2603,6 @@ static void r8153_init(struct r8152 *tp) | |||
| 2567 | r8153_enable_eee(tp); | 2603 | r8153_enable_eee(tp); |
| 2568 | r8153_enable_aldps(tp); | 2604 | r8153_enable_aldps(tp); |
| 2569 | r8152b_enable_fc(tp); | 2605 | r8152b_enable_fc(tp); |
| 2570 | |||
| 2571 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | | ||
| 2572 | BMCR_ANRESTART); | ||
| 2573 | } | 2606 | } |
| 2574 | 2607 | ||
| 2575 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | 2608 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
