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authorhayeswang <hayeswang@realtek.com>2014-07-09 22:58:54 -0400
committerVladislav Zhurba <vzhurba@nvidia.com>2018-02-01 16:58:00 -0500
commit0cdc64ad5193f62842eab99eea9604969728014e (patch)
treec725bd3d356dc3883117778ba58099509a2a0561 /drivers/net/usb
parent5e75c1bec11e9ad0f4885c2616b5901f946a6f55 (diff)
r8152: support jumbo frame for RTL8153
The maximum jumbo frame size for RTL8153 is 9K bytes. Change the max rx packet size to 9K. Change the use of the shared fifo from 6K (default) to 12K for tx. From http://git.kernel.org/cgit/linux/kernel/git/davem/net.git/commit/?id=69b4b7a4148e94a3fe7f06f72ee70113a6c61837 Change-Id: Ibac731fdd34664b3a99e5a9c7019b8fbd5a355dd Signed-off-by: Hayes Wang <hayeswang@realtek.com> Signed-off-by: David S. Miller <davem@davemloft.net> (cherry picked from upstream commit 69b4b7a4148e94a3fe7f06f72ee70113a6c61837) Signed-off-by: Aly Hirani <ahirani@nvidia.com> Reviewed-on: http://git-master/r/553394 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/net/usb')
-rw-r--r--drivers/net/usb/r8152_shield.c36
1 files changed, 32 insertions, 4 deletions
diff --git a/drivers/net/usb/r8152_shield.c b/drivers/net/usb/r8152_shield.c
index 2ca77d2da..cd81f1bd1 100644
--- a/drivers/net/usb/r8152_shield.c
+++ b/drivers/net/usb/r8152_shield.c
@@ -60,6 +60,7 @@
60#define PLA_WDT6_CTRL 0xe428 60#define PLA_WDT6_CTRL 0xe428
61#define PLA_TCR0 0xe610 61#define PLA_TCR0 0xe610
62#define PLA_TCR1 0xe612 62#define PLA_TCR1 0xe612
63#define PLA_MTPS 0xe615
63#define PLA_TXFIFO_CTRL 0xe618 64#define PLA_TXFIFO_CTRL 0xe618
64#define PLA_RSTTALLY 0xe800 65#define PLA_RSTTALLY 0xe800
65#define PLA_CR 0xe813 66#define PLA_CR 0xe813
@@ -181,6 +182,10 @@
181/* PLA_TCR1 */ 182/* PLA_TCR1 */
182#define VERSION_MASK 0x7cf0 183#define VERSION_MASK 0x7cf0
183 184
185/* PLA_MTPS */
186#define MTPS_JUMBO (12 * 1024 / 64)
187#define MTPS_DEFAULT (6 * 1024 / 64)
188
184/* PLA_RSTTALLY */ 189/* PLA_RSTTALLY */
185#define TALLY_RESET 0x0001 190#define TALLY_RESET 0x0001
186 191
@@ -441,7 +446,10 @@ enum rtl_register_content {
441#define BYTE_EN_START_MASK 0x0f 446#define BYTE_EN_START_MASK 0x0f
442#define BYTE_EN_END_MASK 0xf0 447#define BYTE_EN_END_MASK 0xf0
443 448
449#define RTL8153_MAX_PACKET 9216 /* 9K */
450#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
444#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) 451#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
452#define RTL8153_RMS RTL8153_MAX_PACKET
445#define RTL8152_TX_TIMEOUT (5 * HZ) 453#define RTL8152_TX_TIMEOUT (5 * HZ)
446 454
447/* rtl8152 flags */ 455/* rtl8152 flags */
@@ -2559,7 +2567,8 @@ static void r8153_first_init(struct r8152 *tp)
2559 ocp_data &= ~CPCR_RX_VLAN; 2567 ocp_data &= ~CPCR_RX_VLAN;
2560 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 2568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2561 2569
2562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2571 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2563 2572
2564 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 2573 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2565 ocp_data |= TCR0_AUTO_FIFO; 2574 ocp_data |= TCR0_AUTO_FIFO;
@@ -2609,7 +2618,7 @@ static void r8153_enter_oob(struct r8152 *tp)
2609 mdelay(1); 2618 mdelay(1);
2610 } 2619 }
2611 2620
2612 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 2621 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2613 2622
2614 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 2623 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2615 ocp_data &= ~TEREDO_WAKE_MASK; 2624 ocp_data &= ~TEREDO_WAKE_MASK;
@@ -3470,6 +3479,26 @@ out:
3470 return res; 3479 return res;
3471} 3480}
3472 3481
3482static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3483{
3484 struct r8152 *tp = netdev_priv(dev);
3485
3486 switch (tp->version) {
3487 case RTL_VER_01:
3488 case RTL_VER_02:
3489 return eth_change_mtu(dev, new_mtu);
3490 default:
3491 break;
3492 }
3493
3494 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3495 return -EINVAL;
3496
3497 dev->mtu = new_mtu;
3498
3499 return 0;
3500}
3501
3473static const struct net_device_ops rtl8152_netdev_ops = { 3502static const struct net_device_ops rtl8152_netdev_ops = {
3474 .ndo_open = rtl8152_open, 3503 .ndo_open = rtl8152_open,
3475 .ndo_stop = rtl8152_close, 3504 .ndo_stop = rtl8152_close,
@@ -3478,8 +3507,7 @@ static const struct net_device_ops rtl8152_netdev_ops = {
3478 .ndo_tx_timeout = rtl8152_tx_timeout, 3507 .ndo_tx_timeout = rtl8152_tx_timeout,
3479 .ndo_set_rx_mode = rtl8152_set_rx_mode, 3508 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3480 .ndo_set_mac_address = rtl8152_set_mac_address, 3509 .ndo_set_mac_address = rtl8152_set_mac_address,
3481 3510 .ndo_change_mtu = rtl8152_change_mtu,
3482 .ndo_change_mtu = eth_change_mtu,
3483 .ndo_validate_addr = eth_validate_addr, 3511 .ndo_validate_addr = eth_validate_addr,
3484}; 3512};
3485 3513