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authorAlex Van Brunt <avanbrunt@nvidia.com>2016-04-04 12:19:52 -0400
committerAlexander Van Brunt <avanbrunt@nvidia.com>2016-04-04 20:12:56 -0400
commita1e9c97f27bd17767d6eaa117ce0311428aedb07 (patch)
treebc993a5990bae2ca0b073ac5871a1564822f21c7 /drivers/gpu
parent2095d7324e5ced12165bccfb6622770f12cedfca (diff)
gpu: nvgpu: move t18x code to kernel-nvgpu-t18x
Part of moving the nvgpu driver out of the common kernel is moving the T18x part of the nvgpu driver out of kernel-t18x. So, update the Makefile to replect this change. bug 200187033 Change-Id: I11e0a73c80648ea15e9a81fe2767fe1d05ab8c2f Signed-off-by: Alex Van Brunt <avanbrunt@nvidia.com> Reviewed-on: http://git-master/r/1119777 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile29
-rw-r--r--drivers/gpu/nvgpu/gp10b/cde_gp10b.c148
-rw-r--r--drivers/gpu/nvgpu/gp10b/cde_gp10b.h23
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce2_gp10b.c83
-rw-r--r--drivers/gpu/nvgpu/gp10b/ce2_gp10b.h29
-rw-r--r--drivers/gpu/nvgpu/gp10b/fb_gp10b.c112
-rw-r--r--drivers/gpu/nvgpu/gp10b/fb_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c53
-rw-r--r--drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h23
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c195
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.h20
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b.c110
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b.h26
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c641
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h93
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c66
-rw-r--r--drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h25
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c73
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h28
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c1781
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h94
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h28
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c168
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h125
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h109
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h81
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h85
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h473
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h457
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h669
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h181
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h137
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h1237
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h4149
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h561
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h245
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h577
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h205
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h145
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h69
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h141
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h821
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h481
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h409
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h109
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h161
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.c226
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.h19
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.c167
-rw-r--r--drivers/gpu/nvgpu/gp10b/mc_gp10b.h31
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.c391
-rw-r--r--drivers/gpu/nvgpu/gp10b/mm_gp10b.h22
-rw-r--r--drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c737
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.c419
-rw-r--r--drivers/gpu/nvgpu/gp10b/pmu_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/gp10b/regops_gp10b.c505
-rw-r--r--drivers/gpu/nvgpu/gp10b/regops_gp10b.h24
-rw-r--r--drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c150
-rw-r--r--drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h30
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.c99
-rw-r--r--drivers/gpu/nvgpu/gp10b/therm_gp10b.h19
-rw-r--r--drivers/gpu/nvgpu/gr_t18x.h20
-rw-r--r--drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h36
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c20
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c206
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h21
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c36
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c185
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h21
71 files changed, 0 insertions, 18943 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
deleted file mode 100644
index cd46b30df..000000000
--- a/drivers/gpu/nvgpu/Makefile
+++ /dev/null
@@ -1,29 +0,0 @@
1nvgpu-t18x := ../../../../kernel-t18x/drivers/gpu/nvgpu
2
3nvgpu-y += \
4 $(nvgpu-t18x)/gp10b/gr_gp10b.o \
5 $(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \
6 $(nvgpu-t18x)/gp10b/ce2_gp10b.o \
7 $(nvgpu-t18x)/gp10b/mc_gp10b.o \
8 $(nvgpu-t18x)/gp10b/fifo_gp10b.o \
9 $(nvgpu-t18x)/gp10b/ltc_gp10b.o \
10 $(nvgpu-t18x)/gp10b/mm_gp10b.o \
11 $(nvgpu-t18x)/gp10b/fb_gp10b.o \
12 $(nvgpu-t18x)/gp10b/pmu_gp10b.o \
13 $(nvgpu-t18x)/gp10b/hal_gp10b.o \
14 $(nvgpu-t18x)/gp10b/rpfb_gp10b.o \
15 $(nvgpu-t18x)/gp10b/gp10b_gating_reglist.o \
16 $(nvgpu-t18x)/gp10b/regops_gp10b.o \
17 $(nvgpu-t18x)/gp10b/cde_gp10b.o \
18 $(nvgpu-t18x)/gp10b/therm_gp10b.o \
19 $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \
20 $(nvgpu-t18x)/gp10b/gp10b_sysfs.o \
21 $(nvgpu-t18x)/gp10b/gp10b.o
22
23nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
24
25nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
26 $(nvgpu-t18x)/vgpu/gp10b/vgpu_hal_gp10b.o \
27 $(nvgpu-t18x)/vgpu/gp10b/vgpu_gr_gp10b.o \
28 $(nvgpu-t18x)/vgpu/gp10b/vgpu_mm_gp10b.o \
29 $(nvgpu-t18x)/vgpu/gp10b/vgpu_fifo_gp10b.o
diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c
deleted file mode 100644
index dadec4d26..000000000
--- a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * GP10B CDE
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "cde_gp10b.h"
18
19enum gp10b_programs {
20 GP10B_PROG_HPASS = 0,
21 GP10B_PROG_HPASS_4K = 1,
22 GP10B_PROG_VPASS = 2,
23 GP10B_PROG_VPASS_4K = 3,
24 GP10B_PROG_HPASS_DEBUG = 4,
25 GP10B_PROG_HPASS_4K_DEBUG = 5,
26 GP10B_PROG_VPASS_DEBUG = 6,
27 GP10B_PROG_VPASS_4K_DEBUG = 7,
28 GP10B_PROG_PASSTHROUGH = 8,
29};
30
31static void gp10b_cde_get_program_numbers(struct gk20a *g,
32 u32 block_height_log2,
33 int *hprog_out, int *vprog_out)
34{
35 int hprog, vprog;
36
37 if (g->cde_app.shader_parameter == 1) {
38 hprog = GP10B_PROG_PASSTHROUGH;
39 vprog = GP10B_PROG_PASSTHROUGH;
40 } else {
41 hprog = GP10B_PROG_HPASS;
42 vprog = GP10B_PROG_VPASS;
43 if (g->cde_app.shader_parameter == 2) {
44 hprog = GP10B_PROG_HPASS_DEBUG;
45 vprog = GP10B_PROG_VPASS_DEBUG;
46 }
47 if (g->mm.bypass_smmu) {
48 if (!g->mm.disable_bigpage) {
49 gk20a_warn(&g->dev->dev,
50 "when bypass_smmu is 1, disable_bigpage must be 1 too");
51 }
52 hprog |= 1;
53 vprog |= 1;
54 }
55 }
56
57 *hprog_out = hprog;
58 *vprog_out = vprog;
59}
60
61static bool gp10b_need_scatter_buffer(struct gk20a *g)
62{
63 return g->mm.bypass_smmu;
64}
65
66static u8 parity(u32 a)
67{
68 a ^= a>>16u;
69 a ^= a>>8u;
70 a ^= a>>4u;
71 a &= 0xfu;
72 return (0x6996u >> a) & 1u;
73}
74
75static int gp10b_populate_scatter_buffer(struct gk20a *g,
76 struct sg_table *sgt,
77 size_t surface_size,
78 void *scatter_buffer_ptr,
79 size_t scatter_buffer_size)
80{
81 /* map scatter buffer to CPU VA and fill it */
82 const u32 page_size_log2 = 12;
83 const u32 page_size = 1 << page_size_log2;
84 const u32 page_size_shift = page_size_log2 - 7u;
85
86 /* 0011 1111 1111 1111 1111 1110 0100 1000 */
87 const u32 getSliceMaskGP10B = 0x3ffffe48;
88 u8 *scatter_buffer = scatter_buffer_ptr;
89
90 size_t i;
91 struct scatterlist *sg = NULL;
92 u8 d = 0;
93 size_t page = 0;
94 size_t pages_left;
95
96 surface_size = round_up(surface_size, page_size);
97
98 pages_left = surface_size >> page_size_log2;
99 if ((pages_left >> 3) > scatter_buffer_size)
100 return -ENOMEM;
101
102 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
103 unsigned int j;
104 u64 surf_pa = sg_phys(sg);
105 unsigned int n = (int)(sg->length >> page_size_log2);
106
107 gk20a_dbg(gpu_dbg_cde, "surfPA=0x%llx + %d pages", surf_pa, n);
108
109 for (j=0; j < n && pages_left > 0; j++, surf_pa += page_size) {
110 u32 addr = (((u32)(surf_pa>>7)) & getSliceMaskGP10B) >> page_size_shift;
111 u8 scatter_bit = parity(addr);
112 u8 bit = page & 7;
113
114 d |= scatter_bit << bit;
115 if (bit == 7) {
116 scatter_buffer[page >> 3] = d;
117 d = 0;
118 }
119
120 ++page;
121 --pages_left;
122 }
123
124 if (pages_left == 0)
125 break;
126 }
127
128 /* write the last byte in case the number of pages is not divisible by 8 */
129 if ((page & 7) != 0)
130 scatter_buffer[page >> 3] = d;
131
132#if defined(GK20A_DEBUG)
133 if (unlikely(gpu_dbg_cde & gk20a_dbg_mask)) {
134 gk20a_dbg(gpu_dbg_cde, "scatterBuffer content:");
135 for (i=0; i < page>>3; i++) {
136 gk20a_dbg(gpu_dbg_cde, " %x", scatter_buffer[i]);
137 }
138 }
139#endif
140 return 0;
141}
142
143void gp10b_init_cde_ops(struct gpu_ops *gops)
144{
145 gops->cde.get_program_numbers = gp10b_cde_get_program_numbers;
146 gops->cde.need_scatter_buffer = gp10b_need_scatter_buffer;
147 gops->cde.populate_scatter_buffer = gp10b_populate_scatter_buffer;
148}
diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.h b/drivers/gpu/nvgpu/gp10b/cde_gp10b.h
deleted file mode 100644
index 52f785f1c..000000000
--- a/drivers/gpu/nvgpu/gp10b/cde_gp10b.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * GP10B CDE
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVHOST_GP10B_CDE
17#define _NVHOST_GP10B_CDE
18
19struct gpu_ops;
20
21void gp10b_init_cde_ops(struct gpu_ops *gops);
22
23#endif
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c
deleted file mode 100644
index 4cb13f3b4..000000000
--- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c
+++ /dev/null
@@ -1,83 +0,0 @@
1/*
2 * GK20A Graphics Copy Engine (gr host)
3 *
4 * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
21#include "hw_ce2_gp10b.h"
22#include "ce2_gp10b.h"
23
24static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
25{
26 gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
27
28 /* wake theads waiting in this channel */
29 gk20a_channel_semaphore_wakeup(g, true);
30 return ce2_intr_status_nonblockpipe_pending_f();
31}
32
33static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
34{
35 gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
36
37 return ce2_intr_status_blockpipe_pending_f();
38}
39
40static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
41{
42 gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n");
43
44 return ce2_intr_status_launcherr_pending_f();
45}
46
47static void gp10b_ce2_isr(struct gk20a *g)
48{
49 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
50 u32 clear_intr = 0;
51
52 gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
53
54 /* clear blocking interrupts: they exibit broken behavior */
55 if (ce2_intr & ce2_intr_status_blockpipe_pending_f())
56 clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
57
58 if (ce2_intr & ce2_intr_status_launcherr_pending_f())
59 clear_intr |= ce2_launcherr_isr(g, ce2_intr);
60
61 gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
62 return;
63}
64
65static void gp10b_ce2_nonstall_isr(struct gk20a *g)
66{
67 u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0));
68 u32 clear_intr = 0;
69
70 gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
71
72 if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f())
73 clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr);
74
75 gk20a_writel(g, ce2_intr_status_r(0), clear_intr);
76
77 return;
78}
79void gp10b_init_ce2(struct gpu_ops *gops)
80{
81 gops->ce2.isr_stall = gp10b_ce2_isr;
82 gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr;
83}
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h
deleted file mode 100644
index d432d1e0f..000000000
--- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * drivers/video/tegra/host/gk20a/fifo_gk20a.h
3 *
4 * GK20A graphics copy engine (gr host)
5 *
6 * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21#ifndef __CE2_GP10B_H__
22#define __CE2_GP10B_H__
23
24#include "gk20a/channel_gk20a.h"
25#include "gk20a/tsg_gk20a.h"
26
27void gp10b_init_ce2(struct gpu_ops *gops);
28
29#endif /*__CE2_GP10B_H__*/
diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c
deleted file mode 100644
index 8b3b21530..000000000
--- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * GP10B FB
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5*
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17
18#include "gk20a/gk20a.h"
19#include "gm20b/fb_gm20b.h"
20#include "gk20a/kind_gk20a.h"
21
22#include "hw_gmmu_gp10b.h"
23
24static void gp10b_init_uncompressed_kind_map(void)
25{
26 gm20b_init_uncompressed_kind_map();
27
28 gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] =
29 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] =
30 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] =
31 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] =
32 gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] =
33 gmmu_pte_kind_z16_v();
34
35 gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] =
36 gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] =
37 gmmu_pte_kind_generic_16bx2_v();
38}
39
40static bool gp10b_kind_supported(u8 k)
41{
42 return (k >= gmmu_pte_kind_z16_2cz_v() &&
43 k <= gmmu_pte_kind_z16_ms8_2cz_v())
44 || k == gmmu_pte_kind_z16_ms16_2cz_v()
45 || k == gmmu_pte_kind_c32_ms4_4cbra_v()
46 || k == gmmu_pte_kind_c64_ms4_4cbra_v();
47}
48
49static bool gp10b_kind_z(u8 k)
50{
51 return (k >= gmmu_pte_kind_z16_2cz_v() &&
52 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
53 k == gmmu_pte_kind_z16_ms16_2cz_v();
54}
55
56static bool gp10b_kind_compressible(u8 k)
57{
58 return (k >= gmmu_pte_kind_z16_2cz_v() &&
59 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
60 k == gmmu_pte_kind_z16_ms16_2cz_v() ||
61 (k >= gmmu_pte_kind_z16_4cz_v() &&
62 k <= gmmu_pte_kind_z16_ms16_4cz_v()) ||
63 k == gmmu_pte_kind_c32_ms4_4cbra_v() ||
64 k == gmmu_pte_kind_c64_ms4_4cbra_v();
65}
66
67static bool gp10b_kind_zbc(u8 k)
68{
69 return (k >= gmmu_pte_kind_z16_2cz_v() &&
70 k <= gmmu_pte_kind_z16_ms8_2cz_v()) ||
71 k == gmmu_pte_kind_z16_ms16_2cz_v() ||
72 k == gmmu_pte_kind_c32_ms4_4cbra_v() ||
73 k == gmmu_pte_kind_c64_ms4_4cbra_v();
74}
75
76static void gp10b_init_kind_attr(void)
77{
78 u16 k;
79
80 gm20b_init_kind_attr();
81
82 for (k = 0; k < 256; k++) {
83 if (gp10b_kind_supported((u8)k))
84 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED;
85 if (gp10b_kind_compressible((u8)k))
86 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE;
87 if (gp10b_kind_z((u8)k))
88 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z;
89 if (gp10b_kind_zbc((u8)k))
90 gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC;
91 }
92}
93
94static int gp10b_fb_compression_page_size(struct gk20a *g)
95{
96 return SZ_64K;
97}
98
99static int gp10b_fb_compressible_page_size(struct gk20a *g)
100{
101 return SZ_4K;
102}
103
104void gp10b_init_fb(struct gpu_ops *gops)
105{
106 gm20b_init_fb(gops);
107 gops->fb.compression_page_size = gp10b_fb_compression_page_size;
108 gops->fb.compressible_page_size = gp10b_fb_compressible_page_size;
109
110 gp10b_init_uncompressed_kind_map();
111 gp10b_init_kind_attr();
112}
diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h
deleted file mode 100644
index 76efd3319..000000000
--- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * GP10B FB
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GP10B_FB
17#define _NVGPU_GP10B_FB
18struct gpu_ops;
19
20void gp10b_init_fb(struct gpu_ops *gops);
21#endif
diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c
deleted file mode 100644
index 7dd200a98..000000000
--- a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * GP10B GPU FECS traces
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gk20a/fecs_trace_gk20a.h"
18#include "gp10b/hw_ctxsw_prog_gp10b.h"
19#include "gp10b/hw_gr_gp10b.h"
20
21#ifdef CONFIG_GK20A_CTXSW_TRACE
22static int gp10b_fecs_trace_flush(struct gk20a *g)
23{
24 struct fecs_method_op_gk20a op = {
25 .mailbox = { .id = 0, .data = 0,
26 .clr = ~0, .ok = 0, .fail = 0},
27 .method.addr = gr_fecs_method_push_adr_write_timestamp_record_v(),
28 .method.data = 0,
29 .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL,
30 .cond.fail = GR_IS_UCODE_OP_SKIP,
31 };
32 int err;
33
34 gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, "");
35
36 err = gr_gk20a_elpg_protected_call(g,
37 gr_gk20a_submit_fecs_method_op(g, op, false));
38 if (err)
39 gk20a_err(dev_from_gk20a(g), "write timestamp record failed");
40
41 return err;
42}
43
44void gp10b_init_fecs_trace_ops(struct gpu_ops *ops)
45{
46 gk20a_init_fecs_trace_ops(ops);
47 ops->fecs_trace.flush = gp10b_fecs_trace_flush;
48}
49#else
50void gp10b_init_fecs_trace_ops(struct gpu_ops *ops)
51{
52}
53#endif /* CONFIG_GK20A_CTXSW_TRACE */
diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
deleted file mode 100644
index 2a25f4f67..000000000
--- a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * GP10B GPU FECS traces
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_FECS_TRACE_GP10B_H_
17#define _NVGPU_FECS_TRACE_GP10B_H_
18
19struct gpu_ops;
20
21int gp10b_init_fecs_trace_ops(struct gpu_ops *);
22
23#endif
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
deleted file mode 100644
index ade6ff0a0..000000000
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * GP10B fifo
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/delay.h>
17#include <linux/types.h>
18
19#include "gk20a/gk20a.h"
20#include "gm20b/fifo_gm20b.h"
21#include "hw_pbdma_gp10b.h"
22#include "fifo_gp10b.h"
23#include "hw_ccsr_gp10b.h"
24#include "hw_fifo_gp10b.h"
25#include "hw_ram_gp10b.h"
26
27static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g,
28 void *inst_ptr)
29{
30 u32 val;
31
32 gk20a_dbg_fn("");
33
34 val = gk20a_mem_rd32(inst_ptr,
35 ram_in_page_dir_base_fault_replay_tex_w());
36 val &= ~ram_in_page_dir_base_fault_replay_tex_m();
37 val |= ram_in_page_dir_base_fault_replay_tex_true_f();
38 gk20a_mem_wr32(inst_ptr,
39 ram_in_page_dir_base_fault_replay_tex_w(), val);
40
41 val = gk20a_mem_rd32(inst_ptr,
42 ram_in_page_dir_base_fault_replay_gcc_w());
43 val &= ~ram_in_page_dir_base_fault_replay_gcc_m();
44 val |= ram_in_page_dir_base_fault_replay_gcc_true_f();
45 gk20a_mem_wr32(inst_ptr,
46 ram_in_page_dir_base_fault_replay_gcc_w(), val);
47
48 gk20a_dbg_fn("done");
49}
50
51static int channel_gp10b_commit_userd(struct channel_gk20a *c)
52{
53 u32 addr_lo;
54 u32 addr_hi;
55 void *inst_ptr;
56
57 gk20a_dbg_fn("");
58
59 inst_ptr = c->inst_block.cpu_va;
60 if (!inst_ptr)
61 return -ENOMEM;
62
63 addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v());
64 addr_hi = u64_hi32(c->userd_iova);
65
66 gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx",
67 c->hw_chid, (u64)c->userd_iova);
68
69 gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_w(),
70 pbdma_userd_target_vid_mem_f() |
71 pbdma_userd_addr_f(addr_lo));
72
73 gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_hi_w(),
74 pbdma_userd_target_vid_mem_f() |
75 pbdma_userd_hi_addr_f(addr_hi));
76
77 return 0;
78}
79
80static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
81 u64 gpfifo_base, u32 gpfifo_entries, u32 flags)
82{
83 void *inst_ptr;
84
85 gk20a_dbg_fn("");
86
87 inst_ptr = c->inst_block.cpu_va;
88 if (!inst_ptr)
89 return -ENOMEM;
90
91 memset(inst_ptr, 0, ram_fc_size_val_v());
92
93 gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_w(),
94 pbdma_gp_base_offset_f(
95 u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s())));
96
97 gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_hi_w(),
98 pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) |
99 pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries)));
100
101 gk20a_mem_wr32(inst_ptr, ram_fc_signature_w(),
102 c->g->ops.fifo.get_pbdma_signature(c->g));
103
104 gk20a_mem_wr32(inst_ptr, ram_fc_formats_w(),
105 pbdma_formats_gp_fermi0_f() |
106 pbdma_formats_pb_fermi1_f() |
107 pbdma_formats_mp_fermi0_f());
108
109 gk20a_mem_wr32(inst_ptr, ram_fc_pb_header_w(),
110 pbdma_pb_header_priv_user_f() |
111 pbdma_pb_header_method_zero_f() |
112 pbdma_pb_header_subchannel_zero_f() |
113 pbdma_pb_header_level_main_f() |
114 pbdma_pb_header_first_true_f() |
115 pbdma_pb_header_type_inc_f());
116
117 gk20a_mem_wr32(inst_ptr, ram_fc_subdevice_w(),
118 pbdma_subdevice_id_f(1) |
119 pbdma_subdevice_status_active_f() |
120 pbdma_subdevice_channel_dma_enable_f());
121
122 gk20a_mem_wr32(inst_ptr, ram_fc_target_w(), pbdma_target_engine_sw_f());
123
124 gk20a_mem_wr32(inst_ptr, ram_fc_acquire_w(),
125 channel_gk20a_pbdma_acquire_val(c));
126
127 gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(),
128 pbdma_runlist_timeslice_timeout_128_f() |
129 pbdma_runlist_timeslice_timescale_3_f() |
130 pbdma_runlist_timeslice_enable_true_f());
131
132 if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE)
133 gp10b_set_pdb_fault_replay_flags(c->g, inst_ptr);
134
135
136 gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid));
137
138 return channel_gp10b_commit_userd(c);
139}
140
141static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
142{
143 return g->gpu_characteristics.gpfifo_class
144 | pbdma_signature_sw_zero_f();
145}
146
147static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
148{
149 u32 new_syncpt = 0, old_syncpt;
150 void *inst_ptr;
151 u32 v;
152
153 gk20a_dbg_fn("");
154
155 inst_ptr = c->inst_block.cpu_va;
156
157 v = gk20a_mem_rd32(inst_ptr, ram_fc_allowed_syncpoints_w());
158 old_syncpt = pbdma_allowed_syncpoints_0_index_v(v);
159 if (c->sync)
160 new_syncpt = c->sync->syncpt_id(c->sync);
161
162 if (new_syncpt && new_syncpt != old_syncpt) {
163 /* disable channel */
164 c->g->ops.fifo.disable_channel(c);
165
166 /* preempt the channel */
167 WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid));
168
169 v = pbdma_allowed_syncpoints_0_valid_f(1);
170
171 gk20a_dbg_info("Channel %d, syncpt id %d\n",
172 c->hw_chid, new_syncpt);
173
174 v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt);
175
176 gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v);
177 }
178
179 /* enable channel */
180 gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
181 gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
182 ccsr_channel_enable_set_true_f());
183
184 gk20a_dbg_fn("done");
185
186 return 0;
187}
188
189void gp10b_init_fifo(struct gpu_ops *gops)
190{
191 gm20b_init_fifo(gops);
192 gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc;
193 gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
194 gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
195}
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
deleted file mode 100644
index ad3679aa7..000000000
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * GP10B Fifo
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef FIFO_GP10B_H
17#define FIFO_GP10B_H
18struct gpu_ops;
19void gp10b_init_fifo(struct gpu_ops *gops);
20#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c
deleted file mode 100644
index a541dda35..000000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * GP10B Graphics
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include "gk20a/gk20a.h"
20#include "hw_fuse_gp10b.h"
21#include "hw_gr_gp10b.h"
22
23static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g)
24{
25 u64 ecc_enabled_units = 0;
26 u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r());
27 u32 opt_feature_fuses_override_disable =
28 gk20a_readl(g,
29 fuse_opt_feature_fuses_override_disable_r());
30 u32 fecs_feature_override_ecc =
31 gk20a_readl(g,
32 gr_fecs_feature_override_ecc_r());
33
34 if (opt_feature_fuses_override_disable) {
35 if (opt_ecc_en)
36 ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED;
37 else
38 ecc_enabled_units = 0;
39 } else {
40 /* SM LRF */
41 if (gr_fecs_feature_override_ecc_sm_lrf_override_v(
42 fecs_feature_override_ecc)) {
43 if (gr_fecs_feature_override_ecc_sm_lrf_v(
44 fecs_feature_override_ecc)) {
45 ecc_enabled_units |=
46 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
47 }
48 } else {
49 if (opt_ecc_en) {
50 ecc_enabled_units |=
51 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF;
52 }
53 }
54
55 /* SM SHM */
56 if (gr_fecs_feature_override_ecc_sm_shm_override_v(
57 fecs_feature_override_ecc)) {
58 if (gr_fecs_feature_override_ecc_sm_shm_v(
59 fecs_feature_override_ecc)) {
60 ecc_enabled_units |=
61 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
62 }
63 } else {
64 if (opt_ecc_en) {
65 ecc_enabled_units |=
66 NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM;
67 }
68 }
69
70 /* TEX */
71 if (gr_fecs_feature_override_ecc_tex_override_v(
72 fecs_feature_override_ecc)) {
73 if (gr_fecs_feature_override_ecc_tex_v(
74 fecs_feature_override_ecc)) {
75 ecc_enabled_units |=
76 NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
77 }
78 } else {
79 if (opt_ecc_en) {
80 ecc_enabled_units |=
81 NVGPU_GPU_FLAGS_ECC_ENABLED_TEX;
82 }
83 }
84
85 /* LTC */
86 if (gr_fecs_feature_override_ecc_ltc_override_v(
87 fecs_feature_override_ecc)) {
88 if (gr_fecs_feature_override_ecc_ltc_v(
89 fecs_feature_override_ecc)) {
90 ecc_enabled_units |=
91 NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
92 }
93 } else {
94 if (opt_ecc_en) {
95 ecc_enabled_units |=
96 NVGPU_GPU_FLAGS_ECC_ENABLED_LTC;
97 }
98 }
99 }
100
101 return ecc_enabled_units;
102}
103
104int gp10b_init_gpu_characteristics(struct gk20a *g)
105{
106 gk20a_init_gpu_characteristics(g);
107 g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g);
108
109 return 0;
110}
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.h b/drivers/gpu/nvgpu/gp10b/gp10b.h
deleted file mode 100644
index 263f3cbea..000000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * GP10B Graphics
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#ifndef GP10B_H
20#define GP10B_H
21
22#include "gk20a/gk20a.h"
23
24int gp10b_init_gpu_characteristics(struct gk20a *g);
25
26#endif /* GP10B_H */
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
deleted file mode 100644
index 4719b13e1..000000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c
+++ /dev/null
@@ -1,641 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 *
17 * This file is autogenerated. Do not edit.
18 */
19
20#ifndef __gp10b_gating_reglist_h__
21#define __gp10b_gating_reglist_h__
22
23#include <linux/types.h>
24#include "gp10b_gating_reglist.h"
25
26struct gating_desc {
27 u32 addr;
28 u32 prod;
29 u32 disable;
30};
31/* slcg bus */
32static const struct gating_desc gp10b_slcg_bus[] = {
33 {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
34};
35
36/* slcg ce2 */
37static const struct gating_desc gp10b_slcg_ce2[] = {
38 {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
39};
40
41/* slcg chiplet */
42static const struct gating_desc gp10b_slcg_chiplet[] = {
43 {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
44 {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
45 {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
46 {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
47};
48
49/* slcg fb */
50static const struct gating_desc gp10b_slcg_fb[] = {
51 {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
52 {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
53};
54
55/* slcg fifo */
56static const struct gating_desc gp10b_slcg_fifo[] = {
57 {.addr = 0x000026ac, .prod = 0x00000f00, .disable = 0x0001fffe},
58};
59
60/* slcg gr */
61static const struct gating_desc gp10b_slcg_gr[] = {
62 {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe},
63 {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
64 {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
65 {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
66 {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
67 {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
68 {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
69 {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
70 {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
71 {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
72 {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
73 {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
74 {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
75 {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
76 {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e},
77 {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
78 {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
79 {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
80 {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
81 {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe},
82 {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe},
83 {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
84 {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
85 {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
86 {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
87 {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
88 {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
89 {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
90 {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
91 {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
92 {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
93 {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
94 {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
95 {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
96 {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
97 {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
98 {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
99 {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
100 {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
101 {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
102 {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
103 {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
104 {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
105 {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
106 {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
107 {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
108 {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
109 {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
110 {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
111 {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
112 {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
113 {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
114};
115
116/* slcg ltc */
117static const struct gating_desc gp10b_slcg_ltc[] = {
118 {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
119 {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
120};
121
122/* slcg perf */
123static const struct gating_desc gp10b_slcg_perf[] = {
124 {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
125 {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
126 {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
127 {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
128};
129
130/* slcg PriRing */
131static const struct gating_desc gp10b_slcg_priring[] = {
132 {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
133};
134
135/* slcg pwr_csb */
136static const struct gating_desc gp10b_slcg_pwr_csb[] = {
137 {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe},
138 {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f},
139 {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe},
140 {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f},
141};
142
143/* slcg pmu */
144static const struct gating_desc gp10b_slcg_pmu[] = {
145 {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
146 {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe},
147 {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
148};
149
150/* therm gr */
151static const struct gating_desc gp10b_slcg_therm[] = {
152 {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
153};
154
155/* slcg Xbar */
156static const struct gating_desc gp10b_slcg_xbar[] = {
157 {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
158 {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
159};
160
161/* blcg bus */
162static const struct gating_desc gp10b_blcg_bus[] = {
163 {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
164};
165
166/* blcg ce */
167static const struct gating_desc gp10b_blcg_ce[] = {
168 {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000},
169};
170
171/* blcg ctxsw prog */
172static const struct gating_desc gp10b_blcg_ctxsw_prog[] = {
173};
174
175/* blcg fb */
176static const struct gating_desc gp10b_blcg_fb[] = {
177 {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
178 {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
179 {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
180 {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
181 {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},
182 {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
183};
184
185/* blcg fifo */
186static const struct gating_desc gp10b_blcg_fifo[] = {
187 {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
188};
189
190/* blcg gr */
191static const struct gating_desc gp10b_blcg_gr[] = {
192 {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
193 {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
194 {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
195 {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
196 {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
197 {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
198 {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
199 {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
200 {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
201 {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
202 {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
203 {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
204 {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
205 {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
206 {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
207 {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
208 {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
209 {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
210 {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
211 {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
212 {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
213 {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
214 {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
215 {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
216 {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
217 {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
218 {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
219 {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
220 {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
221 {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
222 {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
223 {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
224 {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
225 {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
226 {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
227 {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
228 {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
229 {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
230 {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
231 {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
232 {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
233 {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
234 {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
235 {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
236 {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
237 {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
238 {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
239 {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
240 {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
241 {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
242 {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
243 {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
244 {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
245};
246
247/* blcg ltc */
248static const struct gating_desc gp10b_blcg_ltc[] = {
249 {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
250 {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
251 {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
252 {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
253};
254
255/* blcg pwr_csb */
256static const struct gating_desc gp10b_blcg_pwr_csb[] = {
257 {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000},
258};
259
260/* blcg pmu */
261static const struct gating_desc gp10b_blcg_pmu[] = {
262 {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
263};
264
265/* blcg Xbar */
266static const struct gating_desc gp10b_blcg_xbar[] = {
267 {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
268 {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
269};
270
271/* pg gr */
272static const struct gating_desc gp10b_pg_gr[] = {
273};
274
275/* inline functions */
276void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
277 bool prod)
278{
279 u32 i;
280 u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc);
281 for (i = 0; i < size; i++) {
282 if (prod)
283 gk20a_writel(g, gp10b_slcg_bus[i].addr,
284 gp10b_slcg_bus[i].prod);
285 else
286 gk20a_writel(g, gp10b_slcg_bus[i].addr,
287 gp10b_slcg_bus[i].disable);
288 }
289}
290
291void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
292 bool prod)
293{
294 u32 i;
295 u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc);
296 for (i = 0; i < size; i++) {
297 if (prod)
298 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
299 gp10b_slcg_ce2[i].prod);
300 else
301 gk20a_writel(g, gp10b_slcg_ce2[i].addr,
302 gp10b_slcg_ce2[i].disable);
303 }
304}
305
306void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
307 bool prod)
308{
309 u32 i;
310 u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc);
311 for (i = 0; i < size; i++) {
312 if (prod)
313 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
314 gp10b_slcg_chiplet[i].prod);
315 else
316 gk20a_writel(g, gp10b_slcg_chiplet[i].addr,
317 gp10b_slcg_chiplet[i].disable);
318 }
319}
320
321void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
322 bool prod)
323{
324}
325
326void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
327 bool prod)
328{
329 u32 i;
330 u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc);
331 for (i = 0; i < size; i++) {
332 if (prod)
333 gk20a_writel(g, gp10b_slcg_fb[i].addr,
334 gp10b_slcg_fb[i].prod);
335 else
336 gk20a_writel(g, gp10b_slcg_fb[i].addr,
337 gp10b_slcg_fb[i].disable);
338 }
339}
340
341void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
342 bool prod)
343{
344 u32 i;
345 u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc);
346 for (i = 0; i < size; i++) {
347 if (prod)
348 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
349 gp10b_slcg_fifo[i].prod);
350 else
351 gk20a_writel(g, gp10b_slcg_fifo[i].addr,
352 gp10b_slcg_fifo[i].disable);
353 }
354}
355
356void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
357 bool prod)
358{
359 u32 i;
360 u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc);
361 for (i = 0; i < size; i++) {
362 if (prod)
363 gk20a_writel(g, gp10b_slcg_gr[i].addr,
364 gp10b_slcg_gr[i].prod);
365 else
366 gk20a_writel(g, gp10b_slcg_gr[i].addr,
367 gp10b_slcg_gr[i].disable);
368 }
369}
370
371void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
372 bool prod)
373{
374 u32 i;
375 u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc);
376 for (i = 0; i < size; i++) {
377 if (prod)
378 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
379 gp10b_slcg_ltc[i].prod);
380 else
381 gk20a_writel(g, gp10b_slcg_ltc[i].addr,
382 gp10b_slcg_ltc[i].disable);
383 }
384}
385
386void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
387 bool prod)
388{
389 u32 i;
390 u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc);
391 for (i = 0; i < size; i++) {
392 if (prod)
393 gk20a_writel(g, gp10b_slcg_perf[i].addr,
394 gp10b_slcg_perf[i].prod);
395 else
396 gk20a_writel(g, gp10b_slcg_perf[i].addr,
397 gp10b_slcg_perf[i].disable);
398 }
399}
400
401void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
402 bool prod)
403{
404 u32 i;
405 u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc);
406 for (i = 0; i < size; i++) {
407 if (prod)
408 gk20a_writel(g, gp10b_slcg_priring[i].addr,
409 gp10b_slcg_priring[i].prod);
410 else
411 gk20a_writel(g, gp10b_slcg_priring[i].addr,
412 gp10b_slcg_priring[i].disable);
413 }
414}
415
416void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
417 bool prod)
418{
419 u32 i;
420 u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc);
421 for (i = 0; i < size; i++) {
422 if (prod)
423 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
424 gp10b_slcg_pwr_csb[i].prod);
425 else
426 gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr,
427 gp10b_slcg_pwr_csb[i].disable);
428 }
429}
430
431void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
432 bool prod)
433{
434 u32 i;
435 u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc);
436 for (i = 0; i < size; i++) {
437 if (prod)
438 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
439 gp10b_slcg_pmu[i].prod);
440 else
441 gk20a_writel(g, gp10b_slcg_pmu[i].addr,
442 gp10b_slcg_pmu[i].disable);
443 }
444}
445
446void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
447 bool prod)
448{
449 u32 i;
450 u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc);
451 for (i = 0; i < size; i++) {
452 if (prod)
453 gk20a_writel(g, gp10b_slcg_therm[i].addr,
454 gp10b_slcg_therm[i].prod);
455 else
456 gk20a_writel(g, gp10b_slcg_therm[i].addr,
457 gp10b_slcg_therm[i].disable);
458 }
459}
460
461void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
462 bool prod)
463{
464 u32 i;
465 u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc);
466 for (i = 0; i < size; i++) {
467 if (prod)
468 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
469 gp10b_slcg_xbar[i].prod);
470 else
471 gk20a_writel(g, gp10b_slcg_xbar[i].addr,
472 gp10b_slcg_xbar[i].disable);
473 }
474}
475
476void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
477 bool prod)
478{
479 u32 i;
480 u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc);
481 for (i = 0; i < size; i++) {
482 if (prod)
483 gk20a_writel(g, gp10b_blcg_bus[i].addr,
484 gp10b_blcg_bus[i].prod);
485 else
486 gk20a_writel(g, gp10b_blcg_bus[i].addr,
487 gp10b_blcg_bus[i].disable);
488 }
489}
490
491void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
492 bool prod)
493{
494 u32 i;
495 u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc);
496 for (i = 0; i < size; i++) {
497 if (prod)
498 gk20a_writel(g, gp10b_blcg_ce[i].addr,
499 gp10b_blcg_ce[i].prod);
500 else
501 gk20a_writel(g, gp10b_blcg_ce[i].addr,
502 gp10b_blcg_ce[i].disable);
503 }
504}
505
506void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
507 bool prod)
508{
509 u32 i;
510 u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc);
511 for (i = 0; i < size; i++) {
512 if (prod)
513 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
514 gp10b_blcg_ctxsw_prog[i].prod);
515 else
516 gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr,
517 gp10b_blcg_ctxsw_prog[i].disable);
518 }
519}
520
521void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
522 bool prod)
523{
524 u32 i;
525 u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc);
526 for (i = 0; i < size; i++) {
527 if (prod)
528 gk20a_writel(g, gp10b_blcg_fb[i].addr,
529 gp10b_blcg_fb[i].prod);
530 else
531 gk20a_writel(g, gp10b_blcg_fb[i].addr,
532 gp10b_blcg_fb[i].disable);
533 }
534}
535
536void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
537 bool prod)
538{
539 u32 i;
540 u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc);
541 for (i = 0; i < size; i++) {
542 if (prod)
543 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
544 gp10b_blcg_fifo[i].prod);
545 else
546 gk20a_writel(g, gp10b_blcg_fifo[i].addr,
547 gp10b_blcg_fifo[i].disable);
548 }
549}
550
551void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
552 bool prod)
553{
554 u32 i;
555 u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc);
556 for (i = 0; i < size; i++) {
557 if (prod)
558 gk20a_writel(g, gp10b_blcg_gr[i].addr,
559 gp10b_blcg_gr[i].prod);
560 else
561 gk20a_writel(g, gp10b_blcg_gr[i].addr,
562 gp10b_blcg_gr[i].disable);
563 }
564}
565
566void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
567 bool prod)
568{
569 u32 i;
570 u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc);
571 for (i = 0; i < size; i++) {
572 if (prod)
573 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
574 gp10b_blcg_ltc[i].prod);
575 else
576 gk20a_writel(g, gp10b_blcg_ltc[i].addr,
577 gp10b_blcg_ltc[i].disable);
578 }
579}
580
581void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
582 bool prod)
583{
584 u32 i;
585 u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc);
586 for (i = 0; i < size; i++) {
587 if (prod)
588 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
589 gp10b_blcg_pwr_csb[i].prod);
590 else
591 gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr,
592 gp10b_blcg_pwr_csb[i].disable);
593 }
594}
595
596void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
597 bool prod)
598{
599 u32 i;
600 u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc);
601 for (i = 0; i < size; i++) {
602 if (prod)
603 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
604 gp10b_blcg_pmu[i].prod);
605 else
606 gk20a_writel(g, gp10b_blcg_pmu[i].addr,
607 gp10b_blcg_pmu[i].disable);
608 }
609}
610
611void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
612 bool prod)
613{
614 u32 i;
615 u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc);
616 for (i = 0; i < size; i++) {
617 if (prod)
618 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
619 gp10b_blcg_xbar[i].prod);
620 else
621 gk20a_writel(g, gp10b_blcg_xbar[i].addr,
622 gp10b_blcg_xbar[i].disable);
623 }
624}
625
626void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
627 bool prod)
628{
629 u32 i;
630 u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc);
631 for (i = 0; i < size; i++) {
632 if (prod)
633 gk20a_writel(g, gp10b_pg_gr[i].addr,
634 gp10b_pg_gr[i].prod);
635 else
636 gk20a_writel(g, gp10b_pg_gr[i].addr,
637 gp10b_pg_gr[i].disable);
638 }
639}
640
641#endif /* __gp10b_gating_reglist_h__ */
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h
deleted file mode 100644
index e4080def8..000000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "gk20a/gk20a.h"
18
19void gp10b_slcg_bus_load_gating_prod(struct gk20a *g,
20 bool prod);
21
22void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g,
23 bool prod);
24
25void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g,
26 bool prod);
27
28void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
29 bool prod);
30
31void gp10b_slcg_fb_load_gating_prod(struct gk20a *g,
32 bool prod);
33
34void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g,
35 bool prod);
36
37void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g,
38 bool prod);
39
40void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g,
41 bool prod);
42
43void gp10b_slcg_perf_load_gating_prod(struct gk20a *g,
44 bool prod);
45
46void gp10b_slcg_priring_load_gating_prod(struct gk20a *g,
47 bool prod);
48
49void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g,
50 bool prod);
51
52void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g,
53 bool prod);
54
55void gp10b_slcg_therm_load_gating_prod(struct gk20a *g,
56 bool prod);
57
58void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g,
59 bool prod);
60
61void gp10b_blcg_bus_load_gating_prod(struct gk20a *g,
62 bool prod);
63
64void gp10b_blcg_ce_load_gating_prod(struct gk20a *g,
65 bool prod);
66
67void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
68 bool prod);
69
70void gp10b_blcg_fb_load_gating_prod(struct gk20a *g,
71 bool prod);
72
73void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g,
74 bool prod);
75
76void gp10b_blcg_gr_load_gating_prod(struct gk20a *g,
77 bool prod);
78
79void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g,
80 bool prod);
81
82void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g,
83 bool prod);
84
85void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g,
86 bool prod);
87
88void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g,
89 bool prod);
90
91void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g,
92 bool prod);
93
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
deleted file mode 100644
index 800f39c3e..000000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * GP10B specific sysfs files
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/platform_device.h>
17
18#include "gk20a/gk20a.h"
19#include "gp10b_sysfs.h"
20
21#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH)
22
23static ssize_t ecc_enable_store(struct device *device,
24 struct device_attribute *attr, const char *buf, size_t count)
25{
26 struct platform_device *ndev = to_platform_device(device);
27 struct gk20a *g = get_gk20a(ndev);
28 u32 ecc_mask;
29 u32 err = 0;
30
31 err = sscanf(buf, "%d", &ecc_mask);
32 if (err == 1) {
33 err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd
34 (g, ecc_mask);
35 if (err)
36 dev_err(device, "ECC override did not happen\n");
37 } else
38 return -EINVAL;
39 return count;
40}
41
42static ssize_t ecc_enable_read(struct device *device,
43 struct device_attribute *attr, char *buf)
44{
45 struct platform_device *ndev = to_platform_device(device);
46 struct gk20a *g = get_gk20a(ndev);
47
48 return sprintf(buf, "ecc override =0x%x\n",
49 g->ops.gr.get_lrf_tex_ltc_dram_override(g));
50}
51
52static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store);
53
54void gp10b_create_sysfs(struct platform_device *dev)
55{
56 int error = 0;
57
58 error |= device_create_file(&dev->dev, &dev_attr_ecc_enable);
59 if (error)
60 dev_err(&dev->dev, "Failed to create sysfs attributes!\n");
61}
62
63void gp10b_remove_sysfs(struct device *dev)
64{
65 device_remove_file(dev, &dev_attr_ecc_enable);
66}
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h
deleted file mode 100644
index c1d101daf..000000000
--- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * GP10B specific sysfs files
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GP10B_SYSFS_H_
17#define _GP10B_SYSFS_H_
18
19/*ECC Fuse*/
20#define FUSE_OPT_ECC_EN 0x358
21
22void gp10b_create_sysfs(struct platform_device *dev);
23void gp10b_remove_sysfs(struct device *dev);
24
25#endif /*_GP10B_SYSFS_H_*/
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c
deleted file mode 100644
index b29562574..000000000
--- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * drivers/video/tegra/host/gp10b/gr_ctx_gp10b.c
3 *
4 * GM20B Graphics Context
5 *
6 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include "gk20a/gk20a.h"
23#include "gr_ctx_gp10b.h"
24
25static int gr_gp10b_get_netlist_name(int index, char *name)
26{
27 switch (index) {
28#ifdef GP10B_NETLIST_IMAGE_FW_NAME
29 case NETLIST_FINAL:
30 sprintf(name, GP10B_NETLIST_IMAGE_FW_NAME);
31 return 0;
32#endif
33#ifdef GK20A_NETLIST_IMAGE_A
34 case NETLIST_SLOT_A:
35 sprintf(name, GK20A_NETLIST_IMAGE_A);
36 return 0;
37#endif
38#ifdef GK20A_NETLIST_IMAGE_B
39 case NETLIST_SLOT_B:
40 sprintf(name, GK20A_NETLIST_IMAGE_B);
41 return 0;
42#endif
43#ifdef GK20A_NETLIST_IMAGE_C
44 case NETLIST_SLOT_C:
45 sprintf(name, GK20A_NETLIST_IMAGE_C);
46 return 0;
47#endif
48#ifdef GK20A_NETLIST_IMAGE_D
49 case NETLIST_SLOT_D:
50 sprintf(name, GK20A_NETLIST_IMAGE_D);
51 return 0;
52#endif
53 default:
54 return -1;
55 }
56
57 return -1;
58}
59
60static bool gr_gp10b_is_firmware_defined(void)
61{
62#ifdef GP10B_NETLIST_IMAGE_FW_NAME
63 return true;
64#else
65 return false;
66#endif
67}
68
69void gp10b_init_gr_ctx(struct gpu_ops *gops) {
70 gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name;
71 gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined;
72 gops->gr_ctx.use_dma_for_fw_bootstrap = true;
73}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
deleted file mode 100644
index b5c76d24d..000000000
--- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * GP10B Graphics Context
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __GR_CTX_GM10B_H__
19#define __GR_CTX_GM10B_H__
20
21#include "gk20a/gr_ctx_gk20a.h"
22
23/* production netlist, one and only one from below */
24#define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A
25
26void gp10b_init_gr_ctx(struct gpu_ops *gops);
27
28#endif /*__GR_CTX_GP10B_H__*/
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
deleted file mode 100644
index 1aba35f36..000000000
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ /dev/null
@@ -1,1781 +0,0 @@
1/*
2 * GP10B GPU GR
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */
17#include <linux/delay.h>
18#include <linux/tegra-fuse.h>
19
20#include "gk20a/gr_gk20a.h"
21#include "gk20a/semaphore_gk20a.h"
22#include "gk20a/dbg_gpu_gk20a.h"
23
24#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */
25#include "gp10b/gr_gp10b.h"
26#include "hw_gr_gp10b.h"
27#include "hw_fifo_gp10b.h"
28#include "hw_proj_gp10b.h"
29#include "hw_ctxsw_prog_gp10b.h"
30#include "hw_mc_gp10b.h"
31#include "gp10b_sysfs.h"
32#include <linux/vmalloc.h>
33
34static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num)
35{
36 bool valid = false;
37
38 switch (class_num) {
39 case PASCAL_COMPUTE_A:
40 case PASCAL_A:
41 case PASCAL_DMA_COPY_A:
42 valid = true;
43 break;
44
45 case MAXWELL_COMPUTE_B:
46 case MAXWELL_B:
47 case FERMI_TWOD_A:
48 case KEPLER_DMA_COPY_A:
49 case MAXWELL_DMA_COPY_A:
50 valid = true;
51 break;
52
53 default:
54 break;
55 }
56 gk20a_dbg_info("class=0x%x valid=%d", class_num, valid);
57 return valid;
58}
59
60static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
61 bool *post_event, struct channel_gk20a *fault_ch)
62{
63 int ret = 0;
64 u32 offset = proj_gpc_stride_v() * gpc +
65 proj_tpc_in_gpc_stride_v() * tpc;
66 u32 lrf_ecc_status, shm_ecc_status;
67
68 gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch);
69
70 /* Check for LRF ECC errors. */
71 lrf_ecc_status = gk20a_readl(g,
72 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset);
73 if ( (lrf_ecc_status &
74 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) ||
75 (lrf_ecc_status &
76 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) ||
77 (lrf_ecc_status &
78 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) ||
79 (lrf_ecc_status &
80 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) {
81
82 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
83 "Single bit error detected in SM LRF!");
84
85 g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] +=
86 gk20a_readl(g,
87 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset);
88 gk20a_writel(g,
89 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset,
90 0);
91 }
92 if ( (lrf_ecc_status &
93 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) ||
94 (lrf_ecc_status &
95 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) ||
96 (lrf_ecc_status &
97 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) ||
98 (lrf_ecc_status &
99 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) {
100
101 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
102 "Double bit error detected in SM LRF!");
103
104 g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] +=
105 gk20a_readl(g,
106 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset);
107 gk20a_writel(g,
108 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset,
109 0);
110 }
111 gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
112 lrf_ecc_status);
113
114 /* Check for SHM ECC errors. */
115 shm_ecc_status = gk20a_readl(g,
116 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset);
117 if ((shm_ecc_status &
118 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) ||
119 (shm_ecc_status &
120 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) ||
121 (shm_ecc_status &
122 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) ||
123 (shm_ecc_status &
124 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) {
125 u32 ecc_stats_reg_val;
126
127 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
128 "Single bit error detected in SM SHM!");
129
130 ecc_stats_reg_val =
131 gk20a_readl(g,
132 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
133 g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] +=
134 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
135 g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] +=
136 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
137 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
138 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
139 gk20a_writel(g,
140 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
141 ecc_stats_reg_val);
142 }
143 if ( (shm_ecc_status &
144 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) ||
145 (shm_ecc_status &
146 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) {
147 u32 ecc_stats_reg_val;
148
149 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
150 "Double bit error detected in SM SHM!");
151
152 ecc_stats_reg_val =
153 gk20a_readl(g,
154 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
155 g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] +=
156 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
157 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
158 gk20a_writel(g,
159 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset,
160 ecc_stats_reg_val);
161 }
162 gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset,
163 shm_ecc_status);
164
165
166 return ret;
167}
168
169static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
170 bool *post_event)
171{
172 int ret = 0;
173 u32 offset = proj_gpc_stride_v() * gpc +
174 proj_tpc_in_gpc_stride_v() * tpc;
175 u32 esr;
176 u32 ecc_stats_reg_val;
177
178 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
179
180 esr = gk20a_readl(g,
181 gr_gpc0_tpc0_tex_m_hww_esr_r() + offset);
182 gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr);
183
184 if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) {
185 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
186 "Single bit error detected in TEX!");
187
188 /* Pipe 0 counters */
189 gk20a_writel(g,
190 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
191 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
192
193 ecc_stats_reg_val = gk20a_readl(g,
194 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
195 g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] +=
196 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
197 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
198 gk20a_writel(g,
199 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
200 ecc_stats_reg_val);
201
202 ecc_stats_reg_val = gk20a_readl(g,
203 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
204 g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] +=
205 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
206 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
207 gk20a_writel(g,
208 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
209 ecc_stats_reg_val);
210
211
212 /* Pipe 1 counters */
213 gk20a_writel(g,
214 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
215 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
216
217 ecc_stats_reg_val = gk20a_readl(g,
218 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
219 g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] +=
220 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
221 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
222 gk20a_writel(g,
223 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
224 ecc_stats_reg_val);
225
226 ecc_stats_reg_val = gk20a_readl(g,
227 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
228 g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] +=
229 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
230 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
231 gk20a_writel(g,
232 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
233 ecc_stats_reg_val);
234
235
236 gk20a_writel(g,
237 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
238 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
239 }
240 if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) {
241 gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr,
242 "Double bit error detected in TEX!");
243
244 /* Pipe 0 counters */
245 gk20a_writel(g,
246 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
247 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f());
248
249 ecc_stats_reg_val = gk20a_readl(g,
250 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
251 g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] +=
252 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
253 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
254 gk20a_writel(g,
255 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
256 ecc_stats_reg_val);
257
258 ecc_stats_reg_val = gk20a_readl(g,
259 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
260 g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] +=
261 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
262 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
263 gk20a_writel(g,
264 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
265 ecc_stats_reg_val);
266
267
268 /* Pipe 1 counters */
269 gk20a_writel(g,
270 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
271 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f());
272
273 ecc_stats_reg_val = gk20a_readl(g,
274 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
275 g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] +=
276 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
277 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
278 gk20a_writel(g,
279 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset,
280 ecc_stats_reg_val);
281
282 ecc_stats_reg_val = gk20a_readl(g,
283 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
284 g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] +=
285 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
286 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
287 gk20a_writel(g,
288 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset,
289 ecc_stats_reg_val);
290
291
292 gk20a_writel(g,
293 gr_pri_gpc0_tpc0_tex_m_routing_r() + offset,
294 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f());
295 }
296
297 gk20a_writel(g,
298 gr_gpc0_tpc0_tex_m_hww_esr_r() + offset,
299 esr);
300
301 return ret;
302}
303
304static int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
305 struct channel_gk20a *c, bool patch)
306{
307 struct gr_gk20a *gr = &g->gr;
308 struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
309 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
310 u32 attrib_offset_in_chunk = 0;
311 u32 alpha_offset_in_chunk = 0;
312 u32 pd_ab_max_output;
313 u32 gpc_index, ppc_index;
314 u32 temp, temp2;
315 u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate;
316 u32 attrib_size_in_chunk, cb_attrib_cache_size_init;
317
318 gk20a_dbg_fn("");
319
320 if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) {
321 attrib_size_in_chunk = gr->attrib_cb_default_size +
322 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
323 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
324 cb_attrib_cache_size_init = gr->attrib_cb_default_size +
325 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
326 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
327 } else {
328 attrib_size_in_chunk = gr->attrib_cb_size;
329 cb_attrib_cache_size_init = gr->attrib_cb_default_size;
330 }
331
332 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(),
333 gr->attrib_cb_default_size, patch);
334 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(),
335 gr->alpha_cb_default_size, patch);
336
337 pd_ab_max_output = (gr->alpha_cb_default_size *
338 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) /
339 gr_pd_ab_dist_cfg1_max_output_granularity_v();
340
341 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(),
342 gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
343 gr_pd_ab_dist_cfg1_max_batches_init_f(), patch);
344
345 attrib_offset_in_chunk = alpha_offset_in_chunk +
346 gr->tpc_count * gr->alpha_cb_size;
347
348 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
349 temp = proj_gpc_stride_v() * gpc_index;
350 temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index;
351 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
352 ppc_index++) {
353 cbm_cfg_size_beta = cb_attrib_cache_size_init *
354 gr->pes_tpc_count[ppc_index][gpc_index];
355 cbm_cfg_size_alpha = gr->alpha_cb_default_size *
356 gr->pes_tpc_count[ppc_index][gpc_index];
357 cbm_cfg_size_steadystate = gr->attrib_cb_default_size *
358 gr->pes_tpc_count[ppc_index][gpc_index];
359
360 gr_gk20a_ctx_patch_write(g, ch_ctx,
361 gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp +
362 proj_ppc_in_gpc_stride_v() * ppc_index,
363 cbm_cfg_size_beta, patch);
364
365 gr_gk20a_ctx_patch_write(g, ch_ctx,
366 gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp +
367 proj_ppc_in_gpc_stride_v() * ppc_index,
368 attrib_offset_in_chunk, patch);
369
370 gr_gk20a_ctx_patch_write(g, ch_ctx,
371 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp +
372 proj_ppc_in_gpc_stride_v() * ppc_index,
373 cbm_cfg_size_steadystate,
374 patch);
375
376 attrib_offset_in_chunk += attrib_size_in_chunk *
377 gr->pes_tpc_count[ppc_index][gpc_index];
378
379 gr_gk20a_ctx_patch_write(g, ch_ctx,
380 gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp +
381 proj_ppc_in_gpc_stride_v() * ppc_index,
382 cbm_cfg_size_alpha, patch);
383
384 gr_gk20a_ctx_patch_write(g, ch_ctx,
385 gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp +
386 proj_ppc_in_gpc_stride_v() * ppc_index,
387 alpha_offset_in_chunk, patch);
388
389 alpha_offset_in_chunk += gr->alpha_cb_size *
390 gr->pes_tpc_count[ppc_index][gpc_index];
391
392 gr_gk20a_ctx_patch_write(g, ch_ctx,
393 gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2),
394 gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate),
395 patch);
396 }
397 }
398
399 return 0;
400}
401
402static void gr_gp10b_commit_global_pagepool(struct gk20a *g,
403 struct channel_ctx_gk20a *ch_ctx,
404 u64 addr, u32 size, bool patch)
405{
406 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(),
407 gr_scc_pagepool_base_addr_39_8_f(addr), patch);
408
409 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(),
410 gr_scc_pagepool_total_pages_f(size) |
411 gr_scc_pagepool_valid_true_f(), patch);
412
413 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(),
414 gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch);
415
416 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(),
417 gr_gpcs_gcc_pagepool_total_pages_f(size), patch);
418}
419
420static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr,
421 struct zbc_entry *color_val, u32 index)
422{
423 u32 i;
424 u32 zbc_c;
425
426 /* update l2 table */
427 g->ops.ltc.set_zbc_color_entry(g, color_val, index);
428
429 /* update ds table */
430 gk20a_writel(g, gr_ds_zbc_color_r_r(),
431 gr_ds_zbc_color_r_val_f(color_val->color_ds[0]));
432 gk20a_writel(g, gr_ds_zbc_color_g_r(),
433 gr_ds_zbc_color_g_val_f(color_val->color_ds[1]));
434 gk20a_writel(g, gr_ds_zbc_color_b_r(),
435 gr_ds_zbc_color_b_val_f(color_val->color_ds[2]));
436 gk20a_writel(g, gr_ds_zbc_color_a_r(),
437 gr_ds_zbc_color_a_val_f(color_val->color_ds[3]));
438
439 gk20a_writel(g, gr_ds_zbc_color_fmt_r(),
440 gr_ds_zbc_color_fmt_val_f(color_val->format));
441
442 gk20a_writel(g, gr_ds_zbc_tbl_index_r(),
443 gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
444
445 /* trigger the write */
446 gk20a_writel(g, gr_ds_zbc_tbl_ld_r(),
447 gr_ds_zbc_tbl_ld_select_c_f() |
448 gr_ds_zbc_tbl_ld_action_write_f() |
449 gr_ds_zbc_tbl_ld_trigger_active_f());
450
451 /* update local copy */
452 for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) {
453 gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i];
454 gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i];
455 }
456 gr->zbc_col_tbl[index].format = color_val->format;
457 gr->zbc_col_tbl[index].ref_cnt++;
458
459 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index),
460 color_val->color_ds[0]);
461 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index),
462 color_val->color_ds[1]);
463 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index),
464 color_val->color_ds[2]);
465 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index),
466 color_val->color_ds[3]);
467 zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3));
468 zbc_c &= ~(0x7f << ((index % 4) * 7));
469 zbc_c |= color_val->format << ((index % 4) * 7);
470 gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c);
471
472 return 0;
473}
474
475static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr,
476 struct zbc_entry *depth_val, u32 index)
477{
478 u32 zbc_z;
479
480 /* update l2 table */
481 g->ops.ltc.set_zbc_depth_entry(g, depth_val, index);
482
483 /* update ds table */
484 gk20a_writel(g, gr_ds_zbc_z_r(),
485 gr_ds_zbc_z_val_f(depth_val->depth));
486
487 gk20a_writel(g, gr_ds_zbc_z_fmt_r(),
488 gr_ds_zbc_z_fmt_val_f(depth_val->format));
489
490 gk20a_writel(g, gr_ds_zbc_tbl_index_r(),
491 gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE));
492
493 /* trigger the write */
494 gk20a_writel(g, gr_ds_zbc_tbl_ld_r(),
495 gr_ds_zbc_tbl_ld_select_z_f() |
496 gr_ds_zbc_tbl_ld_action_write_f() |
497 gr_ds_zbc_tbl_ld_trigger_active_f());
498
499 /* update local copy */
500 gr->zbc_dep_tbl[index].depth = depth_val->depth;
501 gr->zbc_dep_tbl[index].format = depth_val->format;
502 gr->zbc_dep_tbl[index].ref_cnt++;
503
504 gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth);
505 zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3));
506 zbc_z &= ~(0x7f << (index % 4) * 7);
507 zbc_z |= depth_val->format << (index % 4) * 7;
508 gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z);
509
510 return 0;
511}
512
513static u32 gr_gp10b_pagepool_default_size(struct gk20a *g)
514{
515 return gr_scc_pagepool_total_pages_hwmax_value_v();
516}
517
518static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g)
519{
520 struct gr_gk20a *gr = &g->gr;
521 int size;
522
523 gr->attrib_cb_size = gr->attrib_cb_default_size;
524 gr->alpha_cb_size = gr->alpha_cb_default_size;
525
526 gr->attrib_cb_size = min(gr->attrib_cb_size,
527 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(~0) / g->gr.tpc_count);
528 gr->alpha_cb_size = min(gr->alpha_cb_size,
529 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(~0) / g->gr.tpc_count);
530
531 size = gr->attrib_cb_size *
532 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
533 gr->max_tpc_count;
534
535 size += gr->alpha_cb_size *
536 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() *
537 gr->max_tpc_count;
538
539 size = ALIGN(size, 128);
540
541 return size;
542}
543
544static void gr_gp10b_set_go_idle_timeout(struct gk20a *g, u32 data)
545{
546 gk20a_writel(g, gr_fe_go_idle_timeout_r(), data);
547}
548
549static void gr_gp10b_set_coalesce_buffer_size(struct gk20a *g, u32 data)
550{
551 u32 val;
552
553 gk20a_dbg_fn("");
554
555 val = gk20a_readl(g, gr_gpcs_tc_debug0_r());
556 val = set_field(val, gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(),
557 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(data));
558 gk20a_writel(g, gr_gpcs_tc_debug0_r(), val);
559
560 gk20a_dbg_fn("done");
561}
562
563static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr,
564 u32 class_num, u32 offset, u32 data)
565{
566 gk20a_dbg_fn("");
567
568 if (class_num == PASCAL_COMPUTE_A) {
569 switch (offset << 2) {
570 case NVC0C0_SET_SHADER_EXCEPTIONS:
571 gk20a_gr_set_shader_exceptions(g, data);
572 break;
573 default:
574 goto fail;
575 }
576 }
577
578 if (class_num == PASCAL_A) {
579 switch (offset << 2) {
580 case NVC097_SET_SHADER_EXCEPTIONS:
581 gk20a_gr_set_shader_exceptions(g, data);
582 break;
583 case NVC097_SET_CIRCULAR_BUFFER_SIZE:
584 g->ops.gr.set_circular_buffer_size(g, data);
585 break;
586 case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE:
587 g->ops.gr.set_alpha_circular_buffer_size(g, data);
588 break;
589 case NVC097_SET_GO_IDLE_TIMEOUT:
590 gr_gp10b_set_go_idle_timeout(g, data);
591 break;
592 case NVC097_SET_COALESCE_BUFFER_SIZE:
593 gr_gp10b_set_coalesce_buffer_size(g, data);
594 break;
595 default:
596 goto fail;
597 }
598 }
599 return 0;
600
601fail:
602 return -EINVAL;
603}
604
605static void gr_gp10b_cb_size_default(struct gk20a *g)
606{
607 struct gr_gk20a *gr = &g->gr;
608
609 if (!gr->attrib_cb_default_size)
610 gr->attrib_cb_default_size = 0x800;
611 gr->alpha_cb_default_size =
612 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
613}
614
615static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
616{
617 struct gr_gk20a *gr = &g->gr;
618 u32 gpc_index, ppc_index, stride, val;
619 u32 pd_ab_max_output;
620 u32 alpha_cb_size = data * 4;
621
622 gk20a_dbg_fn("");
623
624 if (alpha_cb_size > gr->alpha_cb_size)
625 alpha_cb_size = gr->alpha_cb_size;
626
627 gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(),
628 (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) &
629 ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~0)) |
630 gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size));
631
632 pd_ab_max_output = alpha_cb_size *
633 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() /
634 gr_pd_ab_dist_cfg1_max_output_granularity_v();
635
636 gk20a_writel(g, gr_pd_ab_dist_cfg1_r(),
637 gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) |
638 gr_pd_ab_dist_cfg1_max_batches_init_f());
639
640 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
641 stride = proj_gpc_stride_v() * gpc_index;
642
643 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
644 ppc_index++) {
645
646 val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
647 stride +
648 proj_ppc_in_gpc_stride_v() * ppc_index);
649
650 val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(),
651 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size *
652 gr->pes_tpc_count[ppc_index][gpc_index]));
653
654 gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() +
655 stride +
656 proj_ppc_in_gpc_stride_v() * ppc_index, val);
657 }
658 }
659}
660
661static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
662{
663 struct gr_gk20a *gr = &g->gr;
664 u32 gpc_index, ppc_index, stride, val;
665 u32 cb_size_steady = data * 4, cb_size;
666
667 gk20a_dbg_fn("");
668
669 if (cb_size_steady > gr->attrib_cb_size)
670 cb_size_steady = gr->attrib_cb_size;
671 if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) !=
672 gk20a_readl(g,
673 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) {
674 cb_size = cb_size_steady +
675 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
676 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
677 } else {
678 cb_size = cb_size_steady;
679 }
680
681 gk20a_writel(g, gr_ds_tga_constraintlogic_beta_r(),
682 (gk20a_readl(g, gr_ds_tga_constraintlogic_beta_r()) &
683 ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) |
684 gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady));
685
686 for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
687 stride = proj_gpc_stride_v() * gpc_index;
688
689 for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index];
690 ppc_index++) {
691
692 val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
693 stride +
694 proj_ppc_in_gpc_stride_v() * ppc_index);
695
696 val = set_field(val,
697 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(),
698 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size *
699 gr->pes_tpc_count[ppc_index][gpc_index]));
700
701 gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() +
702 stride +
703 proj_ppc_in_gpc_stride_v() * ppc_index, val);
704
705 gk20a_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index +
706 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() +
707 stride,
708 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(
709 cb_size_steady));
710
711 val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r(
712 ppc_index + gpc_index));
713
714 val = set_field(val,
715 gr_gpcs_swdx_tc_beta_cb_size_v_m(),
716 gr_gpcs_swdx_tc_beta_cb_size_v_f(
717 cb_size_steady *
718 gr->gpc_ppc_count[gpc_index]));
719
720 gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r(
721 ppc_index + gpc_index), val);
722 }
723 }
724}
725
726static int gr_gp10b_init_ctx_state(struct gk20a *g)
727{
728 struct fecs_method_op_gk20a op = {
729 .mailbox = { .id = 0, .data = 0,
730 .clr = ~0, .ok = 0, .fail = 0},
731 .method.data = 0,
732 .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL,
733 .cond.fail = GR_IS_UCODE_OP_SKIP,
734 };
735 int err;
736
737 gk20a_dbg_fn("");
738
739 err = gr_gk20a_init_ctx_state(g);
740 if (err)
741 return err;
742
743 if (!g->gr.t18x.ctx_vars.preempt_image_size) {
744 op.method.addr =
745 gr_fecs_method_push_adr_discover_preemption_image_size_v();
746 op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size;
747 err = gr_gk20a_submit_fecs_method_op(g, op, false);
748 if (err) {
749 gk20a_err(dev_from_gk20a(g),
750 "query preempt image size failed");
751 return err;
752 }
753 }
754
755 gk20a_dbg_info("preempt image size: %u",
756 g->gr.t18x.ctx_vars.preempt_image_size);
757
758 gk20a_dbg_fn("done");
759
760 return 0;
761}
762
763int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
764 struct mem_desc *mem)
765{
766 int err;
767
768 gk20a_dbg_fn("");
769
770 err = gk20a_gmmu_alloc_attr(vm->mm->g, 0, size, mem);
771 if (err)
772 return err;
773
774 mem->gpu_va = gk20a_gmmu_map(vm,
775 &mem->sgt,
776 size,
777 NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE,
778 gk20a_mem_flag_none,
779 false);
780
781 if (!mem->gpu_va) {
782 err = -ENOMEM;
783 goto fail_free;
784 }
785
786 return 0;
787
788fail_free:
789 gk20a_gmmu_free(vm->mm->g, mem);
790 return err;
791}
792
793static int gr_gp10b_alloc_gr_ctx(struct gk20a *g,
794 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
795 u32 class,
796 u32 flags)
797{
798 int err;
799
800 gk20a_dbg_fn("");
801
802 err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags);
803 if (err)
804 return err;
805
806 (*gr_ctx)->t18x.ctx_id_valid = false;
807
808 if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp)
809 flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP;
810
811 if (class == PASCAL_COMPUTE_A &&
812 g->gr.t18x.ctx_vars.force_preemption_cilp)
813 flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP;
814
815 if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) {
816 u32 spill_size =
817 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
818 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
819 u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
820 gr_scc_pagepool_total_pages_byte_granularity_v();
821 u32 betacb_size = g->gr.attrib_cb_default_size +
822 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
823 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
824 u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
825 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
826 g->gr.max_tpc_count;
827 attrib_cb_size = ALIGN(attrib_cb_size, 128);
828
829 gk20a_dbg_info("gfxp context spill_size=%d", spill_size);
830 gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size);
831 gk20a_dbg_info("gfxp context attrib_cb_size=%d",
832 attrib_cb_size);
833 err = gr_gp10b_alloc_buffer(vm,
834 g->gr.t18x.ctx_vars.preempt_image_size,
835 &(*gr_ctx)->t18x.preempt_ctxsw_buffer);
836 if (err) {
837 gk20a_err(dev_from_gk20a(vm->mm->g),
838 "cannot allocate preempt buffer");
839 goto fail_free_gk20a_ctx;
840 }
841
842 err = gr_gp10b_alloc_buffer(vm,
843 spill_size,
844 &(*gr_ctx)->t18x.spill_ctxsw_buffer);
845 if (err) {
846 gk20a_err(dev_from_gk20a(vm->mm->g),
847 "cannot allocate spill buffer");
848 goto fail_free_preempt;
849 }
850
851 err = gr_gp10b_alloc_buffer(vm,
852 attrib_cb_size,
853 &(*gr_ctx)->t18x.betacb_ctxsw_buffer);
854 if (err) {
855 gk20a_err(dev_from_gk20a(vm->mm->g),
856 "cannot allocate beta buffer");
857 goto fail_free_spill;
858 }
859
860 err = gr_gp10b_alloc_buffer(vm,
861 pagepool_size,
862 &(*gr_ctx)->t18x.pagepool_ctxsw_buffer);
863 if (err) {
864 gk20a_err(dev_from_gk20a(vm->mm->g),
865 "cannot allocate page pool");
866 goto fail_free_betacb;
867 }
868
869 (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP;
870 }
871
872 if (class == PASCAL_COMPUTE_A) {
873 if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP)
874 (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP;
875 else
876 (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA;
877 }
878
879 gk20a_dbg_fn("done");
880
881 return err;
882
883fail_free_betacb:
884 gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer);
885fail_free_spill:
886 gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer);
887fail_free_preempt:
888 gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer);
889fail_free_gk20a_ctx:
890 gr_gk20a_free_gr_ctx(g, vm, *gr_ctx);
891 *gr_ctx = NULL;
892
893 return err;
894}
895
896static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
897 struct gr_ctx_desc *gr_ctx) {
898 void *ctx_ptr = vmap(gr_ctx->mem.pages,
899 PAGE_ALIGN(gr_ctx->mem.size) >> PAGE_SHIFT,
900 0, pgprot_writecombine(PAGE_KERNEL));
901 if (!ctx_ptr) {
902 WARN_ON("Cannot map context");
903 return;
904 }
905 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n",
906 gk20a_mem_rd32(ctx_ptr +
907 ctxsw_prog_main_image_magic_value_o(), 0),
908 ctxsw_prog_main_image_magic_value_v_value_v());
909
910 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n",
911 gk20a_mem_rd32(ctx_ptr +
912 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(), 0));
913
914 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n",
915 gk20a_mem_rd32(ctx_ptr +
916 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), 0));
917
918 gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n",
919 gk20a_mem_rd32(ctx_ptr +
920 ctxsw_prog_main_image_context_timestamp_buffer_control_o(), 0));
921
922 gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n",
923 gk20a_mem_rd32(ctx_ptr +
924 ctxsw_prog_main_image_num_save_ops_o(), 0));
925 gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n",
926 gk20a_mem_rd32(ctx_ptr +
927 ctxsw_prog_main_image_num_wfi_save_ops_o(), 0));
928 gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n",
929 gk20a_mem_rd32(ctx_ptr +
930 ctxsw_prog_main_image_num_cta_save_ops_o(), 0));
931 gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n",
932 gk20a_mem_rd32(ctx_ptr +
933 ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0));
934 gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n",
935 gk20a_mem_rd32(ctx_ptr +
936 ctxsw_prog_main_image_num_cilp_save_ops_o(), 0));
937 gk20a_err(dev_from_gk20a(g),
938 "image gfx preemption option (GFXP is 1) %x\n",
939 gk20a_mem_rd32(ctx_ptr +
940 ctxsw_prog_main_image_graphics_preemption_options_o(),
941 0));
942 vunmap(ctx_ptr);
943}
944
945static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
946 struct gr_ctx_desc *gr_ctx)
947{
948 gk20a_dbg_fn("");
949
950 if (!gr_ctx)
951 return;
952
953 if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close)
954 dump_ctx_switch_stats(g, vm, gr_ctx);
955
956 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer);
957 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
958 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
959 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
960 gr_gk20a_free_gr_ctx(g, vm, gr_ctx);
961 gk20a_dbg_fn("done");
962}
963
964
965static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
966 struct channel_ctx_gk20a *ch_ctx,
967 void *ctx_ptr)
968{
969 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
970 u32 gfxp_preempt_option =
971 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f();
972 u32 cilp_preempt_option =
973 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f();
974 int err;
975
976 gk20a_dbg_fn("");
977
978 if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) {
979 gk20a_dbg_info("GfxP: %x", gfxp_preempt_option);
980 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0,
981 gfxp_preempt_option);
982 }
983
984 if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) {
985 gk20a_dbg_info("CILP: %x", cilp_preempt_option);
986 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0,
987 cilp_preempt_option);
988 }
989
990 if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) {
991 u32 addr;
992 u32 size;
993 u32 cbes_reserve;
994
995 gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_full_preemption_ptr_o(), 0,
996 gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8);
997
998 err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
999
1000 addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >>
1001 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) |
1002 (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) <<
1003 (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()));
1004
1005 gk20a_dbg_info("attrib cb addr : 0x%016x", addr);
1006 g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true);
1007
1008 addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >>
1009 gr_scc_pagepool_base_addr_39_8_align_bits_v()) |
1010 (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) <<
1011 (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v()));
1012 size = gr_ctx->t18x.pagepool_ctxsw_buffer.size;
1013
1014 if (size == g->ops.gr.pagepool_default_size(g))
1015 size = gr_scc_pagepool_total_pages_hwmax_v();
1016
1017 g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true);
1018
1019 addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >>
1020 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) |
1021 (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) <<
1022 (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()));
1023 size = gr_ctx->t18x.spill_ctxsw_buffer.size /
1024 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
1025
1026 gr_gk20a_ctx_patch_write(g, ch_ctx,
1027 gr_gpc0_swdx_rm_spill_buffer_addr_r(),
1028 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr),
1029 true);
1030 gr_gk20a_ctx_patch_write(g, ch_ctx,
1031 gr_gpc0_swdx_rm_spill_buffer_size_r(),
1032 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size),
1033 true);
1034
1035 cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v();
1036 gr_gk20a_ctx_patch_write(g, ch_ctx,
1037 gr_gpcs_swdx_beta_cb_ctrl_r(),
1038 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(
1039 cbes_reserve),
1040 true);
1041 gr_gk20a_ctx_patch_write(g, ch_ctx,
1042 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(),
1043 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(
1044 cbes_reserve),
1045 true);
1046
1047 gr_gk20a_ctx_patch_write_end(g, ch_ctx);
1048 }
1049
1050 gk20a_dbg_fn("done");
1051}
1052
1053static int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
1054 struct gk20a_debug_output *o)
1055{
1056 struct gr_gk20a *gr = &g->gr;
1057
1058 gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n",
1059 gk20a_readl(g, gr_status_r()));
1060 gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n",
1061 gk20a_readl(g, gr_status_1_r()));
1062 gk20a_debug_output(o, "NV_PGRAPH_STATUS2: 0x%x\n",
1063 gk20a_readl(g, gr_status_2_r()));
1064 gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n",
1065 gk20a_readl(g, gr_engine_status_r()));
1066 gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n",
1067 gk20a_readl(g, gr_gpfifo_status_r()));
1068 gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n",
1069 gk20a_readl(g, gr_gpfifo_ctl_r()));
1070 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n",
1071 gk20a_readl(g, gr_fecs_host_int_status_r()));
1072 gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION : 0x%x\n",
1073 gk20a_readl(g, gr_exception_r()));
1074 gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n",
1075 gk20a_readl(g, gr_fecs_intr_r()));
1076 gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n",
1077 gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A)));
1078 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n",
1079 gk20a_readl(g, gr_activity_0_r()));
1080 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n",
1081 gk20a_readl(g, gr_activity_1_r()));
1082 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY2: 0x%x\n",
1083 gk20a_readl(g, gr_activity_2_r()));
1084 gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n",
1085 gk20a_readl(g, gr_activity_4_r()));
1086 gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n",
1087 gk20a_readl(g, gr_pri_sked_activity_r()));
1088 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n",
1089 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r()));
1090 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n",
1091 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r()));
1092 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n",
1093 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r()));
1094 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n",
1095 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r()));
1096 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1097 gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r()));
1098 if (gr->gpc_tpc_count[0] == 2)
1099 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1100 gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r()));
1101 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1102 gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r()));
1103 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n",
1104 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r()));
1105 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n",
1106 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r()));
1107 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n",
1108 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r()));
1109 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n",
1110 gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r()));
1111 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1112 gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r()));
1113 if (gr->gpc_tpc_count[0] == 2)
1114 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1115 gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r()));
1116 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n",
1117 gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r()));
1118 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n",
1119 gk20a_readl(g, gr_pri_be0_becs_be_activity0_r()));
1120 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0: 0x%x\n",
1121 gk20a_readl(g, gr_pri_be1_becs_be_activity0_r()));
1122 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0: 0x%x\n",
1123 gk20a_readl(g, gr_pri_bes_becs_be_activity0_r()));
1124 gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n",
1125 gk20a_readl(g, gr_pri_ds_mpipe_status_r()));
1126 gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n",
1127 gk20a_readl(g, gr_fe_go_idle_timeout_r()));
1128 gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n",
1129 gk20a_readl(g, gr_pri_fe_go_idle_info_r()));
1130 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n",
1131 gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r()));
1132 gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
1133 gk20a_readl(g, gr_cwd_fs_r()));
1134 gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n",
1135 gk20a_readl(g, gr_fe_tpc_fs_r()));
1136 gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n",
1137 gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0)));
1138 gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
1139 gk20a_readl(g, gr_cwd_sm_id_r(0)));
1140 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n",
1141 gk20a_readl(g, gr_fecs_ctxsw_status_fe_0_r()));
1142 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n",
1143 gk20a_readl(g, gr_fecs_ctxsw_status_1_r()));
1144 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n",
1145 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r()));
1146 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n",
1147 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r()));
1148 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n",
1149 gk20a_readl(g, gr_fecs_ctxsw_idlestate_r()));
1150 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n",
1151 gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r()));
1152 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n",
1153 gk20a_readl(g, gr_fecs_current_ctx_r()));
1154 gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n",
1155 gk20a_readl(g, gr_fecs_new_ctx_r()));
1156 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n",
1157 gk20a_readl(g, gr_pri_be0_crop_status1_r()));
1158 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n",
1159 gk20a_readl(g, gr_pri_bes_crop_status1_r()));
1160 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS : 0x%x\n",
1161 gk20a_readl(g, gr_pri_be0_zrop_status_r()));
1162 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS2 : 0x%x\n",
1163 gk20a_readl(g, gr_pri_be0_zrop_status2_r()));
1164 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS : 0x%x\n",
1165 gk20a_readl(g, gr_pri_bes_zrop_status_r()));
1166 gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n",
1167 gk20a_readl(g, gr_pri_bes_zrop_status2_r()));
1168 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n",
1169 gk20a_readl(g, gr_pri_be0_becs_be_exception_r()));
1170 gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n",
1171 gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r()));
1172 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n",
1173 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r()));
1174 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n",
1175 gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r()));
1176 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n",
1177 gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r()));
1178 gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n",
1179 gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r()));
1180 return 0;
1181}
1182
1183static bool gr_activity_empty_or_preempted(u32 val)
1184{
1185 while(val) {
1186 u32 v = val & 7;
1187 if (v != gr_activity_4_gpc0_empty_v() &&
1188 v != gr_activity_4_gpc0_preempted_v())
1189 return false;
1190 val >>= 3;
1191 }
1192
1193 return true;
1194}
1195
1196static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long end_jiffies,
1197 u32 expect_delay)
1198{
1199 u32 delay = expect_delay;
1200 bool gr_enabled;
1201 bool ctxsw_active;
1202 bool gr_busy;
1203 u32 gr_status;
1204 u32 activity0, activity1, activity2, activity4;
1205
1206 gk20a_dbg_fn("");
1207
1208 do {
1209 /* fmodel: host gets fifo_engine_status(gr) from gr
1210 only when gr_status is read */
1211 gr_status = gk20a_readl(g, gr_status_r());
1212
1213 gr_enabled = gk20a_readl(g, mc_enable_r()) &
1214 mc_enable_pgraph_enabled_f();
1215
1216 ctxsw_active = gr_status & 1<<7;
1217
1218 activity0 = gk20a_readl(g, gr_activity_0_r());
1219 activity1 = gk20a_readl(g, gr_activity_1_r());
1220 activity2 = gk20a_readl(g, gr_activity_2_r());
1221 activity4 = gk20a_readl(g, gr_activity_4_r());
1222
1223 gr_busy = !(gr_activity_empty_or_preempted(activity0) &&
1224 gr_activity_empty_or_preempted(activity1) &&
1225 activity2 == 0 &&
1226 gr_activity_empty_or_preempted(activity4));
1227
1228 if (!gr_enabled || (!gr_busy && !ctxsw_active)) {
1229 gk20a_dbg_fn("done");
1230 return 0;
1231 }
1232
1233 usleep_range(delay, delay * 2);
1234 delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX);
1235
1236 } while (time_before(jiffies, end_jiffies)
1237 || !tegra_platform_is_silicon());
1238
1239 gk20a_err(dev_from_gk20a(g),
1240 "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x",
1241 ctxsw_active, gr_busy, activity0, activity1, activity2, activity4);
1242
1243 return -EAGAIN;
1244}
1245
1246static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
1247 struct channel_ctx_gk20a *ch_ctx,
1248 u64 addr, bool patch)
1249{
1250 struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
1251 int attrBufferSize;
1252
1253 if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va)
1254 attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size;
1255 else
1256 attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g);
1257
1258 attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f();
1259
1260 gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch);
1261
1262 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(),
1263 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) |
1264 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch);
1265
1266 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(),
1267 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch);
1268
1269 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(),
1270 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) |
1271 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch);
1272}
1273
1274static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g,
1275 struct channel_ctx_gk20a *ch_ctx,
1276 u64 addr, u64 size, bool patch)
1277{
1278 u32 data;
1279
1280 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(),
1281 gr_scc_bundle_cb_base_addr_39_8_f(addr), patch);
1282
1283 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(),
1284 gr_scc_bundle_cb_size_div_256b_f(size) |
1285 gr_scc_bundle_cb_size_valid_true_f(), patch);
1286
1287 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(),
1288 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch);
1289
1290 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(),
1291 gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) |
1292 gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch);
1293
1294 /* data for state_limit */
1295 data = (g->gr.bundle_cb_default_size *
1296 gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) /
1297 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v();
1298
1299 data = min_t(u32, data, g->gr.min_gpm_fifo_depth);
1300
1301 gk20a_dbg_info("bundle cb token limit : %d, state limit : %d",
1302 g->gr.bundle_cb_token_limit, data);
1303
1304 gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(),
1305 gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) |
1306 gr_pd_ab_dist_cfg2_state_limit_f(data), patch);
1307}
1308
1309static int gr_gp10b_init_fs_state(struct gk20a *g)
1310{
1311 u32 data;
1312
1313 data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r());
1314 data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(),
1315 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f());
1316 gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data);
1317
1318 data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r());
1319 data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(),
1320 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f());
1321 gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data);
1322
1323 return gr_gm20b_ctx_state_floorsweep(g);
1324}
1325
1326static void gr_gp10b_init_cyclestats(struct gk20a *g)
1327{
1328#if defined(CONFIG_GK20A_CYCLE_STATS)
1329 g->gpu_characteristics.flags |=
1330 NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS;
1331 g->gpu_characteristics.flags |=
1332 NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT;
1333#else
1334 (void)g;
1335#endif
1336}
1337
1338static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
1339{
1340 tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0);
1341 tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0);
1342
1343 if (g->gr.gpc_tpc_mask[gpc_index] == 0x1)
1344 tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0);
1345 else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2)
1346 tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
1347 else
1348 tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
1349}
1350
1351static void gr_gp10b_get_access_map(struct gk20a *g,
1352 u32 **whitelist, int *num_entries)
1353{
1354 static u32 wl_addr_gp10b[] = {
1355 /* this list must be sorted (low to high) */
1356 0x404468, /* gr_pri_mme_max_instructions */
1357 0x418300, /* gr_pri_gpcs_rasterarb_line_class */
1358 0x418800, /* gr_pri_gpcs_setup_debug */
1359 0x418e00, /* gr_pri_gpcs_swdx_config */
1360 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1361 0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1362 0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1363 0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1364 0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */
1365 0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1366 0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1367 0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1368 0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1369 0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1370 0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1371 0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1372 0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1373 0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1374 0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1375 0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1376 0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1377 0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1378 0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1379 0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1380 0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr */
1381 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */
1382 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */
1383 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */
1384 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */
1385 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */
1386 };
1387
1388 *whitelist = wl_addr_gp10b;
1389 *num_entries = ARRAY_SIZE(wl_addr_gp10b);
1390}
1391
1392static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch)
1393{
1394 int ret = 0;
1395
1396 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1397
1398 ret = gk20a_disable_channel_tsg(g, fault_ch);
1399 if (ret) {
1400 gk20a_err(dev_from_gk20a(g),
1401 "CILP: failed to disable channel/TSG!\n");
1402 return ret;
1403 }
1404
1405 ret = g->ops.fifo.update_runlist(g, 0, ~0, true, false);
1406 if (ret) {
1407 gk20a_err(dev_from_gk20a(g),
1408 "CILP: failed to restart runlist 0!");
1409 return ret;
1410 }
1411
1412 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist");
1413
1414 if (gk20a_is_channel_marked_as_tsg(fault_ch))
1415 gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true);
1416 else
1417 gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false);
1418
1419 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg");
1420
1421 return ret;
1422}
1423
1424static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch)
1425{
1426 int ret;
1427 struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx;
1428
1429 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1430
1431 if (!gr_ctx)
1432 return -EINVAL;
1433
1434 if (gr_ctx->t18x.cilp_preempt_pending) {
1435 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1436 "CILP is already pending for chid %d",
1437 fault_ch->hw_chid);
1438 return 0;
1439 }
1440
1441 /* get ctx_id from the ucode image */
1442 if (!gr_ctx->t18x.ctx_id_valid) {
1443 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1444 "CILP: looking up ctx id");
1445 ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id);
1446 if (ret) {
1447 gk20a_err(dev_from_gk20a(g), "CILP: error looking up ctx id!\n");
1448 return ret;
1449 }
1450 gr_ctx->t18x.ctx_id_valid = true;
1451 }
1452
1453 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1454 "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id);
1455
1456 /* send ucode method to set ctxsw interrupt */
1457 ret = gr_gk20a_submit_fecs_sideband_method_op(g,
1458 (struct fecs_method_op_gk20a) {
1459 .method.data = gr_ctx->t18x.ctx_id,
1460 .method.addr =
1461 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(),
1462 .mailbox = {
1463 .id = 1 /* sideband */, .data = 0,
1464 .clr = ~0, .ret = NULL,
1465 .ok = gr_fecs_ctxsw_mailbox_value_pass_v(),
1466 .fail = 0},
1467 .cond.ok = GR_IS_UCODE_OP_EQUAL,
1468 .cond.fail = GR_IS_UCODE_OP_SKIP});
1469
1470 if (ret) {
1471 gk20a_err(dev_from_gk20a(g),
1472 "CILP: failed to enable ctxsw interrupt!");
1473 return ret;
1474 }
1475
1476 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1477 "CILP: enabled ctxsw completion interrupt");
1478
1479 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1480 "CILP: disabling channel %d",
1481 fault_ch->hw_chid);
1482
1483 ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch);
1484 if (ret) {
1485 gk20a_err(dev_from_gk20a(g),
1486 "CILP: failed to disable channel!!");
1487 return ret;
1488 }
1489
1490 /* set cilp_preempt_pending = true and record the channel */
1491 gr_ctx->t18x.cilp_preempt_pending = true;
1492 g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid;
1493
1494 if (gk20a_is_channel_marked_as_tsg(fault_ch)) {
1495 struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid];
1496
1497 gk20a_tsg_event_id_post_event(tsg,
1498 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED);
1499 } else {
1500 gk20a_channel_event_id_post_event(fault_ch,
1501 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED);
1502 }
1503
1504 return 0;
1505}
1506
1507static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g,
1508 struct channel_gk20a *fault_ch)
1509{
1510 struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx;
1511
1512 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1513
1514 if (!gr_ctx)
1515 return -EINVAL;
1516
1517 /* The ucode is self-clearing, so all we need to do here is
1518 to clear cilp_preempt_pending. */
1519 if (!gr_ctx->t18x.cilp_preempt_pending) {
1520 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1521 "CILP is already cleared for chid %d\n",
1522 fault_ch->hw_chid);
1523 return 0;
1524 }
1525
1526 gr_ctx->t18x.cilp_preempt_pending = false;
1527 g->gr.t18x.cilp_preempt_pending_chid = -1;
1528
1529 return 0;
1530}
1531
1532/* @brief pre-process work on the SM exceptions to determine if we clear them or not.
1533 *
1534 * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing
1535 */
1536static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
1537 u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr,
1538 bool sm_debugger_attached, struct channel_gk20a *fault_ch,
1539 bool *early_exit, bool *ignore_debugger)
1540{
1541 int ret;
1542 bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode ==
1543 NVGPU_GR_PREEMPTION_MODE_CILP) ;
1544 u32 global_mask = 0, dbgr_control0, global_esr_copy;
1545 u32 offset = proj_gpc_stride_v() * gpc +
1546 proj_tpc_in_gpc_stride_v() * tpc;
1547
1548 *early_exit = false;
1549 *ignore_debugger = false;
1550
1551 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n",
1552 gpc, tpc, global_esr);
1553
1554 if (cilp_enabled && sm_debugger_attached) {
1555 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f())
1556 gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
1557 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
1558
1559 if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f())
1560 gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
1561 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f());
1562
1563 global_mask = gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() |
1564 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() |
1565 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() |
1566 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f() |
1567 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() |
1568 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
1569
1570 if (warp_esr != 0 || (global_esr & global_mask) != 0) {
1571 *ignore_debugger = true;
1572
1573 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1574 "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n",
1575 gpc, tpc);
1576
1577 if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) {
1578 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1579 "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n",
1580 gpc, tpc);
1581 gk20a_suspend_all_sms(g, global_mask, false);
1582
1583 gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch);
1584 } else {
1585 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1586 "CILP: STOP_TRIGGER from gpc %d tpc %d\n",
1587 gpc, tpc);
1588 gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true);
1589 }
1590
1591 /* reset the HWW errors after locking down */
1592 global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
1593 gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
1594 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1595 "CILP: HWWs cleared for gpc %d tpc %d\n",
1596 gpc, tpc);
1597
1598 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n");
1599 ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch);
1600 if (ret) {
1601 gk20a_err(dev_from_gk20a(g), "CILP: error while setting CILP preempt pending!\n");
1602 return ret;
1603 }
1604
1605 dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset);
1606 if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) {
1607 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1608 "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n",
1609 gpc, tpc);
1610 dbgr_control0 = set_field(dbgr_control0,
1611 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(),
1612 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f());
1613 gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
1614 }
1615
1616 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
1617 "CILP: resume for gpc %d tpc %d\n",
1618 gpc, tpc);
1619 gk20a_resume_single_sm(g, gpc, tpc);
1620
1621 *ignore_debugger = true;
1622 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc);
1623 }
1624
1625 *early_exit = true;
1626 }
1627 return 0;
1628}
1629
1630static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid)
1631{
1632 struct gr_ctx_desc *gr_ctx;
1633 struct channel_gk20a *ch;
1634 int chid;
1635 int ret = -EINVAL;
1636
1637 chid = g->gr.t18x.cilp_preempt_pending_chid;
1638
1639 ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid));
1640 if (!ch)
1641 return ret;
1642
1643 gr_ctx = ch->ch_ctx.gr_ctx;
1644
1645 if (gr_ctx->t18x.cilp_preempt_pending) {
1646 *__chid = chid;
1647 ret = 0;
1648 }
1649
1650 gk20a_channel_put(ch);
1651
1652 return ret;
1653}
1654
1655static int gr_gp10b_handle_fecs_error(struct gk20a *g,
1656 struct channel_gk20a *__ch,
1657 struct gr_gk20a_isr_data *isr_data)
1658{
1659 u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r());
1660 struct channel_gk20a *ch;
1661 int chid = -1;
1662 int ret = 0;
1663
1664 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "");
1665
1666 /*
1667 * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR)
1668 * indicates that a CILP ctxsw save has finished
1669 */
1670 if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) {
1671 gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
1672 "CILP: ctxsw save completed!\n");
1673
1674 /* now clear the interrupt */
1675 gk20a_writel(g, gr_fecs_host_int_clear_r(),
1676 gr_fecs_host_int_clear_ctxsw_intr1_clear_f());
1677
1678 ret = gr_gp10b_get_cilp_preempt_pending_chid(g, &chid);
1679 if (ret)
1680 goto clean_up;
1681
1682 ch = gk20a_channel_get(
1683 gk20a_fifo_channel_from_hw_chid(g, chid));
1684 if (!ch)
1685 goto clean_up;
1686
1687
1688 /* set preempt_pending to false */
1689 ret = gr_gp10b_clear_cilp_preempt_pending(g, ch);
1690 if (ret) {
1691 gk20a_err(dev_from_gk20a(g), "CILP: error while unsetting CILP preempt pending!\n");
1692 gk20a_channel_put(ch);
1693 goto clean_up;
1694 }
1695
1696 if (gk20a_gr_sm_debugger_attached(g)) {
1697 if (gk20a_is_channel_marked_as_tsg(ch)) {
1698 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
1699 struct channel_gk20a *__ch;
1700
1701 mutex_lock(&tsg->ch_list_lock);
1702 list_for_each_entry(__ch, &tsg->ch_list, ch_entry) {
1703 gk20a_dbg_gpu_post_events(__ch);
1704 }
1705 mutex_unlock(&tsg->ch_list_lock);
1706
1707 gk20a_tsg_event_id_post_event(tsg,
1708 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
1709 } else {
1710 gk20a_dbg_gpu_post_events(ch);
1711
1712 gk20a_channel_event_id_post_event(ch,
1713 NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE);
1714 }
1715 }
1716
1717 gk20a_channel_put(ch);
1718 }
1719
1720clean_up:
1721 /* handle any remaining interrupts */
1722 return gk20a_gr_handle_fecs_error(g, __ch, isr_data);
1723}
1724
1725static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr)
1726{
1727 if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
1728 hww_warp_esr = set_field(hww_warp_esr,
1729 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
1730 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f());
1731
1732 return hww_warp_esr;
1733}
1734
1735static u32 get_ecc_override_val(struct gk20a *g)
1736{
1737 if (tegra_fuse_readl(FUSE_OPT_ECC_EN))
1738 return gk20a_readl(g, gr_fecs_feature_override_ecc_r());
1739 else
1740 return 0;
1741}
1742
1743void gp10b_init_gr(struct gpu_ops *gops)
1744{
1745 gm20b_init_gr(gops);
1746 gops->gr.init_fs_state = gr_gp10b_init_fs_state;
1747 gops->gr.is_valid_class = gr_gp10b_is_valid_class;
1748 gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager;
1749 gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool;
1750 gops->gr.add_zbc_color = gr_gp10b_add_zbc_color;
1751 gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth;
1752 gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size;
1753 gops->gr.calc_global_ctx_buffer_size =
1754 gr_gp10b_calc_global_ctx_buffer_size;
1755 gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb;
1756 gops->gr.commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb;
1757 gops->gr.handle_sw_method = gr_gp10b_handle_sw_method;
1758 gops->gr.cb_size_default = gr_gp10b_cb_size_default;
1759 gops->gr.set_alpha_circular_buffer_size =
1760 gr_gp10b_set_alpha_circular_buffer_size;
1761 gops->gr.set_circular_buffer_size =
1762 gr_gp10b_set_circular_buffer_size;
1763 gops->gr.init_ctx_state = gr_gp10b_init_ctx_state;
1764 gops->gr.alloc_gr_ctx = gr_gp10b_alloc_gr_ctx;
1765 gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx;
1766 gops->gr.update_ctxsw_preemption_mode =
1767 gr_gp10b_update_ctxsw_preemption_mode;
1768 gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs;
1769 gops->gr.wait_empty = gr_gp10b_wait_empty;
1770 gops->gr.init_cyclestats = gr_gp10b_init_cyclestats;
1771 gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask;
1772 gops->gr.get_access_map = gr_gp10b_get_access_map;
1773 gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception;
1774 gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception;
1775 gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr;
1776 gops->gr.pre_process_sm_exception =
1777 gr_gp10b_pre_process_sm_exception;
1778 gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error;
1779 gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs;
1780 gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val;
1781}
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
deleted file mode 100644
index bd4b5879a..000000000
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * GM20B GPU GR
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GR_GP10B_H_
17#define _NVGPU_GR_GP10B_H_
18
19struct gpu_ops;
20
21enum {
22 PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
23 PASCAL_A = 0xC097,
24 PASCAL_COMPUTE_A = 0xC0C0,
25 PASCAL_DMA_COPY_A = 0xC0B5,
26};
27
28#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
29#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
30#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
31#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
32#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
33#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
34
35void gp10b_init_gr(struct gpu_ops *ops);
36int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
37 struct mem_desc *mem);
38void gr_gp10b_create_sysfs(struct platform_device *dev);
39
40struct ecc_stat {
41 char **names;
42 u32 *counters;
43 struct hlist_node hash_node;
44};
45
46struct gr_t18x {
47 struct {
48 u32 preempt_image_size;
49 u32 force_preemption_gfxp;
50 u32 force_preemption_cilp;
51 u32 dump_ctxsw_stats_on_channel_close;
52 struct dentry *debugfs_force_preemption_cilp;
53 struct dentry *debugfs_force_preemption_gfxp;
54 struct dentry *debugfs_dump_ctxsw_stats;
55 } ctx_vars;
56
57 struct {
58 struct ecc_stat sm_lrf_single_err_count;
59 struct ecc_stat sm_lrf_double_err_count;
60
61 struct ecc_stat sm_shm_sec_count;
62 struct ecc_stat sm_shm_sed_count;
63 struct ecc_stat sm_shm_ded_count;
64
65 struct ecc_stat tex_total_sec_pipe0_count;
66 struct ecc_stat tex_total_ded_pipe0_count;
67 struct ecc_stat tex_unique_sec_pipe0_count;
68 struct ecc_stat tex_unique_ded_pipe0_count;
69 struct ecc_stat tex_total_sec_pipe1_count;
70 struct ecc_stat tex_total_ded_pipe1_count;
71 struct ecc_stat tex_unique_sec_pipe1_count;
72 struct ecc_stat tex_unique_ded_pipe1_count;
73
74 struct ecc_stat l2_sec_count;
75 struct ecc_stat l2_ded_count;
76 } ecc_stats;
77
78 int cilp_preempt_pending_chid;
79};
80
81struct gr_ctx_desc_t18x {
82 struct mem_desc preempt_ctxsw_buffer;
83 struct mem_desc spill_ctxsw_buffer;
84 struct mem_desc betacb_ctxsw_buffer;
85 struct mem_desc pagepool_ctxsw_buffer;
86 u32 ctx_id;
87 bool ctx_id_valid;
88 bool cilp_preempt_pending;
89};
90
91#define NVGPU_GR_PREEMPTION_MODE_GFXP 1
92#define NVGPU_GR_PREEMPTION_MODE_CILP 3
93
94#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h
deleted file mode 100644
index c32770178..000000000
--- a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * GP10B GPU graphics ops
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _GR_OPS_GP10B_H_
17#define _GR_OPS_GP10B_H_
18
19#include "gr_ops.h"
20
21#define __gr_gp10b_op(X) gr_gp10b_ ## X
22#define __set_gr_gp10b_op(X) . X = gr_gp10b_ ## X
23
24bool __gr_gp10b_op(is_valid_class)(struct gk20a *, u32);
25int __gr_gp10b_op(alloc_obj_ctx)(struct channel_gk20a *, struct nvgpu_alloc_obj_ctx_args *);
26
27
28#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
deleted file mode 100644
index 427936c72..000000000
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ /dev/null
@@ -1,168 +0,0 @@
1/*
2 * GP10B Tegra HAL interface
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/printk.h>
18
19#include <linux/types.h>
20
21#include "gk20a/gk20a.h"
22
23#include "gp10b/gr_gp10b.h"
24#include "gp10b/fecs_trace_gp10b.h"
25#include "gp10b/mc_gp10b.h"
26#include "gp10b/ltc_gp10b.h"
27#include "gp10b/mm_gp10b.h"
28#include "gp10b/ce2_gp10b.h"
29#include "gp10b/fb_gp10b.h"
30#include "gp10b/pmu_gp10b.h"
31#include "gp10b/gr_ctx_gp10b.h"
32#include "gp10b/fifo_gp10b.h"
33#include "gp10b/gp10b_gating_reglist.h"
34#include "gp10b/regops_gp10b.h"
35#include "gp10b/cde_gp10b.h"
36#include "gp10b/therm_gp10b.h"
37
38#include "gm20b/gr_gm20b.h"
39#include "gm20b/fifo_gm20b.h"
40#include "gm20b/pmu_gm20b.h"
41#include "gm20b/clk_gm20b.h"
42#include <linux/tegra-fuse.h>
43
44#include "gp10b.h"
45
46#define FUSE_OPT_PRIV_SEC_EN_0 0x264
47#define PRIV_SECURITY_ENABLED 0x01
48
49static struct gpu_ops gp10b_ops = {
50 .clock_gating = {
51 .slcg_bus_load_gating_prod =
52 gp10b_slcg_bus_load_gating_prod,
53 .slcg_ce2_load_gating_prod =
54 gp10b_slcg_ce2_load_gating_prod,
55 .slcg_chiplet_load_gating_prod =
56 gp10b_slcg_chiplet_load_gating_prod,
57 .slcg_ctxsw_firmware_load_gating_prod =
58 gp10b_slcg_ctxsw_firmware_load_gating_prod,
59 .slcg_fb_load_gating_prod =
60 gp10b_slcg_fb_load_gating_prod,
61 .slcg_fifo_load_gating_prod =
62 gp10b_slcg_fifo_load_gating_prod,
63 .slcg_gr_load_gating_prod =
64 gr_gp10b_slcg_gr_load_gating_prod,
65 .slcg_ltc_load_gating_prod =
66 ltc_gp10b_slcg_ltc_load_gating_prod,
67 .slcg_perf_load_gating_prod =
68 gp10b_slcg_perf_load_gating_prod,
69 .slcg_priring_load_gating_prod =
70 gp10b_slcg_priring_load_gating_prod,
71 .slcg_pmu_load_gating_prod =
72 gp10b_slcg_pmu_load_gating_prod,
73 .slcg_therm_load_gating_prod =
74 gp10b_slcg_therm_load_gating_prod,
75 .slcg_xbar_load_gating_prod =
76 gp10b_slcg_xbar_load_gating_prod,
77 .blcg_bus_load_gating_prod =
78 gp10b_blcg_bus_load_gating_prod,
79 .blcg_ce_load_gating_prod =
80 gp10b_blcg_ce_load_gating_prod,
81 .blcg_ctxsw_firmware_load_gating_prod =
82 gp10b_blcg_ctxsw_firmware_load_gating_prod,
83 .blcg_fb_load_gating_prod =
84 gp10b_blcg_fb_load_gating_prod,
85 .blcg_fifo_load_gating_prod =
86 gp10b_blcg_fifo_load_gating_prod,
87 .blcg_gr_load_gating_prod =
88 gp10b_blcg_gr_load_gating_prod,
89 .blcg_ltc_load_gating_prod =
90 gp10b_blcg_ltc_load_gating_prod,
91 .blcg_pwr_csb_load_gating_prod =
92 gp10b_blcg_pwr_csb_load_gating_prod,
93 .blcg_pmu_load_gating_prod =
94 gp10b_blcg_pmu_load_gating_prod,
95 .blcg_xbar_load_gating_prod =
96 gp10b_blcg_xbar_load_gating_prod,
97 .pg_gr_load_gating_prod =
98 gr_gp10b_pg_gr_load_gating_prod,
99 }
100};
101
102int gp10b_init_hal(struct gk20a *g)
103{
104 struct gpu_ops *gops = &g->ops;
105 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
106
107 *gops = gp10b_ops;
108
109#ifdef CONFIG_TEGRA_ACR
110 if (tegra_platform_is_linsim()) {
111 gops->privsecurity = 0;
112 gops->securegpccs = 0;
113 } else {
114 if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
115 PRIV_SECURITY_ENABLED) {
116 gops->privsecurity = 1;
117 gops->securegpccs =1;
118 } else {
119 gk20a_dbg_info("priv security is disabled in HW");
120 gops->privsecurity = 0;
121 gops->securegpccs = 0;
122 }
123 }
124#else
125 if (tegra_platform_is_linsim()) {
126 gk20a_dbg_info("running ASIM with PRIV security disabled");
127 gops->privsecurity = 0;
128 gops->securegpccs = 0;
129 } else {
130 if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) &
131 PRIV_SECURITY_ENABLED) {
132 gk20a_dbg_info("priv security is not supported but enabled");
133 gops->privsecurity = 1;
134 gops->securegpccs =1;
135 return -EPERM;
136 } else {
137 gops->privsecurity = 0;
138 gops->securegpccs = 0;
139 }
140 }
141#endif
142
143 gp10b_init_mc(gops);
144 gp10b_init_gr(gops);
145 gp10b_init_fecs_trace_ops(gops);
146 gp10b_init_ltc(gops);
147 gp10b_init_fb(gops);
148 gp10b_init_fifo(gops);
149 gp10b_init_ce2(gops);
150 gp10b_init_gr_ctx(gops);
151 gp10b_init_mm(gops);
152 gp10b_init_pmu_ops(gops);
153 gk20a_init_debug_ops(gops);
154 gp10b_init_regops(gops);
155 gp10b_init_cde_ops(gops);
156 gp10b_init_therm_ops(gops);
157 gops->name = "gp10b";
158 gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics;
159
160 c->twod_class = FERMI_TWOD_A;
161 c->threed_class = PASCAL_A;
162 c->compute_class = PASCAL_COMPUTE_A;
163 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
164 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
165 c->dma_copy_class = PASCAL_DMA_COPY_A;
166
167 return 0;
168}
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
deleted file mode 100644
index 0b464d07c..000000000
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * GP10B Tegra HAL interface
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_HAL_GP10B_H
17#define _NVGPU_HAL_GP10B_H
18struct gk20a;
19
20int gp10b_init_hal(struct gk20a *gops);
21#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h
deleted file mode 100644
index c04b01c1f..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_bus_gp10b_h_
51#define _hw_bus_gp10b_h_
52
53static inline u32 bus_bar1_block_r(void)
54{
55 return 0x00001704;
56}
57static inline u32 bus_bar1_block_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 bus_bar1_block_target_vid_mem_f(void)
62{
63 return 0x0;
64}
65static inline u32 bus_bar1_block_mode_virtual_f(void)
66{
67 return 0x80000000;
68}
69static inline u32 bus_bar2_block_r(void)
70{
71 return 0x00001714;
72}
73static inline u32 bus_bar2_block_ptr_f(u32 v)
74{
75 return (v & 0xfffffff) << 0;
76}
77static inline u32 bus_bar2_block_target_vid_mem_f(void)
78{
79 return 0x0;
80}
81static inline u32 bus_bar2_block_mode_virtual_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 bus_bar1_block_ptr_shift_v(void)
86{
87 return 0x0000000c;
88}
89static inline u32 bus_bar2_block_ptr_shift_v(void)
90{
91 return 0x0000000c;
92}
93static inline u32 bus_intr_0_r(void)
94{
95 return 0x00001100;
96}
97static inline u32 bus_intr_0_pri_squash_m(void)
98{
99 return 0x1 << 1;
100}
101static inline u32 bus_intr_0_pri_fecserr_m(void)
102{
103 return 0x1 << 2;
104}
105static inline u32 bus_intr_0_pri_timeout_m(void)
106{
107 return 0x1 << 3;
108}
109static inline u32 bus_intr_en_0_r(void)
110{
111 return 0x00001140;
112}
113static inline u32 bus_intr_en_0_pri_squash_m(void)
114{
115 return 0x1 << 1;
116}
117static inline u32 bus_intr_en_0_pri_fecserr_m(void)
118{
119 return 0x1 << 2;
120}
121static inline u32 bus_intr_en_0_pri_timeout_m(void)
122{
123 return 0x1 << 3;
124}
125#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h
deleted file mode 100644
index cd5265b33..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ccsr_gp10b_h_
51#define _hw_ccsr_gp10b_h_
52
53static inline u32 ccsr_channel_inst_r(u32 i)
54{
55 return 0x00800000 + i*8;
56}
57static inline u32 ccsr_channel_inst__size_1_v(void)
58{
59 return 0x00000200;
60}
61static inline u32 ccsr_channel_inst_ptr_f(u32 v)
62{
63 return (v & 0xfffffff) << 0;
64}
65static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
66{
67 return 0x0;
68}
69static inline u32 ccsr_channel_inst_bind_false_f(void)
70{
71 return 0x0;
72}
73static inline u32 ccsr_channel_inst_bind_true_f(void)
74{
75 return 0x80000000;
76}
77static inline u32 ccsr_channel_r(u32 i)
78{
79 return 0x00800004 + i*8;
80}
81static inline u32 ccsr_channel__size_1_v(void)
82{
83 return 0x00000200;
84}
85static inline u32 ccsr_channel_enable_v(u32 r)
86{
87 return (r >> 0) & 0x1;
88}
89static inline u32 ccsr_channel_enable_set_f(u32 v)
90{
91 return (v & 0x1) << 10;
92}
93static inline u32 ccsr_channel_enable_set_true_f(void)
94{
95 return 0x400;
96}
97static inline u32 ccsr_channel_enable_clr_true_f(void)
98{
99 return 0x800;
100}
101static inline u32 ccsr_channel_status_v(u32 r)
102{
103 return (r >> 24) & 0xf;
104}
105static inline u32 ccsr_channel_busy_v(u32 r)
106{
107 return (r >> 28) & 0x1;
108}
109#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h
deleted file mode 100644
index b0c35a302..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ce2_gp10b_h_
51#define _hw_ce2_gp10b_h_
52
53static inline u32 ce2_intr_status_r(u32 i)
54{
55 return 0x00104410 + i*128;
56}
57static inline u32 ce2_intr_status_blockpipe_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 ce2_intr_status_blockpipe_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 ce2_intr_status_launcherr_pending_f(void)
74{
75 return 0x4;
76}
77static inline u32 ce2_intr_status_launcherr_reset_f(void)
78{
79 return 0x4;
80}
81#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h
deleted file mode 100644
index 640453ceb..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_chiplet_pwr_gp10b_h_
51#define _hw_chiplet_pwr_gp10b_h_
52
53static inline u32 chiplet_pwr_gpcs_weight_6_r(void)
54{
55 return 0x0010e018;
56}
57static inline u32 chiplet_pwr_gpcs_weight_7_r(void)
58{
59 return 0x0010e01c;
60}
61static inline u32 chiplet_pwr_gpcs_config_1_r(void)
62{
63 return 0x0010e03c;
64}
65static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void)
66{
67 return 0x1;
68}
69static inline u32 chiplet_pwr_fbps_weight_0_r(void)
70{
71 return 0x0010e100;
72}
73static inline u32 chiplet_pwr_fbps_weight_1_r(void)
74{
75 return 0x0010e104;
76}
77static inline u32 chiplet_pwr_fbps_config_1_r(void)
78{
79 return 0x0010e13c;
80}
81static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void)
82{
83 return 0x1;
84}
85#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h
deleted file mode 100644
index eef9a96fd..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h
+++ /dev/null
@@ -1,473 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ctxsw_prog_gp10b_h_
51#define _hw_ctxsw_prog_gp10b_h_
52
53static inline u32 ctxsw_prog_fecs_header_v(void)
54{
55 return 0x00000100;
56}
57static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
58{
59 return 0x00000008;
60}
61static inline u32 ctxsw_prog_main_image_patch_count_o(void)
62{
63 return 0x00000010;
64}
65static inline u32 ctxsw_prog_main_image_context_id_o(void)
66{
67 return 0x000000f0;
68}
69static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
70{
71 return 0x00000014;
72}
73static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
74{
75 return 0x00000018;
76}
77static inline u32 ctxsw_prog_main_image_zcull_o(void)
78{
79 return 0x0000001c;
80}
81static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
82{
83 return 0x00000001;
84}
85static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
86{
87 return 0x00000002;
88}
89static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
90{
91 return 0x00000020;
92}
93static inline u32 ctxsw_prog_main_image_pm_o(void)
94{
95 return 0x00000028;
96}
97static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
98{
99 return 0x7 << 0;
100}
101static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
102{
103 return 0x0;
104}
105static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
106{
107 return 0x7 << 3;
108}
109static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
110{
111 return 0x8;
112}
113static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
114{
115 return 0x0;
116}
117static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
118{
119 return 0x0000002c;
120}
121static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
122{
123 return 0x000000f4;
124}
125static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
126{
127 return 0x000000d0;
128}
129static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
130{
131 return 0x000000d4;
132}
133static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
134{
135 return 0x000000d8;
136}
137static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
138{
139 return 0x000000dc;
140}
141static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
142{
143 return 0x000000f8;
144}
145static inline u32 ctxsw_prog_main_image_magic_value_o(void)
146{
147 return 0x000000fc;
148}
149static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
150{
151 return 0x600dc0de;
152}
153static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
154{
155 return 0x0000000c;
156}
157static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
158{
159 return (r >> 0) & 0xffff;
160}
161static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
162{
163 return 0x000000f4;
164}
165static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
166{
167 return (r >> 0) & 0xffff;
168}
169static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
170{
171 return (r >> 16) & 0xffff;
172}
173static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
174{
175 return 0x000000f8;
176}
177static inline u32 ctxsw_prog_local_magic_value_o(void)
178{
179 return 0x000000fc;
180}
181static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
182{
183 return 0xad0becab;
184}
185static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
186{
187 return 0x000000ec;
188}
189static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
190{
191 return (r >> 0) & 0xffff;
192}
193static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
194{
195 return (r >> 16) & 0xff;
196}
197static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
198{
199 return 0x00000100;
200}
201static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
202{
203 return 0x00000004;
204}
205static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
206{
207 return 0x00000000;
208}
209static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
210{
211 return 0x00000002;
212}
213static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
214{
215 return 0x000000a0;
216}
217static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
218{
219 return 2;
220}
221static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
222{
223 return (v & 0x3) << 0;
224}
225static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
226{
227 return 0x3 << 0;
228}
229static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
230{
231 return (r >> 0) & 0x3;
232}
233static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
234{
235 return 0x0;
236}
237static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
238{
239 return 0x2;
240}
241static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
242{
243 return 0x000000a4;
244}
245static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
246{
247 return 0x000000a8;
248}
249static inline u32 ctxsw_prog_main_image_misc_options_o(void)
250{
251 return 0x0000003c;
252}
253static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
254{
255 return 0x1 << 3;
256}
257static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
258{
259 return 0x0;
260}
261static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
262{
263 return 0x00000080;
264}
265static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
266{
267 return (v & 0x3) << 0;
268}
269static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
270{
271 return 0x1;
272}
273static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
274{
275 return 0x00000068;
276}
277static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
278{
279 return 0x00000084;
280}
281static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
282{
283 return (v & 0x3) << 0;
284}
285static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
286{
287 return 0x1;
288}
289static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
290{
291 return 0x2;
292}
293static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
294{
295 return 0x000000ac;
296}
297static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
298{
299 return (v & 0xffff) << 0;
300}
301static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
302{
303 return 0x000000b0;
304}
305static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
306{
307 return 0xfffffff << 0;
308}
309static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
310{
311 return 0x3 << 28;
312}
313static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
314{
315 return 0x0;
316}
317static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
318{
319 return 0x20000000;
320}
321static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
322{
323 return 0x30000000;
324}
325static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
326{
327 return 0x000000b4;
328}
329static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
330{
331 return (v & 0xffffffff) << 0;
332}
333static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
334{
335 return 0x00000080;
336}
337static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
338{
339 return 0x00000020;
340}
341static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
342{
343 return 0x00000000;
344}
345static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
346{
347 return 0x00000000;
348}
349static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
350{
351 return 0x00000004;
352}
353static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
354{
355 return 0x600dbeef;
356}
357static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
358{
359 return 0x00000008;
360}
361static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
362{
363 return 0x0000000c;
364}
365static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
366{
367 return 0x00000018;
368}
369static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
370{
371 return 0x0000001c;
372}
373static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
374{
375 return (v & 0xffffff) << 0;
376}
377static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
378{
379 return (r >> 0) & 0xffffff;
380}
381static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
382{
383 return (v & 0xff) << 24;
384}
385static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
386{
387 return 0xff << 24;
388}
389static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
390{
391 return (r >> 24) & 0xff;
392}
393static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
394{
395 return 0x00000001;
396}
397static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
398{
399 return 0x1000000;
400}
401static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
402{
403 return 0x00000002;
404}
405static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
406{
407 return 0x2000000;
408}
409static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
410{
411 return 0x0000000a;
412}
413static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
414{
415 return 0xa000000;
416}
417static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
418{
419 return 0x0000000b;
420}
421static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
422{
423 return 0xb000000;
424}
425static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
426{
427 return 0x0000000c;
428}
429static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
430{
431 return 0xc000000;
432}
433static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
434{
435 return 0x0000000d;
436}
437static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
438{
439 return 0xd000000;
440}
441static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
442{
443 return 0x00000003;
444}
445static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
446{
447 return 0x3000000;
448}
449static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
450{
451 return 0x00000004;
452}
453static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
454{
455 return 0x4000000;
456}
457static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
458{
459 return 0x00000005;
460}
461static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
462{
463 return 0x5000000;
464}
465static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
466{
467 return 0x000000ff;
468}
469static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
470{
471 return 0xff000000;
472}
473#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h
deleted file mode 100644
index 1fee19b14..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h
+++ /dev/null
@@ -1,457 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fb_gp10b_h_
51#define _hw_fb_gp10b_h_
52
53static inline u32 fb_fbhub_num_active_ltcs_r(void)
54{
55 return 0x00100800;
56}
57static inline u32 fb_mmu_ctrl_r(void)
58{
59 return 0x00100c80;
60}
61static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
62{
63 return (v & 0x1) << 0;
64}
65static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
66{
67 return 0x0;
68}
69static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
70{
71 return 0x1;
72}
73static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
74{
75 return (r >> 15) & 0x1;
76}
77static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
78{
79 return 0x0;
80}
81static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
82{
83 return (r >> 16) & 0xff;
84}
85static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
86{
87 return (r >> 11) & 0x1;
88}
89static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
90{
91 return 0x800;
92}
93static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
94{
95 return 0x0;
96}
97static inline u32 fb_priv_mmu_phy_secure_r(void)
98{
99 return 0x00100ce4;
100}
101static inline u32 fb_mmu_invalidate_pdb_r(void)
102{
103 return 0x00100cb8;
104}
105static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
106{
107 return 0x0;
108}
109static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
110{
111 return (v & 0xfffffff) << 4;
112}
113static inline u32 fb_mmu_invalidate_r(void)
114{
115 return 0x00100cbc;
116}
117static inline u32 fb_mmu_invalidate_all_va_true_f(void)
118{
119 return 0x1;
120}
121static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
122{
123 return 0x2;
124}
125static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
126{
127 return 1;
128}
129static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
130{
131 return (v & 0x1) << 2;
132}
133static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
134{
135 return 0x1 << 2;
136}
137static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
138{
139 return (r >> 2) & 0x1;
140}
141static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
142{
143 return 0x4;
144}
145static inline u32 fb_mmu_invalidate_replay_s(void)
146{
147 return 3;
148}
149static inline u32 fb_mmu_invalidate_replay_f(u32 v)
150{
151 return (v & 0x7) << 3;
152}
153static inline u32 fb_mmu_invalidate_replay_m(void)
154{
155 return 0x7 << 3;
156}
157static inline u32 fb_mmu_invalidate_replay_v(u32 r)
158{
159 return (r >> 3) & 0x7;
160}
161static inline u32 fb_mmu_invalidate_replay_none_f(void)
162{
163 return 0x0;
164}
165static inline u32 fb_mmu_invalidate_replay_start_f(void)
166{
167 return 0x8;
168}
169static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
170{
171 return 0x10;
172}
173static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void)
174{
175 return 0x18;
176}
177static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
178{
179 return 0x20;
180}
181static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
182{
183 return 0x20;
184}
185static inline u32 fb_mmu_invalidate_sys_membar_s(void)
186{
187 return 1;
188}
189static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
190{
191 return (v & 0x1) << 6;
192}
193static inline u32 fb_mmu_invalidate_sys_membar_m(void)
194{
195 return 0x1 << 6;
196}
197static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
198{
199 return (r >> 6) & 0x1;
200}
201static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
202{
203 return 0x40;
204}
205static inline u32 fb_mmu_invalidate_ack_s(void)
206{
207 return 2;
208}
209static inline u32 fb_mmu_invalidate_ack_f(u32 v)
210{
211 return (v & 0x3) << 7;
212}
213static inline u32 fb_mmu_invalidate_ack_m(void)
214{
215 return 0x3 << 7;
216}
217static inline u32 fb_mmu_invalidate_ack_v(u32 r)
218{
219 return (r >> 7) & 0x3;
220}
221static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
222{
223 return 0x0;
224}
225static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
226{
227 return 0x100;
228}
229static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
230{
231 return 0x80;
232}
233static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
234{
235 return 6;
236}
237static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
238{
239 return (v & 0x3f) << 9;
240}
241static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
242{
243 return 0x3f << 9;
244}
245static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
246{
247 return (r >> 9) & 0x3f;
248}
249static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
250{
251 return 5;
252}
253static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
254{
255 return (v & 0x1f) << 15;
256}
257static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
258{
259 return 0x1f << 15;
260}
261static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
262{
263 return (r >> 15) & 0x1f;
264}
265static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
266{
267 return 1;
268}
269static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
270{
271 return (v & 0x1) << 20;
272}
273static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
274{
275 return 0x1 << 20;
276}
277static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
278{
279 return (r >> 20) & 0x1;
280}
281static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
282{
283 return 0x0;
284}
285static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
286{
287 return 0x100000;
288}
289static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
290{
291 return 3;
292}
293static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
294{
295 return (v & 0x7) << 24;
296}
297static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
298{
299 return 0x7 << 24;
300}
301static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
302{
303 return (r >> 24) & 0x7;
304}
305static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
306{
307 return 0x0;
308}
309static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
310{
311 return 0x1000000;
312}
313static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
314{
315 return 0x2000000;
316}
317static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
318{
319 return 0x3000000;
320}
321static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
322{
323 return 0x4000000;
324}
325static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
326{
327 return 0x5000000;
328}
329static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
330{
331 return 0x6000000;
332}
333static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
334{
335 return 0x7000000;
336}
337static inline u32 fb_mmu_invalidate_trigger_s(void)
338{
339 return 1;
340}
341static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
342{
343 return (v & 0x1) << 31;
344}
345static inline u32 fb_mmu_invalidate_trigger_m(void)
346{
347 return 0x1 << 31;
348}
349static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
350{
351 return (r >> 31) & 0x1;
352}
353static inline u32 fb_mmu_invalidate_trigger_true_f(void)
354{
355 return 0x80000000;
356}
357static inline u32 fb_mmu_debug_wr_r(void)
358{
359 return 0x00100cc8;
360}
361static inline u32 fb_mmu_debug_wr_aperture_s(void)
362{
363 return 2;
364}
365static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
366{
367 return (v & 0x3) << 0;
368}
369static inline u32 fb_mmu_debug_wr_aperture_m(void)
370{
371 return 0x3 << 0;
372}
373static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
374{
375 return (r >> 0) & 0x3;
376}
377static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
378{
379 return 0x0;
380}
381static inline u32 fb_mmu_debug_wr_vol_false_f(void)
382{
383 return 0x0;
384}
385static inline u32 fb_mmu_debug_wr_vol_true_v(void)
386{
387 return 0x00000001;
388}
389static inline u32 fb_mmu_debug_wr_vol_true_f(void)
390{
391 return 0x4;
392}
393static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
394{
395 return (v & 0xfffffff) << 4;
396}
397static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
398{
399 return 0x0000000c;
400}
401static inline u32 fb_mmu_debug_rd_r(void)
402{
403 return 0x00100ccc;
404}
405static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
406{
407 return 0x0;
408}
409static inline u32 fb_mmu_debug_rd_vol_false_f(void)
410{
411 return 0x0;
412}
413static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
414{
415 return (v & 0xfffffff) << 4;
416}
417static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
418{
419 return 0x0000000c;
420}
421static inline u32 fb_mmu_debug_ctrl_r(void)
422{
423 return 0x00100cc4;
424}
425static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
426{
427 return (r >> 16) & 0x1;
428}
429static inline u32 fb_mmu_debug_ctrl_debug_m(void)
430{
431 return 0x1 << 16;
432}
433static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
434{
435 return 0x00000001;
436}
437static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
438{
439 return 0x00000000;
440}
441static inline u32 fb_mmu_vpr_info_r(void)
442{
443 return 0x00100cd0;
444}
445static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
446{
447 return (r >> 2) & 0x1;
448}
449static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
450{
451 return 0x00000000;
452}
453static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
454{
455 return 0x00000001;
456}
457#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
deleted file mode 100644
index 6f7e09ff9..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h
+++ /dev/null
@@ -1,669 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fifo_gp10b_h_
51#define _hw_fifo_gp10b_h_
52
53static inline u32 fifo_bar1_base_r(void)
54{
55 return 0x00002254;
56}
57static inline u32 fifo_bar1_base_ptr_f(u32 v)
58{
59 return (v & 0xfffffff) << 0;
60}
61static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
62{
63 return 0x0000000c;
64}
65static inline u32 fifo_bar1_base_valid_false_f(void)
66{
67 return 0x0;
68}
69static inline u32 fifo_bar1_base_valid_true_f(void)
70{
71 return 0x10000000;
72}
73static inline u32 fifo_runlist_base_r(void)
74{
75 return 0x00002270;
76}
77static inline u32 fifo_runlist_base_ptr_f(u32 v)
78{
79 return (v & 0xfffffff) << 0;
80}
81static inline u32 fifo_runlist_base_target_vid_mem_f(void)
82{
83 return 0x0;
84}
85static inline u32 fifo_runlist_r(void)
86{
87 return 0x00002274;
88}
89static inline u32 fifo_runlist_engine_f(u32 v)
90{
91 return (v & 0xf) << 20;
92}
93static inline u32 fifo_eng_runlist_base_r(u32 i)
94{
95 return 0x00002280 + i*8;
96}
97static inline u32 fifo_eng_runlist_base__size_1_v(void)
98{
99 return 0x00000001;
100}
101static inline u32 fifo_eng_runlist_r(u32 i)
102{
103 return 0x00002284 + i*8;
104}
105static inline u32 fifo_eng_runlist__size_1_v(void)
106{
107 return 0x00000001;
108}
109static inline u32 fifo_eng_runlist_length_f(u32 v)
110{
111 return (v & 0xffff) << 0;
112}
113static inline u32 fifo_eng_runlist_pending_true_f(void)
114{
115 return 0x100000;
116}
117static inline u32 fifo_pb_timeslice_r(u32 i)
118{
119 return 0x00002350 + i*4;
120}
121static inline u32 fifo_pb_timeslice_timeout_16_f(void)
122{
123 return 0x10;
124}
125static inline u32 fifo_pb_timeslice_timescale_0_f(void)
126{
127 return 0x0;
128}
129static inline u32 fifo_pb_timeslice_enable_true_f(void)
130{
131 return 0x10000000;
132}
133static inline u32 fifo_pbdma_map_r(u32 i)
134{
135 return 0x00002390 + i*4;
136}
137static inline u32 fifo_intr_0_r(void)
138{
139 return 0x00002100;
140}
141static inline u32 fifo_intr_0_bind_error_pending_f(void)
142{
143 return 0x1;
144}
145static inline u32 fifo_intr_0_bind_error_reset_f(void)
146{
147 return 0x1;
148}
149static inline u32 fifo_intr_0_sched_error_pending_f(void)
150{
151 return 0x100;
152}
153static inline u32 fifo_intr_0_sched_error_reset_f(void)
154{
155 return 0x100;
156}
157static inline u32 fifo_intr_0_chsw_error_pending_f(void)
158{
159 return 0x10000;
160}
161static inline u32 fifo_intr_0_chsw_error_reset_f(void)
162{
163 return 0x10000;
164}
165static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
166{
167 return 0x800000;
168}
169static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
170{
171 return 0x800000;
172}
173static inline u32 fifo_intr_0_lb_error_pending_f(void)
174{
175 return 0x1000000;
176}
177static inline u32 fifo_intr_0_lb_error_reset_f(void)
178{
179 return 0x1000000;
180}
181static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void)
182{
183 return 0x2000000;
184}
185static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
186{
187 return 0x8000000;
188}
189static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
190{
191 return 0x8000000;
192}
193static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
194{
195 return 0x10000000;
196}
197static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
198{
199 return 0x20000000;
200}
201static inline u32 fifo_intr_0_runlist_event_pending_f(void)
202{
203 return 0x40000000;
204}
205static inline u32 fifo_intr_0_channel_intr_pending_f(void)
206{
207 return 0x80000000;
208}
209static inline u32 fifo_intr_en_0_r(void)
210{
211 return 0x00002140;
212}
213static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
214{
215 return (v & 0x1) << 8;
216}
217static inline u32 fifo_intr_en_0_sched_error_m(void)
218{
219 return 0x1 << 8;
220}
221static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
222{
223 return (v & 0x1) << 28;
224}
225static inline u32 fifo_intr_en_0_mmu_fault_m(void)
226{
227 return 0x1 << 28;
228}
229static inline u32 fifo_intr_en_1_r(void)
230{
231 return 0x00002528;
232}
233static inline u32 fifo_intr_bind_error_r(void)
234{
235 return 0x0000252c;
236}
237static inline u32 fifo_intr_sched_error_r(void)
238{
239 return 0x0000254c;
240}
241static inline u32 fifo_intr_sched_error_code_f(u32 v)
242{
243 return (v & 0xff) << 0;
244}
245static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
246{
247 return 0x0000000a;
248}
249static inline u32 fifo_intr_chsw_error_r(void)
250{
251 return 0x0000256c;
252}
253static inline u32 fifo_intr_mmu_fault_id_r(void)
254{
255 return 0x0000259c;
256}
257static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
258{
259 return 0x00000000;
260}
261static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
262{
263 return 0x0;
264}
265static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
266{
267 return 0x00002800 + i*16;
268}
269static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
270{
271 return (r >> 0) & 0xfffffff;
272}
273static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
274{
275 return 0x0000000c;
276}
277static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
278{
279 return 0x00002804 + i*16;
280}
281static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
282{
283 return 0x00002808 + i*16;
284}
285static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
286{
287 return 0x0000280c + i*16;
288}
289static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
290{
291 return (r >> 0) & 0x1f;
292}
293static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r)
294{
295 return (r >> 20) & 0x1;
296}
297static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void)
298{
299 return 0x00000000;
300}
301static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void)
302{
303 return 0x00000001;
304}
305static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
306{
307 return (r >> 8) & 0x7f;
308}
309static inline u32 fifo_intr_pbdma_id_r(void)
310{
311 return 0x000025a0;
312}
313static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
314{
315 return (v & 0x1) << (0 + i*1);
316}
317static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
318{
319 return 0x00000001;
320}
321static inline u32 fifo_intr_runlist_r(void)
322{
323 return 0x00002a00;
324}
325static inline u32 fifo_fb_timeout_r(void)
326{
327 return 0x00002a04;
328}
329static inline u32 fifo_fb_timeout_period_m(void)
330{
331 return 0x3fffffff << 0;
332}
333static inline u32 fifo_fb_timeout_period_max_f(void)
334{
335 return 0x3fffffff;
336}
337static inline u32 fifo_error_sched_disable_r(void)
338{
339 return 0x0000262c;
340}
341static inline u32 fifo_sched_disable_r(void)
342{
343 return 0x00002630;
344}
345static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
346{
347 return (v & 0x1) << (0 + i*1);
348}
349static inline u32 fifo_sched_disable_runlist_m(u32 i)
350{
351 return 0x1 << (0 + i*1);
352}
353static inline u32 fifo_sched_disable_true_v(void)
354{
355 return 0x00000001;
356}
357static inline u32 fifo_preempt_r(void)
358{
359 return 0x00002634;
360}
361static inline u32 fifo_preempt_pending_true_f(void)
362{
363 return 0x100000;
364}
365static inline u32 fifo_preempt_type_channel_f(void)
366{
367 return 0x0;
368}
369static inline u32 fifo_preempt_type_tsg_f(void)
370{
371 return 0x1000000;
372}
373static inline u32 fifo_preempt_chid_f(u32 v)
374{
375 return (v & 0xfff) << 0;
376}
377static inline u32 fifo_preempt_id_f(u32 v)
378{
379 return (v & 0xfff) << 0;
380}
381static inline u32 fifo_trigger_mmu_fault_r(u32 i)
382{
383 return 0x00002a30 + i*4;
384}
385static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
386{
387 return (v & 0x1f) << 0;
388}
389static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
390{
391 return (v & 0x1) << 8;
392}
393static inline u32 fifo_engine_status_r(u32 i)
394{
395 return 0x00002640 + i*8;
396}
397static inline u32 fifo_engine_status__size_1_v(void)
398{
399 return 0x00000002;
400}
401static inline u32 fifo_engine_status_id_v(u32 r)
402{
403 return (r >> 0) & 0xfff;
404}
405static inline u32 fifo_engine_status_id_type_v(u32 r)
406{
407 return (r >> 12) & 0x1;
408}
409static inline u32 fifo_engine_status_id_type_chid_v(void)
410{
411 return 0x00000000;
412}
413static inline u32 fifo_engine_status_id_type_tsgid_v(void)
414{
415 return 0x00000001;
416}
417static inline u32 fifo_engine_status_ctx_status_v(u32 r)
418{
419 return (r >> 13) & 0x7;
420}
421static inline u32 fifo_engine_status_ctx_status_valid_v(void)
422{
423 return 0x00000001;
424}
425static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
426{
427 return 0x00000005;
428}
429static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
430{
431 return 0x00000006;
432}
433static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
434{
435 return 0x00000007;
436}
437static inline u32 fifo_engine_status_next_id_v(u32 r)
438{
439 return (r >> 16) & 0xfff;
440}
441static inline u32 fifo_engine_status_next_id_type_v(u32 r)
442{
443 return (r >> 28) & 0x1;
444}
445static inline u32 fifo_engine_status_next_id_type_chid_v(void)
446{
447 return 0x00000000;
448}
449static inline u32 fifo_engine_status_faulted_v(u32 r)
450{
451 return (r >> 30) & 0x1;
452}
453static inline u32 fifo_engine_status_faulted_true_v(void)
454{
455 return 0x00000001;
456}
457static inline u32 fifo_engine_status_engine_v(u32 r)
458{
459 return (r >> 31) & 0x1;
460}
461static inline u32 fifo_engine_status_engine_idle_v(void)
462{
463 return 0x00000000;
464}
465static inline u32 fifo_engine_status_engine_busy_v(void)
466{
467 return 0x00000001;
468}
469static inline u32 fifo_engine_status_ctxsw_v(u32 r)
470{
471 return (r >> 15) & 0x1;
472}
473static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
474{
475 return 0x00000001;
476}
477static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
478{
479 return 0x8000;
480}
481static inline u32 fifo_pbdma_status_r(u32 i)
482{
483 return 0x00003080 + i*4;
484}
485static inline u32 fifo_pbdma_status__size_1_v(void)
486{
487 return 0x00000001;
488}
489static inline u32 fifo_pbdma_status_id_v(u32 r)
490{
491 return (r >> 0) & 0xfff;
492}
493static inline u32 fifo_pbdma_status_id_type_v(u32 r)
494{
495 return (r >> 12) & 0x1;
496}
497static inline u32 fifo_pbdma_status_id_type_chid_v(void)
498{
499 return 0x00000000;
500}
501static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
502{
503 return 0x00000001;
504}
505static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
506{
507 return (r >> 13) & 0x7;
508}
509static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
510{
511 return 0x00000001;
512}
513static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
514{
515 return 0x00000005;
516}
517static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
518{
519 return 0x00000006;
520}
521static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
522{
523 return 0x00000007;
524}
525static inline u32 fifo_pbdma_status_next_id_v(u32 r)
526{
527 return (r >> 16) & 0xfff;
528}
529static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
530{
531 return (r >> 28) & 0x1;
532}
533static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
534{
535 return 0x00000000;
536}
537static inline u32 fifo_pbdma_status_chsw_v(u32 r)
538{
539 return (r >> 15) & 0x1;
540}
541static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
542{
543 return 0x00000001;
544}
545static inline u32 fifo_replay_fault_buffer_lo_r(void)
546{
547 return 0x00002a70;
548}
549static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r)
550{
551 return (r >> 0) & 0x1;
552}
553static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void)
554{
555 return 0x00000001;
556}
557static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void)
558{
559 return 0x00000000;
560}
561static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v)
562{
563 return (v & 0xfffff) << 12;
564}
565static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void)
566{
567 return 0x00000000;
568}
569static inline u32 fifo_replay_fault_buffer_hi_r(void)
570{
571 return 0x00002a74;
572}
573static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v)
574{
575 return (v & 0xff) << 0;
576}
577static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void)
578{
579 return 0x00000000;
580}
581static inline u32 fifo_replay_fault_buffer_size_r(void)
582{
583 return 0x00002a78;
584}
585static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
586{
587 return (v & 0x1ff) << 0;
588}
589static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
590{
591 return 0x000000c0;
592}
593static inline u32 fifo_replay_fault_buffer_get_r(void)
594{
595 return 0x00002a7c;
596}
597static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
598{
599 return (v & 0x1ff) << 0;
600}
601static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
602{
603 return 0x00000000;
604}
605static inline u32 fifo_replay_fault_buffer_put_r(void)
606{
607 return 0x00002a80;
608}
609static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
610{
611 return (v & 0x1ff) << 0;
612}
613static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
614{
615 return 0x00000000;
616}
617static inline u32 fifo_replay_fault_buffer_info_r(void)
618{
619 return 0x00002a84;
620}
621static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v)
622{
623 return (v & 0x1) << 0;
624}
625static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void)
626{
627 return 0x00000000;
628}
629static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void)
630{
631 return 0x00000001;
632}
633static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void)
634{
635 return 0x00000001;
636}
637static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v)
638{
639 return (v & 0x1) << 24;
640}
641static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void)
642{
643 return 0x00000000;
644}
645static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void)
646{
647 return 0x00000001;
648}
649static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void)
650{
651 return 0x00000001;
652}
653static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v)
654{
655 return (v & 0x1) << 28;
656}
657static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void)
658{
659 return 0x00000000;
660}
661static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void)
662{
663 return 0x00000001;
664}
665static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void)
666{
667 return 0x00000001;
668}
669#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h
deleted file mode 100644
index e2dff4909..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_flush_gp10b_h_
51#define _hw_flush_gp10b_h_
52
53static inline u32 flush_l2_system_invalidate_r(void)
54{
55 return 0x00070004;
56}
57static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
58{
59 return (r >> 0) & 0x1;
60}
61static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
66{
67 return 0x1;
68}
69static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
70{
71 return (r >> 1) & 0x1;
72}
73static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 flush_l2_flush_dirty_r(void)
78{
79 return 0x00070010;
80}
81static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
82{
83 return (r >> 0) & 0x1;
84}
85static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
90{
91 return 0x0;
92}
93static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
94{
95 return 0x00000001;
96}
97static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
98{
99 return 0x1;
100}
101static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
102{
103 return (r >> 1) & 0x1;
104}
105static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
110{
111 return 0x0;
112}
113static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 flush_l2_clean_comptags_r(void)
118{
119 return 0x0007000c;
120}
121static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
122{
123 return (r >> 0) & 0x1;
124}
125static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
126{
127 return 0x00000000;
128}
129static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
130{
131 return 0x0;
132}
133static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
138{
139 return 0x1;
140}
141static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
142{
143 return (r >> 1) & 0x1;
144}
145static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
146{
147 return 0x00000000;
148}
149static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
150{
151 return 0x0;
152}
153static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 flush_fb_flush_r(void)
158{
159 return 0x00070000;
160}
161static inline u32 flush_fb_flush_pending_v(u32 r)
162{
163 return (r >> 0) & 0x1;
164}
165static inline u32 flush_fb_flush_pending_busy_v(void)
166{
167 return 0x00000001;
168}
169static inline u32 flush_fb_flush_pending_busy_f(void)
170{
171 return 0x1;
172}
173static inline u32 flush_fb_flush_outstanding_v(u32 r)
174{
175 return (r >> 1) & 0x1;
176}
177static inline u32 flush_fb_flush_outstanding_true_v(void)
178{
179 return 0x00000001;
180}
181#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
deleted file mode 100644
index ae524ce54..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_fuse_gp10b_h_
51#define _hw_fuse_gp10b_h_
52
53static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
54{
55 return 0x00021c38 + i*4;
56}
57static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
58{
59 return 0x00021838 + i*4;
60}
61static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
62{
63 return 0x00021944;
64}
65static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
66{
67 return (v & 0xff) << 0;
68}
69static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
70{
71 return 0xff << 0;
72}
73static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
74{
75 return (r >> 0) & 0xff;
76}
77static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
78{
79 return 0x00021948;
80}
81static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
82{
83 return (v & 0x1) << 0;
84}
85static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
86{
87 return 0x1 << 0;
88}
89static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
90{
91 return (r >> 0) & 0x1;
92}
93static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
94{
95 return 0x1;
96}
97static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
98{
99 return 0x0;
100}
101static inline u32 fuse_status_opt_fbio_r(void)
102{
103 return 0x00021c14;
104}
105static inline u32 fuse_status_opt_fbio_data_f(u32 v)
106{
107 return (v & 0xffff) << 0;
108}
109static inline u32 fuse_status_opt_fbio_data_m(void)
110{
111 return 0xffff << 0;
112}
113static inline u32 fuse_status_opt_fbio_data_v(u32 r)
114{
115 return (r >> 0) & 0xffff;
116}
117static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
118{
119 return 0x00021d70 + i*4;
120}
121static inline u32 fuse_status_opt_fbp_r(void)
122{
123 return 0x00021d38;
124}
125static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
126{
127 return (r >> (0 + i*0)) & 0x1;
128}
129static inline u32 fuse_opt_ecc_en_r(void)
130{
131 return 0x00021228;
132}
133static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
134{
135 return 0x000213f0;
136}
137#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
deleted file mode 100644
index 9ce9448e1..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
+++ /dev/null
@@ -1,1237 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gmmu_gp10b_h_
51#define _hw_gmmu_gp10b_h_
52
53static inline u32 gmmu_new_pde_is_pte_w(void)
54{
55 return 0;
56}
57static inline u32 gmmu_new_pde_is_pte_false_f(void)
58{
59 return 0x0;
60}
61static inline u32 gmmu_new_pde_aperture_w(void)
62{
63 return 0;
64}
65static inline u32 gmmu_new_pde_aperture_invalid_f(void)
66{
67 return 0x0;
68}
69static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
70{
71 return 0x2;
72}
73static inline u32 gmmu_new_pde_address_sys_f(u32 v)
74{
75 return (v & 0xfffffff) << 8;
76}
77static inline u32 gmmu_new_pde_address_sys_w(void)
78{
79 return 0;
80}
81static inline u32 gmmu_new_pde_vol_w(void)
82{
83 return 0;
84}
85static inline u32 gmmu_new_pde_vol_true_f(void)
86{
87 return 0x8;
88}
89static inline u32 gmmu_new_pde_vol_false_f(void)
90{
91 return 0x0;
92}
93static inline u32 gmmu_new_pde_address_shift_v(void)
94{
95 return 0x0000000c;
96}
97static inline u32 gmmu_new_pde__size_v(void)
98{
99 return 0x00000008;
100}
101static inline u32 gmmu_new_dual_pde_is_pte_w(void)
102{
103 return 0;
104}
105static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
106{
107 return 0x0;
108}
109static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
110{
111 return 0;
112}
113static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
114{
115 return 0x0;
116}
117static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
118{
119 return 0x2;
120}
121static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
122{
123 return (v & 0xfffffff) << 4;
124}
125static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
126{
127 return 0;
128}
129static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
130{
131 return 2;
132}
133static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
134{
135 return 0x0;
136}
137static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
138{
139 return 0x2;
140}
141static inline u32 gmmu_new_dual_pde_vol_small_w(void)
142{
143 return 2;
144}
145static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
146{
147 return 0x8;
148}
149static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
150{
151 return 0x0;
152}
153static inline u32 gmmu_new_dual_pde_vol_big_w(void)
154{
155 return 0;
156}
157static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
158{
159 return 0x8;
160}
161static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
162{
163 return 0x0;
164}
165static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
166{
167 return (v & 0xfffffff) << 8;
168}
169static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
170{
171 return 2;
172}
173static inline u32 gmmu_new_dual_pde_address_shift_v(void)
174{
175 return 0x0000000c;
176}
177static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
178{
179 return 0x00000008;
180}
181static inline u32 gmmu_new_dual_pde__size_v(void)
182{
183 return 0x00000010;
184}
185static inline u32 gmmu_new_pte__size_v(void)
186{
187 return 0x00000008;
188}
189static inline u32 gmmu_new_pte_valid_w(void)
190{
191 return 0;
192}
193static inline u32 gmmu_new_pte_valid_true_f(void)
194{
195 return 0x1;
196}
197static inline u32 gmmu_new_pte_valid_false_f(void)
198{
199 return 0x0;
200}
201static inline u32 gmmu_new_pte_privilege_w(void)
202{
203 return 0;
204}
205static inline u32 gmmu_new_pte_privilege_true_f(void)
206{
207 return 0x20;
208}
209static inline u32 gmmu_new_pte_privilege_false_f(void)
210{
211 return 0x0;
212}
213static inline u32 gmmu_new_pte_address_sys_f(u32 v)
214{
215 return (v & 0xfffffff) << 8;
216}
217static inline u32 gmmu_new_pte_address_sys_w(void)
218{
219 return 0;
220}
221static inline u32 gmmu_new_pte_vol_w(void)
222{
223 return 0;
224}
225static inline u32 gmmu_new_pte_vol_true_f(void)
226{
227 return 0x8;
228}
229static inline u32 gmmu_new_pte_vol_false_f(void)
230{
231 return 0x0;
232}
233static inline u32 gmmu_new_pte_aperture_w(void)
234{
235 return 0;
236}
237static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
238{
239 return 0x0;
240}
241static inline u32 gmmu_new_pte_read_only_w(void)
242{
243 return 0;
244}
245static inline u32 gmmu_new_pte_read_only_true_f(void)
246{
247 return 0x40;
248}
249static inline u32 gmmu_new_pte_comptagline_f(u32 v)
250{
251 return (v & 0x3ffff) << 4;
252}
253static inline u32 gmmu_new_pte_comptagline_w(void)
254{
255 return 1;
256}
257static inline u32 gmmu_new_pte_kind_f(u32 v)
258{
259 return (v & 0xff) << 24;
260}
261static inline u32 gmmu_new_pte_kind_w(void)
262{
263 return 1;
264}
265static inline u32 gmmu_new_pte_address_shift_v(void)
266{
267 return 0x0000000c;
268}
269static inline u32 gmmu_pte_kind_f(u32 v)
270{
271 return (v & 0xff) << 4;
272}
273static inline u32 gmmu_pte_kind_w(void)
274{
275 return 1;
276}
277static inline u32 gmmu_pte_kind_invalid_v(void)
278{
279 return 0x000000ff;
280}
281static inline u32 gmmu_pte_kind_pitch_v(void)
282{
283 return 0x00000000;
284}
285static inline u32 gmmu_pte_kind_z16_v(void)
286{
287 return 0x00000001;
288}
289static inline u32 gmmu_pte_kind_z16_2c_v(void)
290{
291 return 0x00000002;
292}
293static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
294{
295 return 0x00000003;
296}
297static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
298{
299 return 0x00000004;
300}
301static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
302{
303 return 0x00000005;
304}
305static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
306{
307 return 0x00000006;
308}
309static inline u32 gmmu_pte_kind_z16_2z_v(void)
310{
311 return 0x00000007;
312}
313static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
314{
315 return 0x00000008;
316}
317static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
318{
319 return 0x00000009;
320}
321static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
322{
323 return 0x0000000a;
324}
325static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
326{
327 return 0x0000000b;
328}
329static inline u32 gmmu_pte_kind_z16_2cz_v(void)
330{
331 return 0x00000036;
332}
333static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
334{
335 return 0x00000037;
336}
337static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
338{
339 return 0x00000038;
340}
341static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
342{
343 return 0x00000039;
344}
345static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
346{
347 return 0x0000005f;
348}
349static inline u32 gmmu_pte_kind_z16_4cz_v(void)
350{
351 return 0x0000000c;
352}
353static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
354{
355 return 0x0000000d;
356}
357static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
358{
359 return 0x0000000e;
360}
361static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
362{
363 return 0x0000000f;
364}
365static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
366{
367 return 0x00000010;
368}
369static inline u32 gmmu_pte_kind_s8z24_v(void)
370{
371 return 0x00000011;
372}
373static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
374{
375 return 0x00000012;
376}
377static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
378{
379 return 0x00000013;
380}
381static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
382{
383 return 0x00000014;
384}
385static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
386{
387 return 0x00000015;
388}
389static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
390{
391 return 0x00000016;
392}
393static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
394{
395 return 0x00000017;
396}
397static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
398{
399 return 0x00000018;
400}
401static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
402{
403 return 0x00000019;
404}
405static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
406{
407 return 0x0000001a;
408}
409static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
410{
411 return 0x0000001b;
412}
413static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
414{
415 return 0x0000001c;
416}
417static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
418{
419 return 0x0000001d;
420}
421static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
422{
423 return 0x0000001e;
424}
425static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
426{
427 return 0x0000001f;
428}
429static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
430{
431 return 0x00000020;
432}
433static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
434{
435 return 0x00000021;
436}
437static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
438{
439 return 0x00000022;
440}
441static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
442{
443 return 0x00000023;
444}
445static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
446{
447 return 0x00000024;
448}
449static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
450{
451 return 0x00000025;
452}
453static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
454{
455 return 0x00000026;
456}
457static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
458{
459 return 0x00000027;
460}
461static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
462{
463 return 0x00000028;
464}
465static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
466{
467 return 0x00000029;
468}
469static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
470{
471 return 0x0000002e;
472}
473static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
474{
475 return 0x0000002f;
476}
477static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
478{
479 return 0x00000030;
480}
481static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
482{
483 return 0x00000031;
484}
485static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
486{
487 return 0x00000032;
488}
489static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
490{
491 return 0x00000033;
492}
493static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
494{
495 return 0x00000034;
496}
497static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
498{
499 return 0x00000035;
500}
501static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
502{
503 return 0x0000003a;
504}
505static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
506{
507 return 0x0000003b;
508}
509static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
510{
511 return 0x0000003c;
512}
513static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
514{
515 return 0x0000003d;
516}
517static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
518{
519 return 0x0000003e;
520}
521static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
522{
523 return 0x0000003f;
524}
525static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
526{
527 return 0x00000040;
528}
529static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
530{
531 return 0x00000041;
532}
533static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
534{
535 return 0x00000042;
536}
537static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
538{
539 return 0x00000043;
540}
541static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
542{
543 return 0x00000044;
544}
545static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
546{
547 return 0x00000045;
548}
549static inline u32 gmmu_pte_kind_z24s8_v(void)
550{
551 return 0x00000046;
552}
553static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
554{
555 return 0x00000047;
556}
557static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
558{
559 return 0x00000048;
560}
561static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
562{
563 return 0x00000049;
564}
565static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
566{
567 return 0x0000004a;
568}
569static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
570{
571 return 0x0000004b;
572}
573static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
574{
575 return 0x0000004c;
576}
577static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
578{
579 return 0x0000004d;
580}
581static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
582{
583 return 0x0000004e;
584}
585static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
586{
587 return 0x0000004f;
588}
589static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
590{
591 return 0x00000050;
592}
593static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
594{
595 return 0x00000051;
596}
597static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
598{
599 return 0x00000052;
600}
601static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
602{
603 return 0x00000053;
604}
605static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
606{
607 return 0x00000054;
608}
609static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
610{
611 return 0x00000055;
612}
613static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
614{
615 return 0x00000056;
616}
617static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
618{
619 return 0x00000057;
620}
621static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
622{
623 return 0x00000058;
624}
625static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
626{
627 return 0x00000059;
628}
629static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
630{
631 return 0x0000005a;
632}
633static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
634{
635 return 0x0000005b;
636}
637static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
638{
639 return 0x0000005c;
640}
641static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
642{
643 return 0x0000005d;
644}
645static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
646{
647 return 0x0000005e;
648}
649static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
650{
651 return 0x00000063;
652}
653static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
654{
655 return 0x00000064;
656}
657static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
658{
659 return 0x00000065;
660}
661static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
662{
663 return 0x00000066;
664}
665static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
666{
667 return 0x00000067;
668}
669static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
670{
671 return 0x00000068;
672}
673static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
674{
675 return 0x00000069;
676}
677static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
678{
679 return 0x0000006a;
680}
681static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
682{
683 return 0x0000006f;
684}
685static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
686{
687 return 0x00000070;
688}
689static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
690{
691 return 0x00000071;
692}
693static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
694{
695 return 0x00000072;
696}
697static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
698{
699 return 0x00000073;
700}
701static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
702{
703 return 0x00000074;
704}
705static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
706{
707 return 0x00000075;
708}
709static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
710{
711 return 0x00000076;
712}
713static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
714{
715 return 0x00000077;
716}
717static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
718{
719 return 0x00000078;
720}
721static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
722{
723 return 0x00000079;
724}
725static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
726{
727 return 0x0000007a;
728}
729static inline u32 gmmu_pte_kind_zf32_v(void)
730{
731 return 0x0000007b;
732}
733static inline u32 gmmu_pte_kind_zf32_1z_v(void)
734{
735 return 0x0000007c;
736}
737static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
738{
739 return 0x0000007d;
740}
741static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
742{
743 return 0x0000007e;
744}
745static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
746{
747 return 0x0000007f;
748}
749static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
750{
751 return 0x00000080;
752}
753static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
754{
755 return 0x00000081;
756}
757static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
758{
759 return 0x00000082;
760}
761static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
762{
763 return 0x00000083;
764}
765static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
766{
767 return 0x00000084;
768}
769static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
770{
771 return 0x00000085;
772}
773static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
774{
775 return 0x00000086;
776}
777static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
778{
779 return 0x00000087;
780}
781static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
782{
783 return 0x00000088;
784}
785static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
786{
787 return 0x00000089;
788}
789static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
790{
791 return 0x0000008a;
792}
793static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
794{
795 return 0x0000008b;
796}
797static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
798{
799 return 0x0000008c;
800}
801static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
802{
803 return 0x0000008d;
804}
805static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
806{
807 return 0x0000008e;
808}
809static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
810{
811 return 0x0000008f;
812}
813static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
814{
815 return 0x00000090;
816}
817static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
818{
819 return 0x00000091;
820}
821static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
822{
823 return 0x00000092;
824}
825static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
826{
827 return 0x00000097;
828}
829static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
830{
831 return 0x00000098;
832}
833static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
834{
835 return 0x00000099;
836}
837static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
838{
839 return 0x0000009a;
840}
841static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
842{
843 return 0x0000009b;
844}
845static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
846{
847 return 0x0000009c;
848}
849static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
850{
851 return 0x0000009d;
852}
853static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
854{
855 return 0x0000009e;
856}
857static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
858{
859 return 0x0000009f;
860}
861static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
862{
863 return 0x000000a0;
864}
865static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
866{
867 return 0x000000a1;
868}
869static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
870{
871 return 0x000000a2;
872}
873static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
874{
875 return 0x000000a3;
876}
877static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
878{
879 return 0x000000a4;
880}
881static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
882{
883 return 0x000000a5;
884}
885static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
886{
887 return 0x000000a6;
888}
889static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
890{
891 return 0x000000a7;
892}
893static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
894{
895 return 0x000000a8;
896}
897static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
898{
899 return 0x000000a9;
900}
901static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
902{
903 return 0x000000aa;
904}
905static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
906{
907 return 0x000000ab;
908}
909static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
910{
911 return 0x000000ac;
912}
913static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
914{
915 return 0x000000ad;
916}
917static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
918{
919 return 0x000000ae;
920}
921static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
922{
923 return 0x000000b3;
924}
925static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
926{
927 return 0x000000b4;
928}
929static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
930{
931 return 0x000000b5;
932}
933static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
934{
935 return 0x000000b6;
936}
937static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
938{
939 return 0x000000b7;
940}
941static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
942{
943 return 0x000000b8;
944}
945static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
946{
947 return 0x000000b9;
948}
949static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
950{
951 return 0x000000ba;
952}
953static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
954{
955 return 0x000000bb;
956}
957static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
958{
959 return 0x000000bc;
960}
961static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
962{
963 return 0x000000bd;
964}
965static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
966{
967 return 0x000000be;
968}
969static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
970{
971 return 0x000000bf;
972}
973static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
974{
975 return 0x000000c0;
976}
977static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
978{
979 return 0x000000c1;
980}
981static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
982{
983 return 0x000000c2;
984}
985static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
986{
987 return 0x000000c3;
988}
989static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
990{
991 return 0x000000c4;
992}
993static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
994{
995 return 0x000000c5;
996}
997static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
998{
999 return 0x000000c6;
1000}
1001static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
1002{
1003 return 0x000000c7;
1004}
1005static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
1006{
1007 return 0x000000c8;
1008}
1009static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
1010{
1011 return 0x000000ce;
1012}
1013static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
1014{
1015 return 0x000000cf;
1016}
1017static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
1018{
1019 return 0x000000d0;
1020}
1021static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
1022{
1023 return 0x000000d1;
1024}
1025static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
1026{
1027 return 0x000000d2;
1028}
1029static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
1030{
1031 return 0x000000d3;
1032}
1033static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
1034{
1035 return 0x000000d4;
1036}
1037static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
1038{
1039 return 0x000000d5;
1040}
1041static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1042{
1043 return 0x000000d6;
1044}
1045static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1046{
1047 return 0x000000d7;
1048}
1049static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1050{
1051 return 0x000000fe;
1052}
1053static inline u32 gmmu_pte_kind_c32_2c_v(void)
1054{
1055 return 0x000000d8;
1056}
1057static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1058{
1059 return 0x000000d9;
1060}
1061static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1062{
1063 return 0x000000da;
1064}
1065static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1066{
1067 return 0x000000db;
1068}
1069static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1070{
1071 return 0x000000dc;
1072}
1073static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1074{
1075 return 0x000000dd;
1076}
1077static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1078{
1079 return 0x000000de;
1080}
1081static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
1082{
1083 return 0x000000cc;
1084}
1085static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1086{
1087 return 0x000000df;
1088}
1089static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1090{
1091 return 0x000000e0;
1092}
1093static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1094{
1095 return 0x000000e1;
1096}
1097static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1098{
1099 return 0x000000e2;
1100}
1101static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1102{
1103 return 0x000000e3;
1104}
1105static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
1106{
1107 return 0x0000002c;
1108}
1109static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1110{
1111 return 0x000000e4;
1112}
1113static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1114{
1115 return 0x000000e5;
1116}
1117static inline u32 gmmu_pte_kind_c64_2c_v(void)
1118{
1119 return 0x000000e6;
1120}
1121static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1122{
1123 return 0x000000e7;
1124}
1125static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1126{
1127 return 0x000000e8;
1128}
1129static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1130{
1131 return 0x000000e9;
1132}
1133static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1134{
1135 return 0x000000ea;
1136}
1137static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1138{
1139 return 0x000000eb;
1140}
1141static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1142{
1143 return 0x000000ec;
1144}
1145static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
1146{
1147 return 0x000000cd;
1148}
1149static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1150{
1151 return 0x000000ed;
1152}
1153static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1154{
1155 return 0x000000ee;
1156}
1157static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1158{
1159 return 0x000000ef;
1160}
1161static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1162{
1163 return 0x000000f0;
1164}
1165static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1166{
1167 return 0x000000f1;
1168}
1169static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
1170{
1171 return 0x0000002d;
1172}
1173static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1174{
1175 return 0x000000f2;
1176}
1177static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1178{
1179 return 0x000000f3;
1180}
1181static inline u32 gmmu_pte_kind_c128_2c_v(void)
1182{
1183 return 0x000000f4;
1184}
1185static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1186{
1187 return 0x000000f5;
1188}
1189static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1190{
1191 return 0x000000f6;
1192}
1193static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1194{
1195 return 0x000000f7;
1196}
1197static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1198{
1199 return 0x000000f8;
1200}
1201static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1202{
1203 return 0x000000f9;
1204}
1205static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1206{
1207 return 0x000000fa;
1208}
1209static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1210{
1211 return 0x000000fb;
1212}
1213static inline u32 gmmu_pte_kind_x8c24_v(void)
1214{
1215 return 0x000000fc;
1216}
1217static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1218{
1219 return 0x000000fd;
1220}
1221static inline u32 gmmu_pte_kind_smsked_message_v(void)
1222{
1223 return 0x000000ca;
1224}
1225static inline u32 gmmu_pte_kind_smhost_message_v(void)
1226{
1227 return 0x000000cb;
1228}
1229static inline u32 gmmu_pte_kind_s8_v(void)
1230{
1231 return 0x0000002a;
1232}
1233static inline u32 gmmu_pte_kind_s8_2s_v(void)
1234{
1235 return 0x0000002b;
1236}
1237#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
deleted file mode 100644
index b3fd704b8..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ /dev/null
@@ -1,4149 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_gr_gp10b_h_
51#define _hw_gr_gp10b_h_
52
53static inline u32 gr_intr_r(void)
54{
55 return 0x00400100;
56}
57static inline u32 gr_intr_notify_pending_f(void)
58{
59 return 0x1;
60}
61static inline u32 gr_intr_notify_reset_f(void)
62{
63 return 0x1;
64}
65static inline u32 gr_intr_semaphore_pending_f(void)
66{
67 return 0x2;
68}
69static inline u32 gr_intr_semaphore_reset_f(void)
70{
71 return 0x2;
72}
73static inline u32 gr_intr_illegal_method_pending_f(void)
74{
75 return 0x10;
76}
77static inline u32 gr_intr_illegal_method_reset_f(void)
78{
79 return 0x10;
80}
81static inline u32 gr_intr_illegal_notify_pending_f(void)
82{
83 return 0x40;
84}
85static inline u32 gr_intr_illegal_notify_reset_f(void)
86{
87 return 0x40;
88}
89static inline u32 gr_intr_firmware_method_f(u32 v)
90{
91 return (v & 0x1) << 8;
92}
93static inline u32 gr_intr_firmware_method_pending_f(void)
94{
95 return 0x100;
96}
97static inline u32 gr_intr_firmware_method_reset_f(void)
98{
99 return 0x100;
100}
101static inline u32 gr_intr_illegal_class_pending_f(void)
102{
103 return 0x20;
104}
105static inline u32 gr_intr_illegal_class_reset_f(void)
106{
107 return 0x20;
108}
109static inline u32 gr_intr_fecs_error_pending_f(void)
110{
111 return 0x80000;
112}
113static inline u32 gr_intr_fecs_error_reset_f(void)
114{
115 return 0x80000;
116}
117static inline u32 gr_intr_class_error_pending_f(void)
118{
119 return 0x100000;
120}
121static inline u32 gr_intr_class_error_reset_f(void)
122{
123 return 0x100000;
124}
125static inline u32 gr_intr_exception_pending_f(void)
126{
127 return 0x200000;
128}
129static inline u32 gr_intr_exception_reset_f(void)
130{
131 return 0x200000;
132}
133static inline u32 gr_fecs_intr_r(void)
134{
135 return 0x00400144;
136}
137static inline u32 gr_class_error_r(void)
138{
139 return 0x00400110;
140}
141static inline u32 gr_class_error_code_v(u32 r)
142{
143 return (r >> 0) & 0xffff;
144}
145static inline u32 gr_intr_nonstall_r(void)
146{
147 return 0x00400120;
148}
149static inline u32 gr_intr_nonstall_trap_pending_f(void)
150{
151 return 0x2;
152}
153static inline u32 gr_intr_en_r(void)
154{
155 return 0x0040013c;
156}
157static inline u32 gr_exception_r(void)
158{
159 return 0x00400108;
160}
161static inline u32 gr_exception_fe_m(void)
162{
163 return 0x1 << 0;
164}
165static inline u32 gr_exception_gpc_m(void)
166{
167 return 0x1 << 24;
168}
169static inline u32 gr_exception_memfmt_m(void)
170{
171 return 0x1 << 1;
172}
173static inline u32 gr_exception_ds_m(void)
174{
175 return 0x1 << 4;
176}
177static inline u32 gr_exception1_r(void)
178{
179 return 0x00400118;
180}
181static inline u32 gr_exception1_gpc_0_pending_f(void)
182{
183 return 0x1;
184}
185static inline u32 gr_exception2_r(void)
186{
187 return 0x0040011c;
188}
189static inline u32 gr_exception_en_r(void)
190{
191 return 0x00400138;
192}
193static inline u32 gr_exception_en_fe_m(void)
194{
195 return 0x1 << 0;
196}
197static inline u32 gr_exception1_en_r(void)
198{
199 return 0x00400130;
200}
201static inline u32 gr_exception2_en_r(void)
202{
203 return 0x00400134;
204}
205static inline u32 gr_gpfifo_ctl_r(void)
206{
207 return 0x00400500;
208}
209static inline u32 gr_gpfifo_ctl_access_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
214{
215 return 0x0;
216}
217static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
218{
219 return 0x1;
220}
221static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
222{
223 return (v & 0x1) << 16;
224}
225static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
226{
227 return 0x00000001;
228}
229static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
230{
231 return 0x10000;
232}
233static inline u32 gr_gpfifo_status_r(void)
234{
235 return 0x00400504;
236}
237static inline u32 gr_trapped_addr_r(void)
238{
239 return 0x00400704;
240}
241static inline u32 gr_trapped_addr_mthd_v(u32 r)
242{
243 return (r >> 2) & 0xfff;
244}
245static inline u32 gr_trapped_addr_subch_v(u32 r)
246{
247 return (r >> 16) & 0x7;
248}
249static inline u32 gr_trapped_data_lo_r(void)
250{
251 return 0x00400708;
252}
253static inline u32 gr_trapped_data_hi_r(void)
254{
255 return 0x0040070c;
256}
257static inline u32 gr_status_r(void)
258{
259 return 0x00400700;
260}
261static inline u32 gr_status_fe_method_upper_v(u32 r)
262{
263 return (r >> 1) & 0x1;
264}
265static inline u32 gr_status_fe_method_lower_v(u32 r)
266{
267 return (r >> 2) & 0x1;
268}
269static inline u32 gr_status_fe_method_lower_idle_v(void)
270{
271 return 0x00000000;
272}
273static inline u32 gr_status_fe_gi_v(u32 r)
274{
275 return (r >> 21) & 0x1;
276}
277static inline u32 gr_status_mask_r(void)
278{
279 return 0x00400610;
280}
281static inline u32 gr_status_1_r(void)
282{
283 return 0x00400604;
284}
285static inline u32 gr_status_2_r(void)
286{
287 return 0x00400608;
288}
289static inline u32 gr_engine_status_r(void)
290{
291 return 0x0040060c;
292}
293static inline u32 gr_engine_status_value_busy_f(void)
294{
295 return 0x1;
296}
297static inline u32 gr_pri_be0_becs_be_exception_r(void)
298{
299 return 0x00410204;
300}
301static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
302{
303 return 0x00410208;
304}
305static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
306{
307 return 0x00502c90;
308}
309static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
310{
311 return 0x00502c94;
312}
313static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
314{
315 return 0x00504508;
316}
317static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
318{
319 return 0x0050450c;
320}
321static inline u32 gr_activity_0_r(void)
322{
323 return 0x00400380;
324}
325static inline u32 gr_activity_1_r(void)
326{
327 return 0x00400384;
328}
329static inline u32 gr_activity_2_r(void)
330{
331 return 0x00400388;
332}
333static inline u32 gr_activity_4_r(void)
334{
335 return 0x00400390;
336}
337static inline u32 gr_activity_4_gpc0_s(void)
338{
339 return 3;
340}
341static inline u32 gr_activity_4_gpc0_f(u32 v)
342{
343 return (v & 0x7) << 0;
344}
345static inline u32 gr_activity_4_gpc0_m(void)
346{
347 return 0x7 << 0;
348}
349static inline u32 gr_activity_4_gpc0_v(u32 r)
350{
351 return (r >> 0) & 0x7;
352}
353static inline u32 gr_activity_4_gpc0_empty_v(void)
354{
355 return 0x00000000;
356}
357static inline u32 gr_activity_4_gpc0_preempted_v(void)
358{
359 return 0x00000004;
360}
361static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
362{
363 return 0x00501000;
364}
365static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
366{
367 return 0x00419000;
368}
369static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
370{
371 return 0x1 << 1;
372}
373static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
374{
375 return 0x005046a4;
376}
377static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
378{
379 return 0x00419ea4;
380}
381static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
382{
383 return 0x1 << 0;
384}
385static inline u32 gr_pri_sked_activity_r(void)
386{
387 return 0x00407054;
388}
389static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
390{
391 return 0x00502c80;
392}
393static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
394{
395 return 0x00502c84;
396}
397static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
398{
399 return 0x00502c88;
400}
401static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
402{
403 return 0x00502c8c;
404}
405static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
406{
407 return 0x00504500;
408}
409static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
410{
411 return 0x00504d00;
412}
413static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
414{
415 return 0x00501d00;
416}
417static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
418{
419 return 0x0041ac80;
420}
421static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
422{
423 return 0x0041ac84;
424}
425static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
426{
427 return 0x0041ac88;
428}
429static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
430{
431 return 0x0041ac8c;
432}
433static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
434{
435 return 0x0041c500;
436}
437static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
438{
439 return 0x0041cd00;
440}
441static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
442{
443 return 0x00419d00;
444}
445static inline u32 gr_pri_be0_becs_be_activity0_r(void)
446{
447 return 0x00410200;
448}
449static inline u32 gr_pri_be1_becs_be_activity0_r(void)
450{
451 return 0x00410600;
452}
453static inline u32 gr_pri_bes_becs_be_activity0_r(void)
454{
455 return 0x00408a00;
456}
457static inline u32 gr_pri_ds_mpipe_status_r(void)
458{
459 return 0x00405858;
460}
461static inline u32 gr_pri_fe_go_idle_info_r(void)
462{
463 return 0x00404194;
464}
465static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
466{
467 return 0x00504238;
468}
469static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
470{
471 return 0x005046b8;
472}
473static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void)
474{
475 return 0x10;
476}
477static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void)
478{
479 return 0x20;
480}
481static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void)
482{
483 return 0x40;
484}
485static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void)
486{
487 return 0x80;
488}
489static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void)
490{
491 return 0x100;
492}
493static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void)
494{
495 return 0x200;
496}
497static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void)
498{
499 return 0x400;
500}
501static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void)
502{
503 return 0x800;
504}
505static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void)
506{
507 return 0x005044a0;
508}
509static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void)
510{
511 return 0x1;
512}
513static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void)
514{
515 return 0x2;
516}
517static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void)
518{
519 return 0x10;
520}
521static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void)
522{
523 return 0x20;
524}
525static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void)
526{
527 return 0x100;
528}
529static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void)
530{
531 return 0x200;
532}
533static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void)
534{
535 return 0x005046bc;
536}
537static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void)
538{
539 return 0x005046c0;
540}
541static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void)
542{
543 return 0x005044a4;
544}
545static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void)
546{
547 return 0xff << 0;
548}
549static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r)
550{
551 return (r >> 0) & 0xff;
552}
553static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void)
554{
555 return 0xff << 8;
556}
557static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r)
558{
559 return (r >> 8) & 0xff;
560}
561static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void)
562{
563 return 0xff << 16;
564}
565static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r)
566{
567 return (r >> 16) & 0xff;
568}
569static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
570{
571 return 0x005042c4;
572}
573static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
574{
575 return 0x0;
576}
577static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
578{
579 return 0x1;
580}
581static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
582{
583 return 0x2;
584}
585static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void)
586{
587 return 0x00504218;
588}
589static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void)
590{
591 return 0xffff << 0;
592}
593static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r)
594{
595 return (r >> 0) & 0xffff;
596}
597static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void)
598{
599 return 0xffff << 16;
600}
601static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r)
602{
603 return (r >> 16) & 0xffff;
604}
605static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void)
606{
607 return 0x005042ec;
608}
609static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void)
610{
611 return 0xffff << 0;
612}
613static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r)
614{
615 return (r >> 0) & 0xffff;
616}
617static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void)
618{
619 return 0xffff << 16;
620}
621static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r)
622{
623 return (r >> 16) & 0xffff;
624}
625static inline u32 gr_pri_be0_crop_status1_r(void)
626{
627 return 0x00410134;
628}
629static inline u32 gr_pri_bes_crop_status1_r(void)
630{
631 return 0x00408934;
632}
633static inline u32 gr_pri_be0_zrop_status_r(void)
634{
635 return 0x00410048;
636}
637static inline u32 gr_pri_be0_zrop_status2_r(void)
638{
639 return 0x0041004c;
640}
641static inline u32 gr_pri_bes_zrop_status_r(void)
642{
643 return 0x00408848;
644}
645static inline u32 gr_pri_bes_zrop_status2_r(void)
646{
647 return 0x0040884c;
648}
649static inline u32 gr_pipe_bundle_address_r(void)
650{
651 return 0x00400200;
652}
653static inline u32 gr_pipe_bundle_address_value_v(u32 r)
654{
655 return (r >> 0) & 0xffff;
656}
657static inline u32 gr_pipe_bundle_data_r(void)
658{
659 return 0x00400204;
660}
661static inline u32 gr_pipe_bundle_config_r(void)
662{
663 return 0x00400208;
664}
665static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
666{
667 return 0x0;
668}
669static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
670{
671 return 0x80000000;
672}
673static inline u32 gr_fe_hww_esr_r(void)
674{
675 return 0x00404000;
676}
677static inline u32 gr_fe_hww_esr_reset_active_f(void)
678{
679 return 0x40000000;
680}
681static inline u32 gr_fe_hww_esr_en_enable_f(void)
682{
683 return 0x80000000;
684}
685static inline u32 gr_fe_go_idle_timeout_r(void)
686{
687 return 0x00404154;
688}
689static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
690{
691 return (v & 0xffffffff) << 0;
692}
693static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
694{
695 return 0x0;
696}
697static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
698{
699 return 0x7fffffff;
700}
701static inline u32 gr_fe_object_table_r(u32 i)
702{
703 return 0x00404200 + i*4;
704}
705static inline u32 gr_fe_object_table_nvclass_v(u32 r)
706{
707 return (r >> 0) & 0xffff;
708}
709static inline u32 gr_fe_tpc_fs_r(void)
710{
711 return 0x004041c4;
712}
713static inline u32 gr_pri_mme_shadow_raw_index_r(void)
714{
715 return 0x00404488;
716}
717static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
718{
719 return 0x80000000;
720}
721static inline u32 gr_pri_mme_shadow_raw_data_r(void)
722{
723 return 0x0040448c;
724}
725static inline u32 gr_mme_hww_esr_r(void)
726{
727 return 0x00404490;
728}
729static inline u32 gr_mme_hww_esr_reset_active_f(void)
730{
731 return 0x40000000;
732}
733static inline u32 gr_mme_hww_esr_en_enable_f(void)
734{
735 return 0x80000000;
736}
737static inline u32 gr_memfmt_hww_esr_r(void)
738{
739 return 0x00404600;
740}
741static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
742{
743 return 0x40000000;
744}
745static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
746{
747 return 0x80000000;
748}
749static inline u32 gr_fecs_cpuctl_r(void)
750{
751 return 0x00409100;
752}
753static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
754{
755 return (v & 0x1) << 1;
756}
757static inline u32 gr_fecs_cpuctl_alias_r(void)
758{
759 return 0x00409130;
760}
761static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
762{
763 return (v & 0x1) << 1;
764}
765static inline u32 gr_fecs_dmactl_r(void)
766{
767 return 0x0040910c;
768}
769static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
770{
771 return (v & 0x1) << 0;
772}
773static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
774{
775 return 0x1 << 1;
776}
777static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
778{
779 return 0x1 << 2;
780}
781static inline u32 gr_fecs_os_r(void)
782{
783 return 0x00409080;
784}
785static inline u32 gr_fecs_idlestate_r(void)
786{
787 return 0x0040904c;
788}
789static inline u32 gr_fecs_mailbox0_r(void)
790{
791 return 0x00409040;
792}
793static inline u32 gr_fecs_mailbox1_r(void)
794{
795 return 0x00409044;
796}
797static inline u32 gr_fecs_irqstat_r(void)
798{
799 return 0x00409008;
800}
801static inline u32 gr_fecs_irqmode_r(void)
802{
803 return 0x0040900c;
804}
805static inline u32 gr_fecs_irqmask_r(void)
806{
807 return 0x00409018;
808}
809static inline u32 gr_fecs_irqdest_r(void)
810{
811 return 0x0040901c;
812}
813static inline u32 gr_fecs_curctx_r(void)
814{
815 return 0x00409050;
816}
817static inline u32 gr_fecs_nxtctx_r(void)
818{
819 return 0x00409054;
820}
821static inline u32 gr_fecs_engctl_r(void)
822{
823 return 0x004090a4;
824}
825static inline u32 gr_fecs_debug1_r(void)
826{
827 return 0x00409090;
828}
829static inline u32 gr_fecs_debuginfo_r(void)
830{
831 return 0x00409094;
832}
833static inline u32 gr_fecs_icd_cmd_r(void)
834{
835 return 0x00409200;
836}
837static inline u32 gr_fecs_icd_cmd_opc_s(void)
838{
839 return 4;
840}
841static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
842{
843 return (v & 0xf) << 0;
844}
845static inline u32 gr_fecs_icd_cmd_opc_m(void)
846{
847 return 0xf << 0;
848}
849static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
850{
851 return (r >> 0) & 0xf;
852}
853static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
854{
855 return 0x8;
856}
857static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
858{
859 return 0xe;
860}
861static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
862{
863 return (v & 0x1f) << 8;
864}
865static inline u32 gr_fecs_icd_rdata_r(void)
866{
867 return 0x0040920c;
868}
869static inline u32 gr_fecs_imemc_r(u32 i)
870{
871 return 0x00409180 + i*16;
872}
873static inline u32 gr_fecs_imemc_offs_f(u32 v)
874{
875 return (v & 0x3f) << 2;
876}
877static inline u32 gr_fecs_imemc_blk_f(u32 v)
878{
879 return (v & 0xff) << 8;
880}
881static inline u32 gr_fecs_imemc_aincw_f(u32 v)
882{
883 return (v & 0x1) << 24;
884}
885static inline u32 gr_fecs_imemd_r(u32 i)
886{
887 return 0x00409184 + i*16;
888}
889static inline u32 gr_fecs_imemt_r(u32 i)
890{
891 return 0x00409188 + i*16;
892}
893static inline u32 gr_fecs_imemt_tag_f(u32 v)
894{
895 return (v & 0xffff) << 0;
896}
897static inline u32 gr_fecs_dmemc_r(u32 i)
898{
899 return 0x004091c0 + i*8;
900}
901static inline u32 gr_fecs_dmemc_offs_s(void)
902{
903 return 6;
904}
905static inline u32 gr_fecs_dmemc_offs_f(u32 v)
906{
907 return (v & 0x3f) << 2;
908}
909static inline u32 gr_fecs_dmemc_offs_m(void)
910{
911 return 0x3f << 2;
912}
913static inline u32 gr_fecs_dmemc_offs_v(u32 r)
914{
915 return (r >> 2) & 0x3f;
916}
917static inline u32 gr_fecs_dmemc_blk_f(u32 v)
918{
919 return (v & 0xff) << 8;
920}
921static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
922{
923 return (v & 0x1) << 24;
924}
925static inline u32 gr_fecs_dmemd_r(u32 i)
926{
927 return 0x004091c4 + i*8;
928}
929static inline u32 gr_fecs_dmatrfbase_r(void)
930{
931 return 0x00409110;
932}
933static inline u32 gr_fecs_dmatrfmoffs_r(void)
934{
935 return 0x00409114;
936}
937static inline u32 gr_fecs_dmatrffboffs_r(void)
938{
939 return 0x0040911c;
940}
941static inline u32 gr_fecs_dmatrfcmd_r(void)
942{
943 return 0x00409118;
944}
945static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
946{
947 return (v & 0x1) << 4;
948}
949static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
950{
951 return (v & 0x1) << 5;
952}
953static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
954{
955 return (v & 0x7) << 8;
956}
957static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
958{
959 return (v & 0x7) << 12;
960}
961static inline u32 gr_fecs_bootvec_r(void)
962{
963 return 0x00409104;
964}
965static inline u32 gr_fecs_bootvec_vec_f(u32 v)
966{
967 return (v & 0xffffffff) << 0;
968}
969static inline u32 gr_fecs_falcon_hwcfg_r(void)
970{
971 return 0x00409108;
972}
973static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
974{
975 return 0x0041a108;
976}
977static inline u32 gr_fecs_falcon_rm_r(void)
978{
979 return 0x00409084;
980}
981static inline u32 gr_fecs_current_ctx_r(void)
982{
983 return 0x00409b00;
984}
985static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
986{
987 return (v & 0xfffffff) << 0;
988}
989static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
990{
991 return (r >> 0) & 0xfffffff;
992}
993static inline u32 gr_fecs_current_ctx_target_s(void)
994{
995 return 2;
996}
997static inline u32 gr_fecs_current_ctx_target_f(u32 v)
998{
999 return (v & 0x3) << 28;
1000}
1001static inline u32 gr_fecs_current_ctx_target_m(void)
1002{
1003 return 0x3 << 28;
1004}
1005static inline u32 gr_fecs_current_ctx_target_v(u32 r)
1006{
1007 return (r >> 28) & 0x3;
1008}
1009static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
1010{
1011 return 0x0;
1012}
1013static inline u32 gr_fecs_current_ctx_valid_s(void)
1014{
1015 return 1;
1016}
1017static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
1018{
1019 return (v & 0x1) << 31;
1020}
1021static inline u32 gr_fecs_current_ctx_valid_m(void)
1022{
1023 return 0x1 << 31;
1024}
1025static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
1026{
1027 return (r >> 31) & 0x1;
1028}
1029static inline u32 gr_fecs_current_ctx_valid_false_f(void)
1030{
1031 return 0x0;
1032}
1033static inline u32 gr_fecs_method_data_r(void)
1034{
1035 return 0x00409500;
1036}
1037static inline u32 gr_fecs_method_push_r(void)
1038{
1039 return 0x00409504;
1040}
1041static inline u32 gr_fecs_method_push_adr_f(u32 v)
1042{
1043 return (v & 0xfff) << 0;
1044}
1045static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
1046{
1047 return 0x00000003;
1048}
1049static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
1050{
1051 return 0x3;
1052}
1053static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
1054{
1055 return 0x00000010;
1056}
1057static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
1058{
1059 return 0x00000009;
1060}
1061static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
1062{
1063 return 0x00000015;
1064}
1065static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
1066{
1067 return 0x00000016;
1068}
1069static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
1070{
1071 return 0x00000025;
1072}
1073static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
1074{
1075 return 0x00000030;
1076}
1077static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
1078{
1079 return 0x00000031;
1080}
1081static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
1082{
1083 return 0x00000032;
1084}
1085static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
1086{
1087 return 0x00000038;
1088}
1089static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
1090{
1091 return 0x00000039;
1092}
1093static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
1094{
1095 return 0x21;
1096}
1097static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
1098{
1099 return 0x0000003d;
1100}
1101static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
1102{
1103 return 0x0000001a;
1104}
1105static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
1106{
1107 return 0x00000004;
1108}
1109static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
1110{
1111 return 0x0000003a;
1112}
1113static inline u32 gr_fecs_host_int_status_r(void)
1114{
1115 return 0x00409c18;
1116}
1117static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
1118{
1119 return (v & 0x1) << 17;
1120}
1121static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
1122{
1123 return (v & 0x1) << 18;
1124}
1125static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
1126{
1127 return (v & 0xffff) << 0;
1128}
1129static inline u32 gr_fecs_host_int_clear_r(void)
1130{
1131 return 0x00409c20;
1132}
1133static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
1134{
1135 return (v & 0x1) << 1;
1136}
1137static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
1138{
1139 return 0x2;
1140}
1141static inline u32 gr_fecs_host_int_enable_r(void)
1142{
1143 return 0x00409c24;
1144}
1145static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
1146{
1147 return 0x2;
1148}
1149static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1150{
1151 return 0x10000;
1152}
1153static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1154{
1155 return 0x20000;
1156}
1157static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1158{
1159 return 0x40000;
1160}
1161static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1162{
1163 return 0x80000;
1164}
1165static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1166{
1167 return 0x00409614;
1168}
1169static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1170{
1171 return 0x0;
1172}
1173static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1174{
1175 return 0x0;
1176}
1177static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1178{
1179 return 0x0;
1180}
1181static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1182{
1183 return 0x10;
1184}
1185static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1186{
1187 return 0x20;
1188}
1189static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1190{
1191 return 0x40;
1192}
1193static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1194{
1195 return 0x0;
1196}
1197static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1198{
1199 return 0x100;
1200}
1201static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1202{
1203 return 0x0;
1204}
1205static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1206{
1207 return 0x200;
1208}
1209static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1210{
1211 return 1;
1212}
1213static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1214{
1215 return (v & 0x1) << 10;
1216}
1217static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1218{
1219 return 0x1 << 10;
1220}
1221static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1222{
1223 return (r >> 10) & 0x1;
1224}
1225static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1226{
1227 return 0x0;
1228}
1229static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1230{
1231 return 0x400;
1232}
1233static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1234{
1235 return 0x0040960c;
1236}
1237static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1238{
1239 return 0x00409800 + i*4;
1240}
1241static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1242{
1243 return 0x00000010;
1244}
1245static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1246{
1247 return (v & 0xffffffff) << 0;
1248}
1249static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1250{
1251 return 0x00000001;
1252}
1253static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1254{
1255 return 0x00000002;
1256}
1257static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1258{
1259 return 0x004098c0 + i*4;
1260}
1261static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1262{
1263 return (v & 0xffffffff) << 0;
1264}
1265static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1266{
1267 return 0x00409840 + i*4;
1268}
1269static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1270{
1271 return (v & 0xffffffff) << 0;
1272}
1273static inline u32 gr_fecs_fs_r(void)
1274{
1275 return 0x00409604;
1276}
1277static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1278{
1279 return 5;
1280}
1281static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1282{
1283 return (v & 0x1f) << 0;
1284}
1285static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1286{
1287 return 0x1f << 0;
1288}
1289static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1290{
1291 return (r >> 0) & 0x1f;
1292}
1293static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1294{
1295 return 5;
1296}
1297static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1298{
1299 return (v & 0x1f) << 16;
1300}
1301static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1302{
1303 return 0x1f << 16;
1304}
1305static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1306{
1307 return (r >> 16) & 0x1f;
1308}
1309static inline u32 gr_fecs_cfg_r(void)
1310{
1311 return 0x00409620;
1312}
1313static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1314{
1315 return (r >> 0) & 0xff;
1316}
1317static inline u32 gr_fecs_rc_lanes_r(void)
1318{
1319 return 0x00409880;
1320}
1321static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1322{
1323 return 6;
1324}
1325static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1326{
1327 return (v & 0x3f) << 0;
1328}
1329static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1330{
1331 return 0x3f << 0;
1332}
1333static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1334{
1335 return (r >> 0) & 0x3f;
1336}
1337static inline u32 gr_fecs_ctxsw_status_1_r(void)
1338{
1339 return 0x00409400;
1340}
1341static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1342{
1343 return 1;
1344}
1345static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1346{
1347 return (v & 0x1) << 12;
1348}
1349static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1350{
1351 return 0x1 << 12;
1352}
1353static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1354{
1355 return (r >> 12) & 0x1;
1356}
1357static inline u32 gr_fecs_arb_ctx_adr_r(void)
1358{
1359 return 0x00409a24;
1360}
1361static inline u32 gr_fecs_new_ctx_r(void)
1362{
1363 return 0x00409b04;
1364}
1365static inline u32 gr_fecs_new_ctx_ptr_s(void)
1366{
1367 return 28;
1368}
1369static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1370{
1371 return (v & 0xfffffff) << 0;
1372}
1373static inline u32 gr_fecs_new_ctx_ptr_m(void)
1374{
1375 return 0xfffffff << 0;
1376}
1377static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1378{
1379 return (r >> 0) & 0xfffffff;
1380}
1381static inline u32 gr_fecs_new_ctx_target_s(void)
1382{
1383 return 2;
1384}
1385static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1386{
1387 return (v & 0x3) << 28;
1388}
1389static inline u32 gr_fecs_new_ctx_target_m(void)
1390{
1391 return 0x3 << 28;
1392}
1393static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1394{
1395 return (r >> 28) & 0x3;
1396}
1397static inline u32 gr_fecs_new_ctx_valid_s(void)
1398{
1399 return 1;
1400}
1401static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1402{
1403 return (v & 0x1) << 31;
1404}
1405static inline u32 gr_fecs_new_ctx_valid_m(void)
1406{
1407 return 0x1 << 31;
1408}
1409static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1410{
1411 return (r >> 31) & 0x1;
1412}
1413static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1414{
1415 return 0x00409a0c;
1416}
1417static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1418{
1419 return 28;
1420}
1421static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1422{
1423 return (v & 0xfffffff) << 0;
1424}
1425static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1426{
1427 return 0xfffffff << 0;
1428}
1429static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1430{
1431 return (r >> 0) & 0xfffffff;
1432}
1433static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1434{
1435 return 2;
1436}
1437static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1438{
1439 return (v & 0x3) << 28;
1440}
1441static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1442{
1443 return 0x3 << 28;
1444}
1445static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1446{
1447 return (r >> 28) & 0x3;
1448}
1449static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1450{
1451 return 0x00409a10;
1452}
1453static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1454{
1455 return 5;
1456}
1457static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1458{
1459 return (v & 0x1f) << 0;
1460}
1461static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1462{
1463 return 0x1f << 0;
1464}
1465static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1466{
1467 return (r >> 0) & 0x1f;
1468}
1469static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1470{
1471 return 0x00409c00;
1472}
1473static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1474{
1475 return 0x00502c04;
1476}
1477static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1478{
1479 return 0x00502400;
1480}
1481static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1482{
1483 return 0x00409420;
1484}
1485static inline u32 gr_fecs_feature_override_ecc_r(void)
1486{
1487 return 0x00409658;
1488}
1489static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
1490{
1491 return (r >> 3) & 0x1;
1492}
1493static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r)
1494{
1495 return (r >> 7) & 0x1;
1496}
1497static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r)
1498{
1499 return (r >> 11) & 0x1;
1500}
1501static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
1502{
1503 return (r >> 15) & 0x1;
1504}
1505static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
1506{
1507 return (r >> 0) & 0x1;
1508}
1509static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r)
1510{
1511 return (r >> 4) & 0x1;
1512}
1513static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r)
1514{
1515 return (r >> 8) & 0x1;
1516}
1517static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
1518{
1519 return (r >> 12) & 0x1;
1520}
1521static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1522{
1523 return 0x00502420;
1524}
1525static inline u32 gr_rstr2d_gpc_map0_r(void)
1526{
1527 return 0x0040780c;
1528}
1529static inline u32 gr_rstr2d_gpc_map1_r(void)
1530{
1531 return 0x00407810;
1532}
1533static inline u32 gr_rstr2d_gpc_map2_r(void)
1534{
1535 return 0x00407814;
1536}
1537static inline u32 gr_rstr2d_gpc_map3_r(void)
1538{
1539 return 0x00407818;
1540}
1541static inline u32 gr_rstr2d_gpc_map4_r(void)
1542{
1543 return 0x0040781c;
1544}
1545static inline u32 gr_rstr2d_gpc_map5_r(void)
1546{
1547 return 0x00407820;
1548}
1549static inline u32 gr_rstr2d_map_table_cfg_r(void)
1550{
1551 return 0x004078bc;
1552}
1553static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1554{
1555 return (v & 0xff) << 0;
1556}
1557static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1558{
1559 return (v & 0xff) << 8;
1560}
1561static inline u32 gr_pd_hww_esr_r(void)
1562{
1563 return 0x00406018;
1564}
1565static inline u32 gr_pd_hww_esr_reset_active_f(void)
1566{
1567 return 0x40000000;
1568}
1569static inline u32 gr_pd_hww_esr_en_enable_f(void)
1570{
1571 return 0x80000000;
1572}
1573static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1574{
1575 return 0x00406028 + i*4;
1576}
1577static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1578{
1579 return 0x00000004;
1580}
1581static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1582{
1583 return (v & 0xf) << 0;
1584}
1585static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1586{
1587 return (v & 0xf) << 4;
1588}
1589static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1590{
1591 return (v & 0xf) << 8;
1592}
1593static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1594{
1595 return (v & 0xf) << 12;
1596}
1597static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1598{
1599 return (v & 0xf) << 16;
1600}
1601static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1602{
1603 return (v & 0xf) << 20;
1604}
1605static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1606{
1607 return (v & 0xf) << 24;
1608}
1609static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1610{
1611 return (v & 0xf) << 28;
1612}
1613static inline u32 gr_pd_ab_dist_cfg0_r(void)
1614{
1615 return 0x004064c0;
1616}
1617static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1618{
1619 return 0x80000000;
1620}
1621static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1622{
1623 return 0x0;
1624}
1625static inline u32 gr_pd_ab_dist_cfg1_r(void)
1626{
1627 return 0x004064c4;
1628}
1629static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1630{
1631 return 0xffff;
1632}
1633static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1634{
1635 return (v & 0xffff) << 16;
1636}
1637static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1638{
1639 return 0x00000080;
1640}
1641static inline u32 gr_pd_ab_dist_cfg2_r(void)
1642{
1643 return 0x004064c8;
1644}
1645static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1646{
1647 return (v & 0x1fff) << 0;
1648}
1649static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1650{
1651 return 0x000001c0;
1652}
1653static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1654{
1655 return (v & 0x1fff) << 16;
1656}
1657static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1658{
1659 return 0x00000020;
1660}
1661static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1662{
1663 return 0x00000182;
1664}
1665static inline u32 gr_pd_dist_skip_table_r(u32 i)
1666{
1667 return 0x004064d0 + i*4;
1668}
1669static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1670{
1671 return 0x00000008;
1672}
1673static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1674{
1675 return (v & 0xff) << 0;
1676}
1677static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1678{
1679 return (v & 0xff) << 8;
1680}
1681static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1682{
1683 return (v & 0xff) << 16;
1684}
1685static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1686{
1687 return (v & 0xff) << 24;
1688}
1689static inline u32 gr_ds_debug_r(void)
1690{
1691 return 0x00405800;
1692}
1693static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1694{
1695 return 0x0;
1696}
1697static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1698{
1699 return 0x8000000;
1700}
1701static inline u32 gr_ds_zbc_color_r_r(void)
1702{
1703 return 0x00405804;
1704}
1705static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1706{
1707 return (v & 0xffffffff) << 0;
1708}
1709static inline u32 gr_ds_zbc_color_g_r(void)
1710{
1711 return 0x00405808;
1712}
1713static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1714{
1715 return (v & 0xffffffff) << 0;
1716}
1717static inline u32 gr_ds_zbc_color_b_r(void)
1718{
1719 return 0x0040580c;
1720}
1721static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1722{
1723 return (v & 0xffffffff) << 0;
1724}
1725static inline u32 gr_ds_zbc_color_a_r(void)
1726{
1727 return 0x00405810;
1728}
1729static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1730{
1731 return (v & 0xffffffff) << 0;
1732}
1733static inline u32 gr_ds_zbc_color_fmt_r(void)
1734{
1735 return 0x00405814;
1736}
1737static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1738{
1739 return (v & 0x7f) << 0;
1740}
1741static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1742{
1743 return 0x0;
1744}
1745static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1746{
1747 return 0x00000001;
1748}
1749static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1750{
1751 return 0x00000002;
1752}
1753static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1754{
1755 return 0x00000004;
1756}
1757static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1758{
1759 return 0x00000028;
1760}
1761static inline u32 gr_ds_zbc_z_r(void)
1762{
1763 return 0x00405818;
1764}
1765static inline u32 gr_ds_zbc_z_val_s(void)
1766{
1767 return 32;
1768}
1769static inline u32 gr_ds_zbc_z_val_f(u32 v)
1770{
1771 return (v & 0xffffffff) << 0;
1772}
1773static inline u32 gr_ds_zbc_z_val_m(void)
1774{
1775 return 0xffffffff << 0;
1776}
1777static inline u32 gr_ds_zbc_z_val_v(u32 r)
1778{
1779 return (r >> 0) & 0xffffffff;
1780}
1781static inline u32 gr_ds_zbc_z_val__init_v(void)
1782{
1783 return 0x00000000;
1784}
1785static inline u32 gr_ds_zbc_z_val__init_f(void)
1786{
1787 return 0x0;
1788}
1789static inline u32 gr_ds_zbc_z_fmt_r(void)
1790{
1791 return 0x0040581c;
1792}
1793static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1794{
1795 return (v & 0x1) << 0;
1796}
1797static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1798{
1799 return 0x0;
1800}
1801static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1802{
1803 return 0x00000001;
1804}
1805static inline u32 gr_ds_zbc_tbl_index_r(void)
1806{
1807 return 0x00405820;
1808}
1809static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1810{
1811 return (v & 0xf) << 0;
1812}
1813static inline u32 gr_ds_zbc_tbl_ld_r(void)
1814{
1815 return 0x00405824;
1816}
1817static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1818{
1819 return 0x0;
1820}
1821static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1822{
1823 return 0x1;
1824}
1825static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1826{
1827 return 0x0;
1828}
1829static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1830{
1831 return 0x4;
1832}
1833static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
1834{
1835 return 0x00405830;
1836}
1837static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1838{
1839 return (v & 0x3fffff) << 0;
1840}
1841static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
1842{
1843 return 0x0040585c;
1844}
1845static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1846{
1847 return (v & 0xffff) << 0;
1848}
1849static inline u32 gr_ds_hww_esr_r(void)
1850{
1851 return 0x00405840;
1852}
1853static inline u32 gr_ds_hww_esr_reset_s(void)
1854{
1855 return 1;
1856}
1857static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1858{
1859 return (v & 0x1) << 30;
1860}
1861static inline u32 gr_ds_hww_esr_reset_m(void)
1862{
1863 return 0x1 << 30;
1864}
1865static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1866{
1867 return (r >> 30) & 0x1;
1868}
1869static inline u32 gr_ds_hww_esr_reset_task_v(void)
1870{
1871 return 0x00000001;
1872}
1873static inline u32 gr_ds_hww_esr_reset_task_f(void)
1874{
1875 return 0x40000000;
1876}
1877static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1878{
1879 return 0x80000000;
1880}
1881static inline u32 gr_ds_hww_esr_2_r(void)
1882{
1883 return 0x00405848;
1884}
1885static inline u32 gr_ds_hww_esr_2_reset_s(void)
1886{
1887 return 1;
1888}
1889static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
1890{
1891 return (v & 0x1) << 30;
1892}
1893static inline u32 gr_ds_hww_esr_2_reset_m(void)
1894{
1895 return 0x1 << 30;
1896}
1897static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
1898{
1899 return (r >> 30) & 0x1;
1900}
1901static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
1902{
1903 return 0x00000001;
1904}
1905static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
1906{
1907 return 0x40000000;
1908}
1909static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
1910{
1911 return 0x80000000;
1912}
1913static inline u32 gr_ds_hww_report_mask_r(void)
1914{
1915 return 0x00405844;
1916}
1917static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1918{
1919 return 0x1;
1920}
1921static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1922{
1923 return 0x2;
1924}
1925static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1926{
1927 return 0x4;
1928}
1929static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1930{
1931 return 0x8;
1932}
1933static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1934{
1935 return 0x10;
1936}
1937static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1938{
1939 return 0x20;
1940}
1941static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1942{
1943 return 0x40;
1944}
1945static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1946{
1947 return 0x80;
1948}
1949static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1950{
1951 return 0x100;
1952}
1953static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1954{
1955 return 0x200;
1956}
1957static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1958{
1959 return 0x400;
1960}
1961static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1962{
1963 return 0x800;
1964}
1965static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
1966{
1967 return 0x1000;
1968}
1969static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
1970{
1971 return 0x2000;
1972}
1973static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
1974{
1975 return 0x4000;
1976}
1977static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
1978{
1979 return 0x8000;
1980}
1981static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
1982{
1983 return 0x10000;
1984}
1985static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
1986{
1987 return 0x20000;
1988}
1989static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
1990{
1991 return 0x40000;
1992}
1993static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
1994{
1995 return 0x80000;
1996}
1997static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
1998{
1999 return 0x100000;
2000}
2001static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
2002{
2003 return 0x200000;
2004}
2005static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
2006{
2007 return 0x400000;
2008}
2009static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
2010{
2011 return 0x800000;
2012}
2013static inline u32 gr_ds_hww_report_mask_2_r(void)
2014{
2015 return 0x0040584c;
2016}
2017static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
2018{
2019 return 0x1;
2020}
2021static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
2022{
2023 return 0x00405870 + i*4;
2024}
2025static inline u32 gr_scc_bundle_cb_base_r(void)
2026{
2027 return 0x00408004;
2028}
2029static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
2030{
2031 return (v & 0xffffffff) << 0;
2032}
2033static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
2034{
2035 return 0x00000008;
2036}
2037static inline u32 gr_scc_bundle_cb_size_r(void)
2038{
2039 return 0x00408008;
2040}
2041static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
2042{
2043 return (v & 0x7ff) << 0;
2044}
2045static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
2046{
2047 return 0x00000018;
2048}
2049static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
2050{
2051 return 0x00000100;
2052}
2053static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
2054{
2055 return 0x00000000;
2056}
2057static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
2058{
2059 return 0x0;
2060}
2061static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
2062{
2063 return 0x80000000;
2064}
2065static inline u32 gr_scc_pagepool_base_r(void)
2066{
2067 return 0x0040800c;
2068}
2069static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
2070{
2071 return (v & 0xffffffff) << 0;
2072}
2073static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
2074{
2075 return 0x00000008;
2076}
2077static inline u32 gr_scc_pagepool_r(void)
2078{
2079 return 0x00408010;
2080}
2081static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
2082{
2083 return (v & 0x3ff) << 0;
2084}
2085static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
2086{
2087 return 0x00000000;
2088}
2089static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
2090{
2091 return 0x00000200;
2092}
2093static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
2094{
2095 return 0x00000100;
2096}
2097static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
2098{
2099 return 10;
2100}
2101static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
2102{
2103 return (v & 0x3ff) << 10;
2104}
2105static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
2106{
2107 return 0x3ff << 10;
2108}
2109static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
2110{
2111 return (r >> 10) & 0x3ff;
2112}
2113static inline u32 gr_scc_pagepool_valid_true_f(void)
2114{
2115 return 0x80000000;
2116}
2117static inline u32 gr_scc_init_r(void)
2118{
2119 return 0x0040802c;
2120}
2121static inline u32 gr_scc_init_ram_trigger_f(void)
2122{
2123 return 0x1;
2124}
2125static inline u32 gr_scc_hww_esr_r(void)
2126{
2127 return 0x00408030;
2128}
2129static inline u32 gr_scc_hww_esr_reset_active_f(void)
2130{
2131 return 0x40000000;
2132}
2133static inline u32 gr_scc_hww_esr_en_enable_f(void)
2134{
2135 return 0x80000000;
2136}
2137static inline u32 gr_sked_hww_esr_r(void)
2138{
2139 return 0x00407020;
2140}
2141static inline u32 gr_sked_hww_esr_reset_active_f(void)
2142{
2143 return 0x40000000;
2144}
2145static inline u32 gr_cwd_fs_r(void)
2146{
2147 return 0x00405b00;
2148}
2149static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2150{
2151 return (v & 0xff) << 0;
2152}
2153static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2154{
2155 return (v & 0xff) << 8;
2156}
2157static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
2158{
2159 return 0x00405b60 + i*4;
2160}
2161static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
2162{
2163 return (v & 0xf) << 0;
2164}
2165static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2166{
2167 return (v & 0xf) << 8;
2168}
2169static inline u32 gr_cwd_sm_id_r(u32 i)
2170{
2171 return 0x00405ba0 + i*4;
2172}
2173static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2174{
2175 return (v & 0xff) << 0;
2176}
2177static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
2178{
2179 return (v & 0xff) << 8;
2180}
2181static inline u32 gr_gpc0_fs_gpc_r(void)
2182{
2183 return 0x00502608;
2184}
2185static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2186{
2187 return (r >> 0) & 0x1f;
2188}
2189static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2190{
2191 return (r >> 16) & 0x1f;
2192}
2193static inline u32 gr_gpc0_cfg_r(void)
2194{
2195 return 0x00502620;
2196}
2197static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2198{
2199 return (r >> 0) & 0xff;
2200}
2201static inline u32 gr_gpccs_rc_lanes_r(void)
2202{
2203 return 0x00502880;
2204}
2205static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2206{
2207 return 6;
2208}
2209static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2210{
2211 return (v & 0x3f) << 0;
2212}
2213static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2214{
2215 return 0x3f << 0;
2216}
2217static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2218{
2219 return (r >> 0) & 0x3f;
2220}
2221static inline u32 gr_gpccs_rc_lane_size_r(void)
2222{
2223 return 0x00502910;
2224}
2225static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2226{
2227 return 24;
2228}
2229static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2230{
2231 return (v & 0xffffff) << 0;
2232}
2233static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2234{
2235 return 0xffffff << 0;
2236}
2237static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2238{
2239 return (r >> 0) & 0xffffff;
2240}
2241static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2242{
2243 return 0x00000000;
2244}
2245static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2246{
2247 return 0x0;
2248}
2249static inline u32 gr_gpc0_zcull_fs_r(void)
2250{
2251 return 0x00500910;
2252}
2253static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2254{
2255 return (v & 0x1ff) << 0;
2256}
2257static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2258{
2259 return (v & 0xf) << 16;
2260}
2261static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2262{
2263 return 0x00500914;
2264}
2265static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2266{
2267 return (v & 0xf) << 0;
2268}
2269static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2270{
2271 return (v & 0xf) << 8;
2272}
2273static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2274{
2275 return 0x00500918;
2276}
2277static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2278{
2279 return (v & 0xffffff) << 0;
2280}
2281static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2282{
2283 return 0x00800000;
2284}
2285static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2286{
2287 return 0x00500920;
2288}
2289static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2290{
2291 return (v & 0xffff) << 0;
2292}
2293static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2294{
2295 return 0x00500a04 + i*32;
2296}
2297static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2298{
2299 return 0x00000040;
2300}
2301static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2302{
2303 return 0x00000010;
2304}
2305static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2306{
2307 return 0x00500c10 + i*4;
2308}
2309static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2310{
2311 return (v & 0xff) << 0;
2312}
2313static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2314{
2315 return 0x00500c30 + i*4;
2316}
2317static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2318{
2319 return (r >> 0) & 0xff;
2320}
2321static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2322{
2323 return 0x00504088;
2324}
2325static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2326{
2327 return (v & 0xffff) << 0;
2328}
2329static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2330{
2331 return 0x00504698;
2332}
2333static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2334{
2335 return (v & 0xffff) << 0;
2336}
2337static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
2338{
2339 return (r >> 0) & 0xffff;
2340}
2341static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2342{
2343 return 0x0050469c;
2344}
2345static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2346{
2347 return (r >> 0) & 0xff;
2348}
2349static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2350{
2351 return (r >> 8) & 0xfff;
2352}
2353static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2354{
2355 return (r >> 20) & 0xfff;
2356}
2357static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2358{
2359 return 0x00503018;
2360}
2361static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2362{
2363 return 0x1 << 0;
2364}
2365static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2366{
2367 return 0x1;
2368}
2369static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2370{
2371 return 0x005030c0;
2372}
2373static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2374{
2375 return (v & 0x3fffff) << 0;
2376}
2377static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2378{
2379 return 0x3fffff << 0;
2380}
2381static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2382{
2383 return 0x00030000;
2384}
2385static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
2386{
2387 return 0x00030a00;
2388}
2389static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2390{
2391 return 0x00000020;
2392}
2393static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2394{
2395 return 0x005030f4;
2396}
2397static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2398{
2399 return 0x005030e4;
2400}
2401static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2402{
2403 return (v & 0xffff) << 0;
2404}
2405static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2406{
2407 return 0xffff << 0;
2408}
2409static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2410{
2411 return 0x00000800;
2412}
2413static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2414{
2415 return 0x00000020;
2416}
2417static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2418{
2419 return 0x005030f8;
2420}
2421static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
2422{
2423 return 0x005030f0;
2424}
2425static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
2426{
2427 return (v & 0x3fffff) << 0;
2428}
2429static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
2430{
2431 return 0x00030000;
2432}
2433static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
2434{
2435 return 0x00419b00;
2436}
2437static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
2438{
2439 return (v & 0xffffffff) << 0;
2440}
2441static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
2442{
2443 return 0x00419b04;
2444}
2445static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
2446{
2447 return 21;
2448}
2449static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
2450{
2451 return (v & 0x1fffff) << 0;
2452}
2453static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
2454{
2455 return 0x1fffff << 0;
2456}
2457static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
2458{
2459 return (r >> 0) & 0x1fffff;
2460}
2461static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
2462{
2463 return 0x80;
2464}
2465static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
2466{
2467 return 1;
2468}
2469static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
2470{
2471 return (v & 0x1) << 31;
2472}
2473static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
2474{
2475 return 0x1 << 31;
2476}
2477static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
2478{
2479 return (r >> 31) & 0x1;
2480}
2481static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
2482{
2483 return 0x80000000;
2484}
2485static inline u32 gr_gpccs_falcon_addr_r(void)
2486{
2487 return 0x0041a0ac;
2488}
2489static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2490{
2491 return 6;
2492}
2493static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2494{
2495 return (v & 0x3f) << 0;
2496}
2497static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2498{
2499 return 0x3f << 0;
2500}
2501static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2502{
2503 return (r >> 0) & 0x3f;
2504}
2505static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2506{
2507 return 0x00000000;
2508}
2509static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2510{
2511 return 0x0;
2512}
2513static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2514{
2515 return 6;
2516}
2517static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2518{
2519 return (v & 0x3f) << 6;
2520}
2521static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2522{
2523 return 0x3f << 6;
2524}
2525static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2526{
2527 return (r >> 6) & 0x3f;
2528}
2529static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2530{
2531 return 0x00000000;
2532}
2533static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2534{
2535 return 0x0;
2536}
2537static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2538{
2539 return 12;
2540}
2541static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2542{
2543 return (v & 0xfff) << 0;
2544}
2545static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2546{
2547 return 0xfff << 0;
2548}
2549static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2550{
2551 return (r >> 0) & 0xfff;
2552}
2553static inline u32 gr_gpccs_cpuctl_r(void)
2554{
2555 return 0x0041a100;
2556}
2557static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2558{
2559 return (v & 0x1) << 1;
2560}
2561static inline u32 gr_gpccs_dmactl_r(void)
2562{
2563 return 0x0041a10c;
2564}
2565static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2566{
2567 return (v & 0x1) << 0;
2568}
2569static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2570{
2571 return 0x1 << 1;
2572}
2573static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2574{
2575 return 0x1 << 2;
2576}
2577static inline u32 gr_gpccs_imemc_r(u32 i)
2578{
2579 return 0x0041a180 + i*16;
2580}
2581static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2582{
2583 return (v & 0x3f) << 2;
2584}
2585static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2586{
2587 return (v & 0xff) << 8;
2588}
2589static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2590{
2591 return (v & 0x1) << 24;
2592}
2593static inline u32 gr_gpccs_imemd_r(u32 i)
2594{
2595 return 0x0041a184 + i*16;
2596}
2597static inline u32 gr_gpccs_imemt_r(u32 i)
2598{
2599 return 0x0041a188 + i*16;
2600}
2601static inline u32 gr_gpccs_imemt__size_1_v(void)
2602{
2603 return 0x00000004;
2604}
2605static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2606{
2607 return (v & 0xffff) << 0;
2608}
2609static inline u32 gr_gpccs_dmemc_r(u32 i)
2610{
2611 return 0x0041a1c0 + i*8;
2612}
2613static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2614{
2615 return (v & 0x3f) << 2;
2616}
2617static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2618{
2619 return (v & 0xff) << 8;
2620}
2621static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2622{
2623 return (v & 0x1) << 24;
2624}
2625static inline u32 gr_gpccs_dmemd_r(u32 i)
2626{
2627 return 0x0041a1c4 + i*8;
2628}
2629static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2630{
2631 return 0x0041a800 + i*4;
2632}
2633static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2634{
2635 return (v & 0xffffffff) << 0;
2636}
2637static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
2638{
2639 return 0x00418e24;
2640}
2641static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
2642{
2643 return 32;
2644}
2645static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
2646{
2647 return (v & 0xffffffff) << 0;
2648}
2649static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
2650{
2651 return 0xffffffff << 0;
2652}
2653static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
2654{
2655 return (r >> 0) & 0xffffffff;
2656}
2657static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
2658{
2659 return 0x00000000;
2660}
2661static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
2662{
2663 return 0x0;
2664}
2665static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
2666{
2667 return 0x00418e28;
2668}
2669static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
2670{
2671 return 11;
2672}
2673static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
2674{
2675 return (v & 0x7ff) << 0;
2676}
2677static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
2678{
2679 return 0x7ff << 0;
2680}
2681static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
2682{
2683 return (r >> 0) & 0x7ff;
2684}
2685static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
2686{
2687 return 0x00000018;
2688}
2689static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
2690{
2691 return 0x18;
2692}
2693static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
2694{
2695 return 1;
2696}
2697static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
2698{
2699 return (v & 0x1) << 31;
2700}
2701static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
2702{
2703 return 0x1 << 31;
2704}
2705static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
2706{
2707 return (r >> 31) & 0x1;
2708}
2709static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
2710{
2711 return 0x00000000;
2712}
2713static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
2714{
2715 return 0x0;
2716}
2717static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
2718{
2719 return 0x00000001;
2720}
2721static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
2722{
2723 return 0x80000000;
2724}
2725static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
2726{
2727 return 0x00500ee4;
2728}
2729static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
2730{
2731 return (v & 0xffff) << 0;
2732}
2733static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
2734{
2735 return 0x00000250;
2736}
2737static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
2738{
2739 return 0x00000100;
2740}
2741static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
2742{
2743 return 0x00500ee0;
2744}
2745static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
2746{
2747 return (v & 0xffffffff) << 0;
2748}
2749static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
2750{
2751 return 0x00000008;
2752}
2753static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
2754{
2755 return 0x00418eec;
2756}
2757static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
2758{
2759 return (v & 0xfff) << 0;
2760}
2761static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
2762{
2763 return 0x00000100;
2764}
2765static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
2766{
2767 return 0x0041befc;
2768}
2769static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
2770{
2771 return (v & 0xfff) << 0;
2772}
2773static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
2774{
2775 return 0x00418ea0 + i*4;
2776}
2777static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
2778{
2779 return (v & 0x3fffff) << 0;
2780}
2781static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
2782{
2783 return 0x3fffff << 0;
2784}
2785static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
2786{
2787 return 0x00418010 + i*4;
2788}
2789static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
2790{
2791 return (v & 0xffffffff) << 0;
2792}
2793static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
2794{
2795 return 0x0041804c + i*4;
2796}
2797static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
2798{
2799 return (v & 0xffffffff) << 0;
2800}
2801static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
2802{
2803 return 0x00418088 + i*4;
2804}
2805static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
2806{
2807 return (v & 0xffffffff) << 0;
2808}
2809static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
2810{
2811 return 0x004180c4 + i*4;
2812}
2813static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
2814{
2815 return (v & 0xffffffff) << 0;
2816}
2817static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
2818{
2819 return 0x00500100;
2820}
2821static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
2822{
2823 return 0x00418110 + i*4;
2824}
2825static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
2826{
2827 return (v & 0xffffffff) << 0;
2828}
2829static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
2830{
2831 return 0x0050014c;
2832}
2833static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2834{
2835 return 0x00418810;
2836}
2837static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2838{
2839 return (v & 0xfffffff) << 0;
2840}
2841static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2842{
2843 return 0x0000000c;
2844}
2845static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2846{
2847 return 0x80000000;
2848}
2849static inline u32 gr_crstr_gpc_map0_r(void)
2850{
2851 return 0x00418b08;
2852}
2853static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2854{
2855 return (v & 0x7) << 0;
2856}
2857static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2858{
2859 return (v & 0x7) << 5;
2860}
2861static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2862{
2863 return (v & 0x7) << 10;
2864}
2865static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2866{
2867 return (v & 0x7) << 15;
2868}
2869static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2870{
2871 return (v & 0x7) << 20;
2872}
2873static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2874{
2875 return (v & 0x7) << 25;
2876}
2877static inline u32 gr_crstr_gpc_map1_r(void)
2878{
2879 return 0x00418b0c;
2880}
2881static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2882{
2883 return (v & 0x7) << 0;
2884}
2885static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2886{
2887 return (v & 0x7) << 5;
2888}
2889static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2890{
2891 return (v & 0x7) << 10;
2892}
2893static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2894{
2895 return (v & 0x7) << 15;
2896}
2897static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2898{
2899 return (v & 0x7) << 20;
2900}
2901static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2902{
2903 return (v & 0x7) << 25;
2904}
2905static inline u32 gr_crstr_gpc_map2_r(void)
2906{
2907 return 0x00418b10;
2908}
2909static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2910{
2911 return (v & 0x7) << 0;
2912}
2913static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2914{
2915 return (v & 0x7) << 5;
2916}
2917static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2918{
2919 return (v & 0x7) << 10;
2920}
2921static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2922{
2923 return (v & 0x7) << 15;
2924}
2925static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2926{
2927 return (v & 0x7) << 20;
2928}
2929static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2930{
2931 return (v & 0x7) << 25;
2932}
2933static inline u32 gr_crstr_gpc_map3_r(void)
2934{
2935 return 0x00418b14;
2936}
2937static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2938{
2939 return (v & 0x7) << 0;
2940}
2941static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2942{
2943 return (v & 0x7) << 5;
2944}
2945static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2946{
2947 return (v & 0x7) << 10;
2948}
2949static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
2950{
2951 return (v & 0x7) << 15;
2952}
2953static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
2954{
2955 return (v & 0x7) << 20;
2956}
2957static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
2958{
2959 return (v & 0x7) << 25;
2960}
2961static inline u32 gr_crstr_gpc_map4_r(void)
2962{
2963 return 0x00418b18;
2964}
2965static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
2966{
2967 return (v & 0x7) << 0;
2968}
2969static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
2970{
2971 return (v & 0x7) << 5;
2972}
2973static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
2974{
2975 return (v & 0x7) << 10;
2976}
2977static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
2978{
2979 return (v & 0x7) << 15;
2980}
2981static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
2982{
2983 return (v & 0x7) << 20;
2984}
2985static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
2986{
2987 return (v & 0x7) << 25;
2988}
2989static inline u32 gr_crstr_gpc_map5_r(void)
2990{
2991 return 0x00418b1c;
2992}
2993static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
2994{
2995 return (v & 0x7) << 0;
2996}
2997static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
2998{
2999 return (v & 0x7) << 5;
3000}
3001static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
3002{
3003 return (v & 0x7) << 10;
3004}
3005static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
3006{
3007 return (v & 0x7) << 15;
3008}
3009static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
3010{
3011 return (v & 0x7) << 20;
3012}
3013static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
3014{
3015 return (v & 0x7) << 25;
3016}
3017static inline u32 gr_crstr_map_table_cfg_r(void)
3018{
3019 return 0x00418bb8;
3020}
3021static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
3022{
3023 return (v & 0xff) << 0;
3024}
3025static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
3026{
3027 return (v & 0xff) << 8;
3028}
3029static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
3030{
3031 return 0x00418980;
3032}
3033static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
3034{
3035 return (v & 0x7) << 0;
3036}
3037static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
3038{
3039 return (v & 0x7) << 4;
3040}
3041static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
3042{
3043 return (v & 0x7) << 8;
3044}
3045static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
3046{
3047 return (v & 0x7) << 12;
3048}
3049static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
3050{
3051 return (v & 0x7) << 16;
3052}
3053static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
3054{
3055 return (v & 0x7) << 20;
3056}
3057static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
3058{
3059 return (v & 0x7) << 24;
3060}
3061static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
3062{
3063 return (v & 0x7) << 28;
3064}
3065static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
3066{
3067 return 0x00418984;
3068}
3069static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
3070{
3071 return (v & 0x7) << 0;
3072}
3073static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
3074{
3075 return (v & 0x7) << 4;
3076}
3077static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
3078{
3079 return (v & 0x7) << 8;
3080}
3081static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
3082{
3083 return (v & 0x7) << 12;
3084}
3085static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
3086{
3087 return (v & 0x7) << 16;
3088}
3089static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
3090{
3091 return (v & 0x7) << 20;
3092}
3093static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
3094{
3095 return (v & 0x7) << 24;
3096}
3097static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
3098{
3099 return (v & 0x7) << 28;
3100}
3101static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
3102{
3103 return 0x00418988;
3104}
3105static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
3106{
3107 return (v & 0x7) << 0;
3108}
3109static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
3110{
3111 return (v & 0x7) << 4;
3112}
3113static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
3114{
3115 return (v & 0x7) << 8;
3116}
3117static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
3118{
3119 return (v & 0x7) << 12;
3120}
3121static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
3122{
3123 return (v & 0x7) << 16;
3124}
3125static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
3126{
3127 return (v & 0x7) << 20;
3128}
3129static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
3130{
3131 return (v & 0x7) << 24;
3132}
3133static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
3134{
3135 return 3;
3136}
3137static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
3138{
3139 return (v & 0x7) << 28;
3140}
3141static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
3142{
3143 return 0x7 << 28;
3144}
3145static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
3146{
3147 return (r >> 28) & 0x7;
3148}
3149static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
3150{
3151 return 0x0041898c;
3152}
3153static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
3154{
3155 return (v & 0x7) << 0;
3156}
3157static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
3158{
3159 return (v & 0x7) << 4;
3160}
3161static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
3162{
3163 return (v & 0x7) << 8;
3164}
3165static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
3166{
3167 return (v & 0x7) << 12;
3168}
3169static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
3170{
3171 return (v & 0x7) << 16;
3172}
3173static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
3174{
3175 return (v & 0x7) << 20;
3176}
3177static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
3178{
3179 return (v & 0x7) << 24;
3180}
3181static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
3182{
3183 return (v & 0x7) << 28;
3184}
3185static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
3186{
3187 return 0x00418c6c;
3188}
3189static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
3190{
3191 return 0x0;
3192}
3193static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
3194{
3195 return 0x1;
3196}
3197static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
3198{
3199 return 0x00419004;
3200}
3201static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
3202{
3203 return (v & 0xffffffff) << 0;
3204}
3205static inline u32 gr_gpcs_gcc_pagepool_r(void)
3206{
3207 return 0x00419008;
3208}
3209static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
3210{
3211 return (v & 0x3ff) << 0;
3212}
3213static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
3214{
3215 return 0x0041980c;
3216}
3217static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
3218{
3219 return 0x10;
3220}
3221static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
3222{
3223 return 0x00419848;
3224}
3225static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
3226{
3227 return (v & 0xfffffff) << 0;
3228}
3229static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
3230{
3231 return (v & 0x1) << 28;
3232}
3233static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
3234{
3235 return 0x10000000;
3236}
3237static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
3238{
3239 return 0x00419c00;
3240}
3241static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
3242{
3243 return 0x0;
3244}
3245static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
3246{
3247 return 0x8;
3248}
3249static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
3250{
3251 return 0x00419c2c;
3252}
3253static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
3254{
3255 return (v & 0xfffffff) << 0;
3256}
3257static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
3258{
3259 return (v & 0x1) << 28;
3260}
3261static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
3262{
3263 return 0x10000000;
3264}
3265static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
3266{
3267 return 0x00419e44;
3268}
3269static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
3270{
3271 return 0x2;
3272}
3273static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3274{
3275 return 0x4;
3276}
3277static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
3278{
3279 return 0x8;
3280}
3281static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3282{
3283 return 0x10;
3284}
3285static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3286{
3287 return 0x20;
3288}
3289static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3290{
3291 return 0x40;
3292}
3293static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
3294{
3295 return 0x80;
3296}
3297static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3298{
3299 return 0x100;
3300}
3301static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3302{
3303 return 0x200;
3304}
3305static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
3306{
3307 return 0x400;
3308}
3309static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3310{
3311 return 0x800;
3312}
3313static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
3314{
3315 return 0x1000;
3316}
3317static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
3318{
3319 return 0x2000;
3320}
3321static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
3322{
3323 return 0x4000;
3324}
3325static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3326{
3327 return 0x8000;
3328}
3329static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3330{
3331 return 0x10000;
3332}
3333static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
3334{
3335 return 0x20000;
3336}
3337static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3338{
3339 return 0x40000;
3340}
3341static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
3342{
3343 return 0x800000;
3344}
3345static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
3346{
3347 return 0x400000;
3348}
3349static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
3350{
3351 return 0x80000;
3352}
3353static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
3354{
3355 return 0x100000;
3356}
3357static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
3358{
3359 return 0x00419e4c;
3360}
3361static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3362{
3363 return 0x1;
3364}
3365static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3366{
3367 return 0x2;
3368}
3369static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3370{
3371 return 0x4;
3372}
3373static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3374{
3375 return 0x8;
3376}
3377static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3378{
3379 return 0x10;
3380}
3381static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void)
3382{
3383 return 0x20000000;
3384}
3385static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void)
3386{
3387 return 0x40000000;
3388}
3389static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3390{
3391 return 0x20;
3392}
3393static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3394{
3395 return 0x40;
3396}
3397static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3398{
3399 return 0x00419d0c;
3400}
3401static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3402{
3403 return 0x2;
3404}
3405static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3406{
3407 return 0x1;
3408}
3409static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3410{
3411 return 0x0050450c;
3412}
3413static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3414{
3415 return (r >> 1) & 0x1;
3416}
3417static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3418{
3419 return 0x2;
3420}
3421static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3422{
3423 return 0x0041ac94;
3424}
3425static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3426{
3427 return (v & 0xff) << 16;
3428}
3429static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3430{
3431 return 0x00502c90;
3432}
3433static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3434{
3435 return (r >> 16) & 0xff;
3436}
3437static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3438{
3439 return 0x00000001;
3440}
3441static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3442{
3443 return 0x00504508;
3444}
3445static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3446{
3447 return (r >> 0) & 0x1;
3448}
3449static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3450{
3451 return 0x00000001;
3452}
3453static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3454{
3455 return (r >> 1) & 0x1;
3456}
3457static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3458{
3459 return 0x00000001;
3460}
3461static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3462{
3463 return 0x00504610;
3464}
3465static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3466{
3467 return (r >> 0) & 0x1;
3468}
3469static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3470{
3471 return 0x00000001;
3472}
3473static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3474{
3475 return 0x00000000;
3476}
3477static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3478{
3479 return 0x80000000;
3480}
3481static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3482{
3483 return 0x0;
3484}
3485static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
3486{
3487 return 0x8;
3488}
3489static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
3490{
3491 return 0x0;
3492}
3493static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3494{
3495 return 0x40000000;
3496}
3497static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3498{
3499 return (r >> 1) & 0x1;
3500}
3501static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3502{
3503 return 0x0;
3504}
3505static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3506{
3507 return (r >> 2) & 0x1;
3508}
3509static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3510{
3511 return 0x0;
3512}
3513static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3514{
3515 return 0x00504614;
3516}
3517static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3518{
3519 return 0x00504624;
3520}
3521static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3522{
3523 return 0x00504634;
3524}
3525static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void)
3526{
3527 return 0x00000000;
3528}
3529static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void)
3530{
3531 return 0x00000000;
3532}
3533static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3534{
3535 return 0x0050460c;
3536}
3537static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3538{
3539 return (r >> 0) & 0x1;
3540}
3541static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3542{
3543 return (r >> 4) & 0x1;
3544}
3545static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3546{
3547 return 0x00000001;
3548}
3549static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3550{
3551 return 0x00419e50;
3552}
3553static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3554{
3555 return 0x10;
3556}
3557static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3558{
3559 return 0x20;
3560}
3561static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3562{
3563 return 0x40;
3564}
3565static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3566{
3567 return 0x1;
3568}
3569static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
3570{
3571 return 0x2;
3572}
3573static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3574{
3575 return 0x4;
3576}
3577static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3578{
3579 return 0x8;
3580}
3581static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
3582{
3583 return 0x80000000;
3584}
3585static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3586{
3587 return 0x00504650;
3588}
3589static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3590{
3591 return 0x10;
3592}
3593static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void)
3594{
3595 return 0x20000000;
3596}
3597static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void)
3598{
3599 return 0x40000000;
3600}
3601static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3602{
3603 return 0x20;
3604}
3605static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3606{
3607 return 0x40;
3608}
3609static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3610{
3611 return 0x00504224;
3612}
3613static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3614{
3615 return 0x1;
3616}
3617static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void)
3618{
3619 return 0x80;
3620}
3621static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
3622{
3623 return 0x100;
3624}
3625static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3626{
3627 return 0x1;
3628}
3629static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
3630{
3631 return 0x2;
3632}
3633static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3634{
3635 return 0x4;
3636}
3637static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3638{
3639 return 0x8;
3640}
3641static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
3642{
3643 return 0x80000000;
3644}
3645static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3646{
3647 return 0x00504648;
3648}
3649static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3650{
3651 return (r >> 0) & 0xffff;
3652}
3653static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3654{
3655 return 0x00000000;
3656}
3657static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3658{
3659 return 0x0;
3660}
3661static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void)
3662{
3663 return 0x1 << 24;
3664}
3665static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void)
3666{
3667 return 0x7 << 25;
3668}
3669static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void)
3670{
3671 return 0x0;
3672}
3673static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
3674{
3675 return 0x00504654;
3676}
3677static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3678{
3679 return 0x00504770;
3680}
3681static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3682{
3683 return 0x00419f70;
3684}
3685static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3686{
3687 return 0x1 << 4;
3688}
3689static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3690{
3691 return (v & 0x1) << 4;
3692}
3693static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3694{
3695 return 0x0050477c;
3696}
3697static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3698{
3699 return 0x00419f7c;
3700}
3701static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3702{
3703 return 0x1 << 0;
3704}
3705static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3706{
3707 return (v & 0x1) << 0;
3708}
3709static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3710{
3711 return 0x0041be08;
3712}
3713static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3714{
3715 return 0x4;
3716}
3717static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3718{
3719 return 0x0041bf00;
3720}
3721static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3722{
3723 return 0x0041bf04;
3724}
3725static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3726{
3727 return 0x0041bf08;
3728}
3729static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3730{
3731 return 0x0041bf0c;
3732}
3733static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3734{
3735 return 0x0041bf10;
3736}
3737static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3738{
3739 return 0x0041bf14;
3740}
3741static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3742{
3743 return 0x0041bfd0;
3744}
3745static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3746{
3747 return (v & 0xff) << 0;
3748}
3749static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3750{
3751 return (v & 0xff) << 8;
3752}
3753static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3754{
3755 return (v & 0x1f) << 16;
3756}
3757static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3758{
3759 return (v & 0x7) << 21;
3760}
3761static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3762{
3763 return (v & 0x1f) << 24;
3764}
3765static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3766{
3767 return 0x0041bfd4;
3768}
3769static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3770{
3771 return (v & 0xffffff) << 0;
3772}
3773static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3774{
3775 return 0x0041bfe4;
3776}
3777static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3778{
3779 return (v & 0x1f) << 0;
3780}
3781static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3782{
3783 return (v & 0x1f) << 5;
3784}
3785static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3786{
3787 return (v & 0x1f) << 10;
3788}
3789static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3790{
3791 return (v & 0x1f) << 15;
3792}
3793static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3794{
3795 return (v & 0x1f) << 20;
3796}
3797static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3798{
3799 return (v & 0x1f) << 25;
3800}
3801static inline u32 gr_bes_zrop_settings_r(void)
3802{
3803 return 0x00408850;
3804}
3805static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3806{
3807 return (v & 0xf) << 0;
3808}
3809static inline u32 gr_be0_crop_debug3_r(void)
3810{
3811 return 0x00410108;
3812}
3813static inline u32 gr_bes_crop_debug3_r(void)
3814{
3815 return 0x00408908;
3816}
3817static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3818{
3819 return 0x1 << 31;
3820}
3821static inline u32 gr_bes_crop_settings_r(void)
3822{
3823 return 0x00408958;
3824}
3825static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3826{
3827 return (v & 0xf) << 0;
3828}
3829static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3830{
3831 return 0x00000020;
3832}
3833static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3834{
3835 return 0x00000020;
3836}
3837static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3838{
3839 return 0x000000c0;
3840}
3841static inline u32 gr_zcull_subregion_qty_v(void)
3842{
3843 return 0x00000010;
3844}
3845static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3846{
3847 return 0x00504604;
3848}
3849static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3850{
3851 return 0x00504608;
3852}
3853static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3854{
3855 return 0x0050465c;
3856}
3857static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3858{
3859 return 0x00504660;
3860}
3861static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3862{
3863 return 0x00504664;
3864}
3865static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3866{
3867 return 0x00504668;
3868}
3869static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3870{
3871 return 0x0050466c;
3872}
3873static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3874{
3875 return 0x00504658;
3876}
3877static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3878{
3879 return 0x00504730;
3880}
3881static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3882{
3883 return 0x00504734;
3884}
3885static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3886{
3887 return 0x00504738;
3888}
3889static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3890{
3891 return 0x0050473c;
3892}
3893static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3894{
3895 return 0x00504740;
3896}
3897static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3898{
3899 return 0x00504744;
3900}
3901static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3902{
3903 return 0x00504748;
3904}
3905static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3906{
3907 return 0x0050474c;
3908}
3909static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
3910{
3911 return 0x00504678;
3912}
3913static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3914{
3915 return 0x00504694;
3916}
3917static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
3918{
3919 return 0x005046f0;
3920}
3921static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
3922{
3923 return 0x00504700;
3924}
3925static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
3926{
3927 return 0x005046f4;
3928}
3929static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
3930{
3931 return 0x00504704;
3932}
3933static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
3934{
3935 return 0x005046f8;
3936}
3937static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
3938{
3939 return 0x00504708;
3940}
3941static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
3942{
3943 return 0x005046fc;
3944}
3945static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
3946{
3947 return 0x0050470c;
3948}
3949static inline u32 gr_fe_pwr_mode_r(void)
3950{
3951 return 0x00404170;
3952}
3953static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3954{
3955 return 0x0;
3956}
3957static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3958{
3959 return 0x2;
3960}
3961static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3962{
3963 return (r >> 4) & 0x1;
3964}
3965static inline u32 gr_fe_pwr_mode_req_send_f(void)
3966{
3967 return 0x10;
3968}
3969static inline u32 gr_fe_pwr_mode_req_done_v(void)
3970{
3971 return 0x00000000;
3972}
3973static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
3974{
3975 return 0x00418880;
3976}
3977static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
3978{
3979 return 0x1 << 0;
3980}
3981static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
3982{
3983 return 0x1 << 11;
3984}
3985static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
3986{
3987 return 0x1 << 1;
3988}
3989static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
3990{
3991 return 0x1 << 2;
3992}
3993static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
3994{
3995 return 0x3 << 3;
3996}
3997static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
3998{
3999 return 0x3 << 5;
4000}
4001static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
4002{
4003 return 0x3 << 28;
4004}
4005static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
4006{
4007 return 0x1 << 30;
4008}
4009static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
4010{
4011 return 0x1 << 31;
4012}
4013static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
4014{
4015 return 0x00418890;
4016}
4017static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
4018{
4019 return 0x00418894;
4020}
4021static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
4022{
4023 return 0x004188b0;
4024}
4025static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
4026{
4027 return (r >> 16) & 0x1;
4028}
4029static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
4030{
4031 return 0x00000001;
4032}
4033static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
4034{
4035 return 0x004188b4;
4036}
4037static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
4038{
4039 return 0x004188b8;
4040}
4041static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
4042{
4043 return 0x004188ac;
4044}
4045static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
4046{
4047 return 0x00419e10;
4048}
4049static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
4050{
4051 return (v & 0x1) << 0;
4052}
4053static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
4054{
4055 return 0x00000001;
4056}
4057static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
4058{
4059 return 0x1 << 31;
4060}
4061static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
4062{
4063 return (r >> 31) & 0x1;
4064}
4065static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
4066{
4067 return 0x80000000;
4068}
4069static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
4070{
4071 return 0x0;
4072}
4073static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
4074{
4075 return 0x1 << 3;
4076}
4077static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
4078{
4079 return 0x8;
4080}
4081static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
4082{
4083 return 0x0;
4084}
4085static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
4086{
4087 return 0x1 << 30;
4088}
4089static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
4090{
4091 return (r >> 30) & 0x1;
4092}
4093static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
4094{
4095 return 0x40000000;
4096}
4097static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
4098{
4099 return 0x004041c0;
4100}
4101static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
4102{
4103 return (v & 0xffffffff) << 0;
4104}
4105static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
4106{
4107 return 0x0;
4108}
4109static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
4110{
4111 return 0x00419c84;
4112}
4113static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
4114{
4115 return (v & 0x7) << 8;
4116}
4117static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
4118{
4119 return 0x7 << 8;
4120}
4121static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
4122{
4123 return 0x100;
4124}
4125static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
4126{
4127 return 0x00419f78;
4128}
4129static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
4130{
4131 return 0x3 << 11;
4132}
4133static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
4134{
4135 return 0x1000;
4136}
4137static inline u32 gr_gpcs_tc_debug0_r(void)
4138{
4139 return 0x00418708;
4140}
4141static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
4142{
4143 return (v & 0xff) << 0;
4144}
4145static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
4146{
4147 return 0xff << 0;
4148}
4149#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
deleted file mode 100644
index 5916f6952..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
+++ /dev/null
@@ -1,561 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ltc_gp10b_h_
51#define _hw_ltc_gp10b_h_
52
53static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
54{
55 return 0x0014046c;
56}
57static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
58{
59 return 0x00140518;
60}
61static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
62{
63 return 0x0017e318;
64}
65static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
66{
67 return 0x1 << 15;
68}
69static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
70{
71 return 0x00140494;
72}
73static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
74{
75 return (r >> 0) & 0xffff;
76}
77static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
78{
79 return (r >> 16) & 0x3;
80}
81static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
82{
83 return 0x00000000;
84}
85static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
86{
87 return 0x00000001;
88}
89static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
90{
91 return 0x00000002;
92}
93static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
94{
95 return 0x0017e26c;
96}
97static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
98{
99 return 0x1;
100}
101static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
102{
103 return 0x2;
104}
105static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
106{
107 return (r >> 2) & 0x1;
108}
109static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
114{
115 return 0x4;
116}
117static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
118{
119 return 0x0014046c;
120}
121static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
122{
123 return 0x0017e270;
124}
125static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
126{
127 return (v & 0x3ffff) << 0;
128}
129static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
130{
131 return 0x0017e274;
132}
133static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
134{
135 return (v & 0x3ffff) << 0;
136}
137static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
138{
139 return 0x0003ffff;
140}
141static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
142{
143 return 0x0017e278;
144}
145static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
146{
147 return 0x0000000b;
148}
149static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
150{
151 return (r >> 0) & 0x3ffffff;
152}
153static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
154{
155 return 0x0017e27c;
156}
157static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
158{
159 return 0x0017e000;
160}
161static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
162{
163 return 0x0017e280;
164}
165static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
166{
167 return (r >> 0) & 0xffff;
168}
169static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
170{
171 return (r >> 24) & 0xf;
172}
173static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
174{
175 return (r >> 28) & 0xf;
176}
177static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
178{
179 return 0x0017e3f4;
180}
181static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
182{
183 return (r >> 0) & 0xffff;
184}
185static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
186{
187 return 0x0017e2ac;
188}
189static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
190{
191 return (v & 0x1f) << 16;
192}
193static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
194{
195 return 0x0017e338;
196}
197static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
198{
199 return (v & 0xf) << 0;
200}
201static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
202{
203 return 0x0017e33c + i*4;
204}
205static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
206{
207 return 0x00000004;
208}
209static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
210{
211 return 0x0017e34c;
212}
213static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
214{
215 return 32;
216}
217static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
218{
219 return (v & 0xffffffff) << 0;
220}
221static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
222{
223 return 0xffffffff << 0;
224}
225static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
226{
227 return (r >> 0) & 0xffffffff;
228}
229static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
230{
231 return 0x0017e2b0;
232}
233static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
234{
235 return 0x10000000;
236}
237static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
238{
239 return 0x0017e214;
240}
241static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
242{
243 return (r >> 0) & 0x1;
244}
245static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
246{
247 return 0x00000001;
248}
249static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
250{
251 return 0x1;
252}
253static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
254{
255 return 0x00140214;
256}
257static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
258{
259 return (r >> 0) & 0x1;
260}
261static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
262{
263 return 0x00000001;
264}
265static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
266{
267 return 0x1;
268}
269static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
270{
271 return 0x00142214;
272}
273static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
274{
275 return (r >> 0) & 0x1;
276}
277static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
278{
279 return 0x00000001;
280}
281static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
282{
283 return 0x1;
284}
285static inline u32 ltc_ltcs_ltss_intr_r(void)
286{
287 return 0x0017e20c;
288}
289static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
290{
291 return 0x100;
292}
293static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
294{
295 return 0x200;
296}
297static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
298{
299 return 0x1 << 20;
300}
301static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
302{
303 return 0x1 << 30;
304}
305static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
306{
307 return 0x1000000;
308}
309static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
310{
311 return 0x2000000;
312}
313static inline u32 ltc_ltc0_lts0_intr_r(void)
314{
315 return 0x0014040c;
316}
317static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
318{
319 return 0x0014051c;
320}
321static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
322{
323 return 0xff << 0;
324}
325static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
326{
327 return (r >> 0) & 0xff;
328}
329static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
330{
331 return 0xff << 16;
332}
333static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
334{
335 return (r >> 16) & 0xff;
336}
337static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
338{
339 return 0x0017e2a0;
340}
341static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
342{
343 return (r >> 0) & 0x1;
344}
345static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
346{
347 return 0x00000001;
348}
349static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
350{
351 return 0x1;
352}
353static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
354{
355 return (r >> 8) & 0xf;
356}
357static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
358{
359 return 0x00000003;
360}
361static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
362{
363 return 0x300;
364}
365static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
366{
367 return (r >> 28) & 0x1;
368}
369static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
370{
371 return 0x00000001;
372}
373static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
374{
375 return 0x10000000;
376}
377static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
378{
379 return (r >> 29) & 0x1;
380}
381static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
382{
383 return 0x00000001;
384}
385static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
386{
387 return 0x20000000;
388}
389static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
390{
391 return (r >> 30) & 0x1;
392}
393static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
394{
395 return 0x00000001;
396}
397static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
398{
399 return 0x40000000;
400}
401static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
402{
403 return 0x0017e2a4;
404}
405static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
406{
407 return (r >> 0) & 0x1;
408}
409static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
410{
411 return 0x00000001;
412}
413static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
414{
415 return 0x1;
416}
417static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
418{
419 return (r >> 8) & 0xf;
420}
421static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
422{
423 return 0x00000003;
424}
425static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
426{
427 return 0x300;
428}
429static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
430{
431 return (r >> 16) & 0x1;
432}
433static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
434{
435 return 0x00000001;
436}
437static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
438{
439 return 0x10000;
440}
441static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
442{
443 return (r >> 28) & 0x1;
444}
445static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
446{
447 return 0x00000001;
448}
449static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
450{
451 return 0x10000000;
452}
453static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
454{
455 return (r >> 29) & 0x1;
456}
457static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
462{
463 return 0x20000000;
464}
465static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
466{
467 return (r >> 30) & 0x1;
468}
469static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
470{
471 return 0x00000001;
472}
473static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
474{
475 return 0x40000000;
476}
477static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
478{
479 return 0x001402a0;
480}
481static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
482{
483 return (r >> 0) & 0x1;
484}
485static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
486{
487 return 0x00000001;
488}
489static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
490{
491 return 0x1;
492}
493static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
494{
495 return 0x001402a4;
496}
497static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
498{
499 return (r >> 0) & 0x1;
500}
501static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
502{
503 return 0x00000001;
504}
505static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
506{
507 return 0x1;
508}
509static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
510{
511 return 0x001422a0;
512}
513static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
514{
515 return (r >> 0) & 0x1;
516}
517static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
518{
519 return 0x00000001;
520}
521static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
522{
523 return 0x1;
524}
525static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
526{
527 return 0x001422a4;
528}
529static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
530{
531 return (r >> 0) & 0x1;
532}
533static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
534{
535 return 0x00000001;
536}
537static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
538{
539 return 0x1;
540}
541static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
542{
543 return 0x0014058c;
544}
545static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
546{
547 return (r >> 0) & 0xffff;
548}
549static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
550{
551 return (r >> 16) & 0x1f;
552}
553static inline u32 ltc_ltca_g_axi_pctrl_r(void)
554{
555 return 0x00160000;
556}
557static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
558{
559 return (v & 0xff) << 2;
560}
561#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
deleted file mode 100644
index 30165e66d..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h
+++ /dev/null
@@ -1,245 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_mc_gp10b_h_
51#define _hw_mc_gp10b_h_
52
53static inline u32 mc_boot_0_r(void)
54{
55 return 0x00000000;
56}
57static inline u32 mc_boot_0_architecture_v(u32 r)
58{
59 return (r >> 24) & 0x1f;
60}
61static inline u32 mc_boot_0_implementation_v(u32 r)
62{
63 return (r >> 20) & 0xf;
64}
65static inline u32 mc_boot_0_major_revision_v(u32 r)
66{
67 return (r >> 4) & 0xf;
68}
69static inline u32 mc_boot_0_minor_revision_v(u32 r)
70{
71 return (r >> 0) & 0xf;
72}
73static inline u32 mc_intr_r(u32 i)
74{
75 return 0x00000100 + i*4;
76}
77static inline u32 mc_intr_pfifo_pending_f(void)
78{
79 return 0x100;
80}
81static inline u32 mc_intr_replayable_fault_pending_f(void)
82{
83 return 0x200;
84}
85static inline u32 mc_intr_pgraph_pending_f(void)
86{
87 return 0x1000;
88}
89static inline u32 mc_intr_pmu_pending_f(void)
90{
91 return 0x1000000;
92}
93static inline u32 mc_intr_ltc_pending_f(void)
94{
95 return 0x2000000;
96}
97static inline u32 mc_intr_priv_ring_pending_f(void)
98{
99 return 0x40000000;
100}
101static inline u32 mc_intr_pbus_pending_f(void)
102{
103 return 0x10000000;
104}
105static inline u32 mc_intr_en_r(u32 i)
106{
107 return 0x00000140 + i*4;
108}
109static inline u32 mc_intr_en_set_r(u32 i)
110{
111 return 0x00000160 + i*4;
112}
113static inline u32 mc_intr_en_clear_r(u32 i)
114{
115 return 0x00000180 + i*4;
116}
117static inline u32 mc_enable_r(void)
118{
119 return 0x00000200;
120}
121static inline u32 mc_enable_xbar_enabled_f(void)
122{
123 return 0x4;
124}
125static inline u32 mc_enable_l2_enabled_f(void)
126{
127 return 0x8;
128}
129static inline u32 mc_enable_pmedia_s(void)
130{
131 return 1;
132}
133static inline u32 mc_enable_pmedia_f(u32 v)
134{
135 return (v & 0x1) << 4;
136}
137static inline u32 mc_enable_pmedia_m(void)
138{
139 return 0x1 << 4;
140}
141static inline u32 mc_enable_pmedia_v(u32 r)
142{
143 return (r >> 4) & 0x1;
144}
145static inline u32 mc_enable_priv_ring_enabled_f(void)
146{
147 return 0x20;
148}
149static inline u32 mc_enable_ce0_m(void)
150{
151 return 0x1 << 6;
152}
153static inline u32 mc_enable_pfifo_enabled_f(void)
154{
155 return 0x100;
156}
157static inline u32 mc_enable_pgraph_enabled_f(void)
158{
159 return 0x1000;
160}
161static inline u32 mc_enable_pwr_v(u32 r)
162{
163 return (r >> 13) & 0x1;
164}
165static inline u32 mc_enable_pwr_disabled_v(void)
166{
167 return 0x00000000;
168}
169static inline u32 mc_enable_pwr_enabled_f(void)
170{
171 return 0x2000;
172}
173static inline u32 mc_enable_pfb_enabled_f(void)
174{
175 return 0x100000;
176}
177static inline u32 mc_enable_ce2_m(void)
178{
179 return 0x1 << 21;
180}
181static inline u32 mc_enable_ce2_enabled_f(void)
182{
183 return 0x200000;
184}
185static inline u32 mc_enable_blg_enabled_f(void)
186{
187 return 0x8000000;
188}
189static inline u32 mc_enable_perfmon_enabled_f(void)
190{
191 return 0x10000000;
192}
193static inline u32 mc_enable_hub_enabled_f(void)
194{
195 return 0x20000000;
196}
197static inline u32 mc_intr_ltc_r(void)
198{
199 return 0x000001c0;
200}
201static inline u32 mc_enable_pb_r(void)
202{
203 return 0x00000204;
204}
205static inline u32 mc_enable_pb_0_s(void)
206{
207 return 1;
208}
209static inline u32 mc_enable_pb_0_f(u32 v)
210{
211 return (v & 0x1) << 0;
212}
213static inline u32 mc_enable_pb_0_m(void)
214{
215 return 0x1 << 0;
216}
217static inline u32 mc_enable_pb_0_v(u32 r)
218{
219 return (r >> 0) & 0x1;
220}
221static inline u32 mc_enable_pb_0_enabled_v(void)
222{
223 return 0x00000001;
224}
225static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
226{
227 return (v & 0x1) << (0 + i*1);
228}
229static inline u32 mc_elpg_enable_r(void)
230{
231 return 0x0000020c;
232}
233static inline u32 mc_elpg_enable_xbar_enabled_f(void)
234{
235 return 0x4;
236}
237static inline u32 mc_elpg_enable_pfb_enabled_f(void)
238{
239 return 0x100000;
240}
241static inline u32 mc_elpg_enable_hub_enabled_f(void)
242{
243 return 0x20000000;
244}
245#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h
deleted file mode 100644
index f66fa9345..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h
+++ /dev/null
@@ -1,577 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pbdma_gp10b_h_
51#define _hw_pbdma_gp10b_h_
52
53static inline u32 pbdma_gp_entry1_r(void)
54{
55 return 0x10000004;
56}
57static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
58{
59 return (r >> 0) & 0xff;
60}
61static inline u32 pbdma_gp_entry1_length_f(u32 v)
62{
63 return (v & 0x1fffff) << 10;
64}
65static inline u32 pbdma_gp_entry1_length_v(u32 r)
66{
67 return (r >> 10) & 0x1fffff;
68}
69static inline u32 pbdma_gp_base_r(u32 i)
70{
71 return 0x00040048 + i*8192;
72}
73static inline u32 pbdma_gp_base__size_1_v(void)
74{
75 return 0x00000001;
76}
77static inline u32 pbdma_gp_base_offset_f(u32 v)
78{
79 return (v & 0x1fffffff) << 3;
80}
81static inline u32 pbdma_gp_base_rsvd_s(void)
82{
83 return 3;
84}
85static inline u32 pbdma_gp_base_hi_r(u32 i)
86{
87 return 0x0004004c + i*8192;
88}
89static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
90{
91 return (v & 0xff) << 0;
92}
93static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
94{
95 return (v & 0x1f) << 16;
96}
97static inline u32 pbdma_gp_fetch_r(u32 i)
98{
99 return 0x00040050 + i*8192;
100}
101static inline u32 pbdma_gp_get_r(u32 i)
102{
103 return 0x00040014 + i*8192;
104}
105static inline u32 pbdma_gp_put_r(u32 i)
106{
107 return 0x00040000 + i*8192;
108}
109static inline u32 pbdma_pb_fetch_r(u32 i)
110{
111 return 0x00040054 + i*8192;
112}
113static inline u32 pbdma_pb_fetch_hi_r(u32 i)
114{
115 return 0x00040058 + i*8192;
116}
117static inline u32 pbdma_get_r(u32 i)
118{
119 return 0x00040018 + i*8192;
120}
121static inline u32 pbdma_get_hi_r(u32 i)
122{
123 return 0x0004001c + i*8192;
124}
125static inline u32 pbdma_put_r(u32 i)
126{
127 return 0x0004005c + i*8192;
128}
129static inline u32 pbdma_put_hi_r(u32 i)
130{
131 return 0x00040060 + i*8192;
132}
133static inline u32 pbdma_formats_r(u32 i)
134{
135 return 0x0004009c + i*8192;
136}
137static inline u32 pbdma_formats_gp_fermi0_f(void)
138{
139 return 0x0;
140}
141static inline u32 pbdma_formats_pb_fermi1_f(void)
142{
143 return 0x100;
144}
145static inline u32 pbdma_formats_mp_fermi0_f(void)
146{
147 return 0x0;
148}
149static inline u32 pbdma_pb_header_r(u32 i)
150{
151 return 0x00040084 + i*8192;
152}
153static inline u32 pbdma_pb_header_priv_user_f(void)
154{
155 return 0x0;
156}
157static inline u32 pbdma_pb_header_method_zero_f(void)
158{
159 return 0x0;
160}
161static inline u32 pbdma_pb_header_subchannel_zero_f(void)
162{
163 return 0x0;
164}
165static inline u32 pbdma_pb_header_level_main_f(void)
166{
167 return 0x0;
168}
169static inline u32 pbdma_pb_header_first_true_f(void)
170{
171 return 0x400000;
172}
173static inline u32 pbdma_pb_header_type_inc_f(void)
174{
175 return 0x20000000;
176}
177static inline u32 pbdma_pb_header_type_non_inc_f(void)
178{
179 return 0x60000000;
180}
181static inline u32 pbdma_hdr_shadow_r(u32 i)
182{
183 return 0x00040118 + i*8192;
184}
185static inline u32 pbdma_subdevice_r(u32 i)
186{
187 return 0x00040094 + i*8192;
188}
189static inline u32 pbdma_subdevice_id_f(u32 v)
190{
191 return (v & 0xfff) << 0;
192}
193static inline u32 pbdma_subdevice_status_active_f(void)
194{
195 return 0x10000000;
196}
197static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
198{
199 return 0x20000000;
200}
201static inline u32 pbdma_method0_r(u32 i)
202{
203 return 0x000400c0 + i*8192;
204}
205static inline u32 pbdma_method0_fifo_size_v(void)
206{
207 return 0x00000004;
208}
209static inline u32 pbdma_method0_addr_f(u32 v)
210{
211 return (v & 0xfff) << 2;
212}
213static inline u32 pbdma_method0_addr_v(u32 r)
214{
215 return (r >> 2) & 0xfff;
216}
217static inline u32 pbdma_method0_subch_v(u32 r)
218{
219 return (r >> 16) & 0x7;
220}
221static inline u32 pbdma_method0_first_true_f(void)
222{
223 return 0x400000;
224}
225static inline u32 pbdma_method0_valid_true_f(void)
226{
227 return 0x80000000;
228}
229static inline u32 pbdma_method1_r(u32 i)
230{
231 return 0x000400c8 + i*8192;
232}
233static inline u32 pbdma_method2_r(u32 i)
234{
235 return 0x000400d0 + i*8192;
236}
237static inline u32 pbdma_method3_r(u32 i)
238{
239 return 0x000400d8 + i*8192;
240}
241static inline u32 pbdma_data0_r(u32 i)
242{
243 return 0x000400c4 + i*8192;
244}
245static inline u32 pbdma_target_r(u32 i)
246{
247 return 0x000400ac + i*8192;
248}
249static inline u32 pbdma_target_engine_sw_f(void)
250{
251 return 0x1f;
252}
253static inline u32 pbdma_acquire_r(u32 i)
254{
255 return 0x00040030 + i*8192;
256}
257static inline u32 pbdma_acquire_retry_man_2_f(void)
258{
259 return 0x2;
260}
261static inline u32 pbdma_acquire_retry_exp_2_f(void)
262{
263 return 0x100;
264}
265static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
266{
267 return (v & 0xf) << 11;
268}
269static inline u32 pbdma_acquire_timeout_exp_max_v(void)
270{
271 return 0x0000000f;
272}
273static inline u32 pbdma_acquire_timeout_exp_max_f(void)
274{
275 return 0x7800;
276}
277static inline u32 pbdma_acquire_timeout_man_f(u32 v)
278{
279 return (v & 0xffff) << 15;
280}
281static inline u32 pbdma_acquire_timeout_man_max_v(void)
282{
283 return 0x0000ffff;
284}
285static inline u32 pbdma_acquire_timeout_man_max_f(void)
286{
287 return 0x7fff8000;
288}
289static inline u32 pbdma_acquire_timeout_en_enable_f(void)
290{
291 return 0x80000000;
292}
293static inline u32 pbdma_acquire_timeout_en_disable_f(void)
294{
295 return 0x0;
296}
297static inline u32 pbdma_status_r(u32 i)
298{
299 return 0x00040100 + i*8192;
300}
301static inline u32 pbdma_channel_r(u32 i)
302{
303 return 0x00040120 + i*8192;
304}
305static inline u32 pbdma_signature_r(u32 i)
306{
307 return 0x00040010 + i*8192;
308}
309static inline u32 pbdma_signature_hw_valid_f(void)
310{
311 return 0xface;
312}
313static inline u32 pbdma_signature_sw_zero_f(void)
314{
315 return 0x0;
316}
317static inline u32 pbdma_userd_r(u32 i)
318{
319 return 0x00040008 + i*8192;
320}
321static inline u32 pbdma_userd_target_vid_mem_f(void)
322{
323 return 0x0;
324}
325static inline u32 pbdma_userd_addr_f(u32 v)
326{
327 return (v & 0x7fffff) << 9;
328}
329static inline u32 pbdma_userd_hi_r(u32 i)
330{
331 return 0x0004000c + i*8192;
332}
333static inline u32 pbdma_userd_hi_addr_f(u32 v)
334{
335 return (v & 0xff) << 0;
336}
337static inline u32 pbdma_hce_ctrl_r(u32 i)
338{
339 return 0x000400e4 + i*8192;
340}
341static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
342{
343 return 0x20;
344}
345static inline u32 pbdma_intr_0_r(u32 i)
346{
347 return 0x00040108 + i*8192;
348}
349static inline u32 pbdma_intr_0_memreq_v(u32 r)
350{
351 return (r >> 0) & 0x1;
352}
353static inline u32 pbdma_intr_0_memreq_pending_f(void)
354{
355 return 0x1;
356}
357static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
358{
359 return 0x2;
360}
361static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
362{
363 return 0x4;
364}
365static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
366{
367 return 0x8;
368}
369static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
370{
371 return 0x10;
372}
373static inline u32 pbdma_intr_0_memflush_pending_f(void)
374{
375 return 0x20;
376}
377static inline u32 pbdma_intr_0_memop_pending_f(void)
378{
379 return 0x40;
380}
381static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
382{
383 return 0x80;
384}
385static inline u32 pbdma_intr_0_lbreq_pending_f(void)
386{
387 return 0x100;
388}
389static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
390{
391 return 0x200;
392}
393static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
394{
395 return 0x400;
396}
397static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
398{
399 return 0x800;
400}
401static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
402{
403 return 0x1000;
404}
405static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
406{
407 return 0x2000;
408}
409static inline u32 pbdma_intr_0_gpptr_pending_f(void)
410{
411 return 0x4000;
412}
413static inline u32 pbdma_intr_0_gpentry_pending_f(void)
414{
415 return 0x8000;
416}
417static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
418{
419 return 0x10000;
420}
421static inline u32 pbdma_intr_0_pbptr_pending_f(void)
422{
423 return 0x20000;
424}
425static inline u32 pbdma_intr_0_pbentry_pending_f(void)
426{
427 return 0x40000;
428}
429static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
430{
431 return 0x80000;
432}
433static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
434{
435 return 0x100000;
436}
437static inline u32 pbdma_intr_0_method_pending_f(void)
438{
439 return 0x200000;
440}
441static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
442{
443 return 0x400000;
444}
445static inline u32 pbdma_intr_0_device_pending_f(void)
446{
447 return 0x800000;
448}
449static inline u32 pbdma_intr_0_semaphore_pending_f(void)
450{
451 return 0x2000000;
452}
453static inline u32 pbdma_intr_0_acquire_pending_f(void)
454{
455 return 0x4000000;
456}
457static inline u32 pbdma_intr_0_pri_pending_f(void)
458{
459 return 0x8000000;
460}
461static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
462{
463 return 0x20000000;
464}
465static inline u32 pbdma_intr_0_pbseg_pending_f(void)
466{
467 return 0x40000000;
468}
469static inline u32 pbdma_intr_0_signature_pending_f(void)
470{
471 return 0x80000000;
472}
473static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
474{
475 return 0x10000000;
476}
477static inline u32 pbdma_intr_1_r(u32 i)
478{
479 return 0x00040148 + i*8192;
480}
481static inline u32 pbdma_intr_en_0_r(u32 i)
482{
483 return 0x0004010c + i*8192;
484}
485static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
486{
487 return 0x100;
488}
489static inline u32 pbdma_intr_en_1_r(u32 i)
490{
491 return 0x0004014c + i*8192;
492}
493static inline u32 pbdma_intr_stall_r(u32 i)
494{
495 return 0x0004013c + i*8192;
496}
497static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
498{
499 return 0x100;
500}
501static inline u32 pbdma_udma_nop_r(void)
502{
503 return 0x00000008;
504}
505static inline u32 pbdma_allowed_syncpoints_r(u32 i)
506{
507 return 0x000400e8 + i*8192;
508}
509static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v)
510{
511 return (v & 0x1) << 31;
512}
513static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v)
514{
515 return (v & 0x7fff) << 16;
516}
517static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r)
518{
519 return (r >> 16) & 0x7fff;
520}
521static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v)
522{
523 return (v & 0x1) << 15;
524}
525static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
526{
527 return (v & 0x7fff) << 0;
528}
529static inline u32 pbdma_syncpointa_r(u32 i)
530{
531 return 0x000400a4 + i*8192;
532}
533static inline u32 pbdma_syncpointa_payload_v(u32 r)
534{
535 return (r >> 0) & 0xffffffff;
536}
537static inline u32 pbdma_syncpointb_r(u32 i)
538{
539 return 0x000400a8 + i*8192;
540}
541static inline u32 pbdma_syncpointb_op_v(u32 r)
542{
543 return (r >> 0) & 0x1;
544}
545static inline u32 pbdma_syncpointb_op_wait_v(void)
546{
547 return 0x00000000;
548}
549static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
550{
551 return (r >> 4) & 0x1;
552}
553static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
554{
555 return 0x00000001;
556}
557static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
558{
559 return (r >> 8) & 0xfff;
560}
561static inline u32 pbdma_runlist_timeslice_r(u32 i)
562{
563 return 0x000400f8 + i*8192;
564}
565static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
566{
567 return 0x80;
568}
569static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
570{
571 return 0x3000;
572}
573static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
574{
575 return 0x10000000;
576}
577#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h
deleted file mode 100644
index ea1a61d27..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_perf_gp10b_h_
51#define _hw_perf_gp10b_h_
52
53static inline u32 perf_pmasys_control_r(void)
54{
55 return 0x001b4000;
56}
57static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
58{
59 return (r >> 4) & 0x1;
60}
61static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
62{
63 return 0x00000001;
64}
65static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
66{
67 return 0x10;
68}
69static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
70{
71 return (v & 0x1) << 5;
72}
73static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
74{
75 return (r >> 5) & 0x1;
76}
77static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
82{
83 return 0x20;
84}
85static inline u32 perf_pmasys_mem_block_r(void)
86{
87 return 0x001b4070;
88}
89static inline u32 perf_pmasys_mem_block_base_f(u32 v)
90{
91 return (v & 0xfffffff) << 0;
92}
93static inline u32 perf_pmasys_mem_block_target_f(u32 v)
94{
95 return (v & 0x3) << 28;
96}
97static inline u32 perf_pmasys_mem_block_target_v(u32 r)
98{
99 return (r >> 28) & 0x3;
100}
101static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
102{
103 return 0x00000000;
104}
105static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
106{
107 return 0x0;
108}
109static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
114{
115 return 0x20000000;
116}
117static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
118{
119 return 0x00000003;
120}
121static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
122{
123 return 0x30000000;
124}
125static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
126{
127 return (v & 0x1) << 31;
128}
129static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
130{
131 return (r >> 31) & 0x1;
132}
133static inline u32 perf_pmasys_mem_block_valid_true_v(void)
134{
135 return 0x00000001;
136}
137static inline u32 perf_pmasys_mem_block_valid_true_f(void)
138{
139 return 0x80000000;
140}
141static inline u32 perf_pmasys_mem_block_valid_false_v(void)
142{
143 return 0x00000000;
144}
145static inline u32 perf_pmasys_mem_block_valid_false_f(void)
146{
147 return 0x0;
148}
149static inline u32 perf_pmasys_outbase_r(void)
150{
151 return 0x001b4074;
152}
153static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
154{
155 return (v & 0x7ffffff) << 5;
156}
157static inline u32 perf_pmasys_outbaseupper_r(void)
158{
159 return 0x001b4078;
160}
161static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
162{
163 return (v & 0xff) << 0;
164}
165static inline u32 perf_pmasys_outsize_r(void)
166{
167 return 0x001b407c;
168}
169static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
170{
171 return (v & 0x7ffffff) << 5;
172}
173static inline u32 perf_pmasys_mem_bytes_r(void)
174{
175 return 0x001b4084;
176}
177static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
178{
179 return (v & 0xfffffff) << 4;
180}
181static inline u32 perf_pmasys_mem_bump_r(void)
182{
183 return 0x001b4088;
184}
185static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
186{
187 return (v & 0xfffffff) << 4;
188}
189static inline u32 perf_pmasys_enginestatus_r(void)
190{
191 return 0x001b40a4;
192}
193static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
194{
195 return (v & 0x1) << 4;
196}
197static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
198{
199 return 0x00000001;
200}
201static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
202{
203 return 0x10;
204}
205#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h
deleted file mode 100644
index 7a4588585..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h
+++ /dev/null
@@ -1,145 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringmaster_gp10b_h_
51#define _hw_pri_ringmaster_gp10b_h_
52
53static inline u32 pri_ringmaster_command_r(void)
54{
55 return 0x0012004c;
56}
57static inline u32 pri_ringmaster_command_cmd_m(void)
58{
59 return 0x3f << 0;
60}
61static inline u32 pri_ringmaster_command_cmd_v(u32 r)
62{
63 return (r >> 0) & 0x3f;
64}
65static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
66{
67 return 0x00000000;
68}
69static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
70{
71 return 0x1;
72}
73static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
74{
75 return 0x2;
76}
77static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
78{
79 return 0x3;
80}
81static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
82{
83 return 0x0;
84}
85static inline u32 pri_ringmaster_command_data_r(void)
86{
87 return 0x00120048;
88}
89static inline u32 pri_ringmaster_start_results_r(void)
90{
91 return 0x00120050;
92}
93static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
94{
95 return (r >> 0) & 0x1;
96}
97static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
98{
99 return 0x00000001;
100}
101static inline u32 pri_ringmaster_intr_status0_r(void)
102{
103 return 0x00120058;
104}
105static inline u32 pri_ringmaster_intr_status1_r(void)
106{
107 return 0x0012005c;
108}
109static inline u32 pri_ringmaster_global_ctl_r(void)
110{
111 return 0x00120060;
112}
113static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
114{
115 return 0x1;
116}
117static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
118{
119 return 0x0;
120}
121static inline u32 pri_ringmaster_enum_fbp_r(void)
122{
123 return 0x00120074;
124}
125static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
126{
127 return (r >> 0) & 0x1f;
128}
129static inline u32 pri_ringmaster_enum_gpc_r(void)
130{
131 return 0x00120078;
132}
133static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
134{
135 return (r >> 0) & 0x1f;
136}
137static inline u32 pri_ringmaster_enum_ltc_r(void)
138{
139 return 0x0012006c;
140}
141static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
142{
143 return (r >> 0) & 0x1f;
144}
145#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h
deleted file mode 100644
index eb711452f..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_sys_gp10b_h_
51#define _hw_pri_ringstation_sys_gp10b_h_
52
53static inline u32 pri_ringstation_sys_master_config_r(u32 i)
54{
55 return 0x00122300 + i*4;
56}
57static inline u32 pri_ringstation_sys_decode_config_r(void)
58{
59 return 0x00122204;
60}
61static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
62{
63 return 0x7 << 0;
64}
65static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
66{
67 return 0x1;
68}
69#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
deleted file mode 100644
index a315ae2d6..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_proj_gp10b_h_
51#define _hw_proj_gp10b_h_
52
53static inline u32 proj_gpc_base_v(void)
54{
55 return 0x00500000;
56}
57static inline u32 proj_gpc_shared_base_v(void)
58{
59 return 0x00418000;
60}
61static inline u32 proj_gpc_stride_v(void)
62{
63 return 0x00008000;
64}
65static inline u32 proj_ltc_stride_v(void)
66{
67 return 0x00002000;
68}
69static inline u32 proj_lts_stride_v(void)
70{
71 return 0x00000200;
72}
73static inline u32 proj_ppc_in_gpc_base_v(void)
74{
75 return 0x00003000;
76}
77static inline u32 proj_ppc_in_gpc_stride_v(void)
78{
79 return 0x00000200;
80}
81static inline u32 proj_rop_base_v(void)
82{
83 return 0x00410000;
84}
85static inline u32 proj_rop_shared_base_v(void)
86{
87 return 0x00408800;
88}
89static inline u32 proj_rop_stride_v(void)
90{
91 return 0x00000400;
92}
93static inline u32 proj_tpc_in_gpc_base_v(void)
94{
95 return 0x00004000;
96}
97static inline u32 proj_tpc_in_gpc_stride_v(void)
98{
99 return 0x00000800;
100}
101static inline u32 proj_tpc_in_gpc_shared_base_v(void)
102{
103 return 0x00001800;
104}
105static inline u32 proj_host_num_pbdma_v(void)
106{
107 return 0x00000001;
108}
109static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 proj_scal_litter_num_fbps_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 proj_scal_litter_num_gpcs_v(void)
118{
119 return 0x00000001;
120}
121static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
122{
123 return 0x00000001;
124}
125static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
126{
127 return 0x00000002;
128}
129static inline u32 proj_scal_litter_num_zcull_banks_v(void)
130{
131 return 0x00000004;
132}
133static inline u32 proj_scal_max_gpcs_v(void)
134{
135 return 0x00000020;
136}
137static inline u32 proj_scal_max_tpc_per_gpc_v(void)
138{
139 return 0x00000008;
140}
141#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h
deleted file mode 100644
index 75bf59a30..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h
+++ /dev/null
@@ -1,821 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pwr_gp10b_h_
51#define _hw_pwr_gp10b_h_
52
53static inline u32 pwr_falcon_irqsset_r(void)
54{
55 return 0x0010a000;
56}
57static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
58{
59 return 0x40;
60}
61static inline u32 pwr_falcon_irqsclr_r(void)
62{
63 return 0x0010a004;
64}
65static inline u32 pwr_falcon_irqstat_r(void)
66{
67 return 0x0010a008;
68}
69static inline u32 pwr_falcon_irqstat_halt_true_f(void)
70{
71 return 0x10;
72}
73static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
74{
75 return 0x20;
76}
77static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
78{
79 return 0x40;
80}
81static inline u32 pwr_falcon_irqmode_r(void)
82{
83 return 0x0010a00c;
84}
85static inline u32 pwr_falcon_irqmset_r(void)
86{
87 return 0x0010a010;
88}
89static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
90{
91 return (v & 0x1) << 0;
92}
93static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
94{
95 return (v & 0x1) << 1;
96}
97static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
98{
99 return (v & 0x1) << 2;
100}
101static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
102{
103 return (v & 0x1) << 3;
104}
105static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
106{
107 return (v & 0x1) << 4;
108}
109static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
110{
111 return (v & 0x1) << 5;
112}
113static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
114{
115 return (v & 0x1) << 6;
116}
117static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
118{
119 return (v & 0x1) << 7;
120}
121static inline u32 pwr_falcon_irqmclr_r(void)
122{
123 return 0x0010a014;
124}
125static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
126{
127 return (v & 0x1) << 0;
128}
129static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
130{
131 return (v & 0x1) << 1;
132}
133static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
138{
139 return (v & 0x1) << 3;
140}
141static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
142{
143 return (v & 0x1) << 4;
144}
145static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
146{
147 return (v & 0x1) << 5;
148}
149static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
150{
151 return (v & 0x1) << 6;
152}
153static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
154{
155 return (v & 0x1) << 7;
156}
157static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
158{
159 return (v & 0xff) << 8;
160}
161static inline u32 pwr_falcon_irqmask_r(void)
162{
163 return 0x0010a018;
164}
165static inline u32 pwr_falcon_irqdest_r(void)
166{
167 return 0x0010a01c;
168}
169static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
170{
171 return (v & 0x1) << 0;
172}
173static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
174{
175 return (v & 0x1) << 1;
176}
177static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
178{
179 return (v & 0x1) << 2;
180}
181static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
182{
183 return (v & 0x1) << 3;
184}
185static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
186{
187 return (v & 0x1) << 4;
188}
189static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
190{
191 return (v & 0x1) << 5;
192}
193static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
198{
199 return (v & 0x1) << 7;
200}
201static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
202{
203 return (v & 0xff) << 8;
204}
205static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
206{
207 return (v & 0x1) << 16;
208}
209static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
210{
211 return (v & 0x1) << 17;
212}
213static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
214{
215 return (v & 0x1) << 18;
216}
217static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
218{
219 return (v & 0x1) << 19;
220}
221static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
222{
223 return (v & 0x1) << 20;
224}
225static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
226{
227 return (v & 0x1) << 21;
228}
229static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
230{
231 return (v & 0x1) << 22;
232}
233static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
234{
235 return (v & 0x1) << 23;
236}
237static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
238{
239 return (v & 0xff) << 24;
240}
241static inline u32 pwr_falcon_curctx_r(void)
242{
243 return 0x0010a050;
244}
245static inline u32 pwr_falcon_nxtctx_r(void)
246{
247 return 0x0010a054;
248}
249static inline u32 pwr_falcon_mailbox0_r(void)
250{
251 return 0x0010a040;
252}
253static inline u32 pwr_falcon_mailbox1_r(void)
254{
255 return 0x0010a044;
256}
257static inline u32 pwr_falcon_itfen_r(void)
258{
259 return 0x0010a048;
260}
261static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
262{
263 return 0x1;
264}
265static inline u32 pwr_falcon_idlestate_r(void)
266{
267 return 0x0010a04c;
268}
269static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
270{
271 return (r >> 0) & 0x1;
272}
273static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
274{
275 return (r >> 1) & 0x7fff;
276}
277static inline u32 pwr_falcon_os_r(void)
278{
279 return 0x0010a080;
280}
281static inline u32 pwr_falcon_engctl_r(void)
282{
283 return 0x0010a0a4;
284}
285static inline u32 pwr_falcon_cpuctl_r(void)
286{
287 return 0x0010a100;
288}
289static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
290{
291 return (v & 0x1) << 1;
292}
293static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
294{
295 return (v & 0x1) << 4;
296}
297static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
298{
299 return 0x1 << 4;
300}
301static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
302{
303 return (r >> 4) & 0x1;
304}
305static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
306{
307 return (v & 0x1) << 6;
308}
309static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
310{
311 return 0x1 << 6;
312}
313static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
314{
315 return (r >> 6) & 0x1;
316}
317static inline u32 pwr_falcon_cpuctl_alias_r(void)
318{
319 return 0x0010a130;
320}
321static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
322{
323 return (v & 0x1) << 1;
324}
325static inline u32 pwr_pmu_scpctl_stat_r(void)
326{
327 return 0x0010ac08;
328}
329static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
330{
331 return (v & 0x1) << 20;
332}
333static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
334{
335 return 0x1 << 20;
336}
337static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
338{
339 return (r >> 20) & 0x1;
340}
341static inline u32 pwr_falcon_imemc_r(u32 i)
342{
343 return 0x0010a180 + i*16;
344}
345static inline u32 pwr_falcon_imemc_offs_f(u32 v)
346{
347 return (v & 0x3f) << 2;
348}
349static inline u32 pwr_falcon_imemc_blk_f(u32 v)
350{
351 return (v & 0xff) << 8;
352}
353static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
354{
355 return (v & 0x1) << 24;
356}
357static inline u32 pwr_falcon_imemd_r(u32 i)
358{
359 return 0x0010a184 + i*16;
360}
361static inline u32 pwr_falcon_imemt_r(u32 i)
362{
363 return 0x0010a188 + i*16;
364}
365static inline u32 pwr_falcon_sctl_r(void)
366{
367 return 0x0010a240;
368}
369static inline u32 pwr_falcon_mmu_phys_sec_r(void)
370{
371 return 0x00100ce4;
372}
373static inline u32 pwr_falcon_bootvec_r(void)
374{
375 return 0x0010a104;
376}
377static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
378{
379 return (v & 0xffffffff) << 0;
380}
381static inline u32 pwr_falcon_dmactl_r(void)
382{
383 return 0x0010a10c;
384}
385static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
386{
387 return 0x1 << 1;
388}
389static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
390{
391 return 0x1 << 2;
392}
393static inline u32 pwr_falcon_hwcfg_r(void)
394{
395 return 0x0010a108;
396}
397static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
398{
399 return (r >> 0) & 0x1ff;
400}
401static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
402{
403 return (r >> 9) & 0x1ff;
404}
405static inline u32 pwr_falcon_dmatrfbase_r(void)
406{
407 return 0x0010a110;
408}
409static inline u32 pwr_falcon_dmatrfbase1_r(void)
410{
411 return 0x0010a128;
412}
413static inline u32 pwr_falcon_dmatrfmoffs_r(void)
414{
415 return 0x0010a114;
416}
417static inline u32 pwr_falcon_dmatrfcmd_r(void)
418{
419 return 0x0010a118;
420}
421static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
422{
423 return (v & 0x1) << 4;
424}
425static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
426{
427 return (v & 0x1) << 5;
428}
429static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
430{
431 return (v & 0x7) << 8;
432}
433static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
434{
435 return (v & 0x7) << 12;
436}
437static inline u32 pwr_falcon_dmatrffboffs_r(void)
438{
439 return 0x0010a11c;
440}
441static inline u32 pwr_falcon_exterraddr_r(void)
442{
443 return 0x0010a168;
444}
445static inline u32 pwr_falcon_exterrstat_r(void)
446{
447 return 0x0010a16c;
448}
449static inline u32 pwr_falcon_exterrstat_valid_m(void)
450{
451 return 0x1 << 31;
452}
453static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
454{
455 return (r >> 31) & 0x1;
456}
457static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
462{
463 return 0x0010a200;
464}
465static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
466{
467 return 4;
468}
469static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
470{
471 return (v & 0xf) << 0;
472}
473static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
474{
475 return 0xf << 0;
476}
477static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
478{
479 return (r >> 0) & 0xf;
480}
481static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
482{
483 return 0x8;
484}
485static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
486{
487 return 0xe;
488}
489static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
490{
491 return (v & 0x1f) << 8;
492}
493static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
494{
495 return 0x0010a20c;
496}
497static inline u32 pwr_falcon_dmemc_r(u32 i)
498{
499 return 0x0010a1c0 + i*8;
500}
501static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
502{
503 return (v & 0x3f) << 2;
504}
505static inline u32 pwr_falcon_dmemc_offs_m(void)
506{
507 return 0x3f << 2;
508}
509static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
510{
511 return (v & 0xff) << 8;
512}
513static inline u32 pwr_falcon_dmemc_blk_m(void)
514{
515 return 0xff << 8;
516}
517static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
518{
519 return (v & 0x1) << 24;
520}
521static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
522{
523 return (v & 0x1) << 25;
524}
525static inline u32 pwr_falcon_dmemd_r(u32 i)
526{
527 return 0x0010a1c4 + i*8;
528}
529static inline u32 pwr_pmu_new_instblk_r(void)
530{
531 return 0x0010a480;
532}
533static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
534{
535 return (v & 0xfffffff) << 0;
536}
537static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
538{
539 return 0x0;
540}
541static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
542{
543 return 0x20000000;
544}
545static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
546{
547 return (v & 0x1) << 30;
548}
549static inline u32 pwr_pmu_mutex_id_r(void)
550{
551 return 0x0010a488;
552}
553static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
554{
555 return (r >> 0) & 0xff;
556}
557static inline u32 pwr_pmu_mutex_id_value_init_v(void)
558{
559 return 0x00000000;
560}
561static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
562{
563 return 0x000000ff;
564}
565static inline u32 pwr_pmu_mutex_id_release_r(void)
566{
567 return 0x0010a48c;
568}
569static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
570{
571 return (v & 0xff) << 0;
572}
573static inline u32 pwr_pmu_mutex_id_release_value_m(void)
574{
575 return 0xff << 0;
576}
577static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
578{
579 return 0x00000000;
580}
581static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
582{
583 return 0x0;
584}
585static inline u32 pwr_pmu_mutex_r(u32 i)
586{
587 return 0x0010a580 + i*4;
588}
589static inline u32 pwr_pmu_mutex__size_1_v(void)
590{
591 return 0x00000010;
592}
593static inline u32 pwr_pmu_mutex_value_f(u32 v)
594{
595 return (v & 0xff) << 0;
596}
597static inline u32 pwr_pmu_mutex_value_v(u32 r)
598{
599 return (r >> 0) & 0xff;
600}
601static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
602{
603 return 0x0;
604}
605static inline u32 pwr_pmu_queue_head_r(u32 i)
606{
607 return 0x0010a4a0 + i*4;
608}
609static inline u32 pwr_pmu_queue_head__size_1_v(void)
610{
611 return 0x00000004;
612}
613static inline u32 pwr_pmu_queue_head_address_f(u32 v)
614{
615 return (v & 0xffffffff) << 0;
616}
617static inline u32 pwr_pmu_queue_head_address_v(u32 r)
618{
619 return (r >> 0) & 0xffffffff;
620}
621static inline u32 pwr_pmu_queue_tail_r(u32 i)
622{
623 return 0x0010a4b0 + i*4;
624}
625static inline u32 pwr_pmu_queue_tail__size_1_v(void)
626{
627 return 0x00000004;
628}
629static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
630{
631 return (v & 0xffffffff) << 0;
632}
633static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
634{
635 return (r >> 0) & 0xffffffff;
636}
637static inline u32 pwr_pmu_msgq_head_r(void)
638{
639 return 0x0010a4c8;
640}
641static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
642{
643 return (v & 0xffffffff) << 0;
644}
645static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
646{
647 return (r >> 0) & 0xffffffff;
648}
649static inline u32 pwr_pmu_msgq_tail_r(void)
650{
651 return 0x0010a4cc;
652}
653static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
654{
655 return (v & 0xffffffff) << 0;
656}
657static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
658{
659 return (r >> 0) & 0xffffffff;
660}
661static inline u32 pwr_pmu_idle_mask_r(u32 i)
662{
663 return 0x0010a504 + i*16;
664}
665static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
666{
667 return 0x1;
668}
669static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
670{
671 return 0x200000;
672}
673static inline u32 pwr_pmu_idle_count_r(u32 i)
674{
675 return 0x0010a508 + i*16;
676}
677static inline u32 pwr_pmu_idle_count_value_f(u32 v)
678{
679 return (v & 0x7fffffff) << 0;
680}
681static inline u32 pwr_pmu_idle_count_value_v(u32 r)
682{
683 return (r >> 0) & 0x7fffffff;
684}
685static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
686{
687 return (v & 0x1) << 31;
688}
689static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
690{
691 return 0x0010a50c + i*16;
692}
693static inline u32 pwr_pmu_idle_ctrl_value_m(void)
694{
695 return 0x3 << 0;
696}
697static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
698{
699 return 0x2;
700}
701static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
702{
703 return 0x3;
704}
705static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
706{
707 return 0x1 << 2;
708}
709static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
710{
711 return 0x0;
712}
713static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
714{
715 return 0x0010a9f0 + i*8;
716}
717static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
718{
719 return 0x0010a9f4 + i*8;
720}
721static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
722{
723 return 0x0010aa30 + i*8;
724}
725static inline u32 pwr_pmu_debug_r(u32 i)
726{
727 return 0x0010a5c0 + i*4;
728}
729static inline u32 pwr_pmu_debug__size_1_v(void)
730{
731 return 0x00000004;
732}
733static inline u32 pwr_pmu_mailbox_r(u32 i)
734{
735 return 0x0010a450 + i*4;
736}
737static inline u32 pwr_pmu_mailbox__size_1_v(void)
738{
739 return 0x0000000c;
740}
741static inline u32 pwr_pmu_bar0_addr_r(void)
742{
743 return 0x0010a7a0;
744}
745static inline u32 pwr_pmu_bar0_data_r(void)
746{
747 return 0x0010a7a4;
748}
749static inline u32 pwr_pmu_bar0_ctl_r(void)
750{
751 return 0x0010a7ac;
752}
753static inline u32 pwr_pmu_bar0_timeout_r(void)
754{
755 return 0x0010a7a8;
756}
757static inline u32 pwr_pmu_bar0_fecs_error_r(void)
758{
759 return 0x0010a988;
760}
761static inline u32 pwr_pmu_bar0_error_status_r(void)
762{
763 return 0x0010a7b0;
764}
765static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
766{
767 return 0x0010a6c0 + i*4;
768}
769static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
770{
771 return 0x0010a6e8 + i*4;
772}
773static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
774{
775 return 0x0010a710 + i*4;
776}
777static inline u32 pwr_pmu_pg_intren_r(u32 i)
778{
779 return 0x0010a760 + i*4;
780}
781static inline u32 pwr_fbif_transcfg_r(u32 i)
782{
783 return 0x0010ae00 + i*4;
784}
785static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
786{
787 return 0x0;
788}
789static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
790{
791 return 0x1;
792}
793static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
794{
795 return 0x2;
796}
797static inline u32 pwr_fbif_transcfg_mem_type_s(void)
798{
799 return 1;
800}
801static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
802{
803 return (v & 0x1) << 2;
804}
805static inline u32 pwr_fbif_transcfg_mem_type_m(void)
806{
807 return 0x1 << 2;
808}
809static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
810{
811 return (r >> 2) & 0x1;
812}
813static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
814{
815 return 0x0;
816}
817static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
818{
819 return 0x4;
820}
821#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
deleted file mode 100644
index 863b15b85..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h
+++ /dev/null
@@ -1,481 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_ram_gp10b_h_
51#define _hw_ram_gp10b_h_
52
53static inline u32 ram_in_ramfc_s(void)
54{
55 return 4096;
56}
57static inline u32 ram_in_ramfc_w(void)
58{
59 return 0;
60}
61static inline u32 ram_in_page_dir_base_target_f(u32 v)
62{
63 return (v & 0x3) << 0;
64}
65static inline u32 ram_in_page_dir_base_target_w(void)
66{
67 return 128;
68}
69static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
70{
71 return 0x0;
72}
73static inline u32 ram_in_page_dir_base_vol_w(void)
74{
75 return 128;
76}
77static inline u32 ram_in_page_dir_base_vol_true_f(void)
78{
79 return 0x4;
80}
81static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
82{
83 return (v & 0x1) << 4;
84}
85static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
86{
87 return 0x1 << 4;
88}
89static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
90{
91 return 128;
92}
93static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
94{
95 return 0x10;
96}
97static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
98{
99 return (v & 0x1) << 5;
100}
101static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
102{
103 return 0x1 << 5;
104}
105static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
106{
107 return 128;
108}
109static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
110{
111 return 0x20;
112}
113static inline u32 ram_in_big_page_size_f(u32 v)
114{
115 return (v & 0x1) << 11;
116}
117static inline u32 ram_in_big_page_size_m(void)
118{
119 return 0x1 << 11;
120}
121static inline u32 ram_in_big_page_size_w(void)
122{
123 return 128;
124}
125static inline u32 ram_in_big_page_size_128kb_f(void)
126{
127 return 0x0;
128}
129static inline u32 ram_in_big_page_size_64kb_f(void)
130{
131 return 0x800;
132}
133static inline u32 ram_in_page_dir_base_lo_f(u32 v)
134{
135 return (v & 0xfffff) << 12;
136}
137static inline u32 ram_in_page_dir_base_lo_w(void)
138{
139 return 128;
140}
141static inline u32 ram_in_page_dir_base_hi_f(u32 v)
142{
143 return (v & 0xff) << 0;
144}
145static inline u32 ram_in_page_dir_base_hi_w(void)
146{
147 return 129;
148}
149static inline u32 ram_in_adr_limit_lo_f(u32 v)
150{
151 return (v & 0xfffff) << 12;
152}
153static inline u32 ram_in_adr_limit_lo_w(void)
154{
155 return 130;
156}
157static inline u32 ram_in_adr_limit_hi_f(u32 v)
158{
159 return (v & 0xffffffff) << 0;
160}
161static inline u32 ram_in_adr_limit_hi_w(void)
162{
163 return 131;
164}
165static inline u32 ram_in_engine_cs_w(void)
166{
167 return 132;
168}
169static inline u32 ram_in_engine_cs_wfi_v(void)
170{
171 return 0x00000000;
172}
173static inline u32 ram_in_engine_cs_wfi_f(void)
174{
175 return 0x0;
176}
177static inline u32 ram_in_engine_cs_fg_v(void)
178{
179 return 0x00000001;
180}
181static inline u32 ram_in_engine_cs_fg_f(void)
182{
183 return 0x8;
184}
185static inline u32 ram_in_gr_cs_w(void)
186{
187 return 132;
188}
189static inline u32 ram_in_gr_cs_wfi_f(void)
190{
191 return 0x0;
192}
193static inline u32 ram_in_gr_wfi_target_w(void)
194{
195 return 132;
196}
197static inline u32 ram_in_gr_wfi_mode_w(void)
198{
199 return 132;
200}
201static inline u32 ram_in_gr_wfi_mode_physical_v(void)
202{
203 return 0x00000000;
204}
205static inline u32 ram_in_gr_wfi_mode_physical_f(void)
206{
207 return 0x0;
208}
209static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
210{
211 return 0x00000001;
212}
213static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
214{
215 return 0x4;
216}
217static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
218{
219 return (v & 0xfffff) << 12;
220}
221static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
222{
223 return 132;
224}
225static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
226{
227 return (v & 0xff) << 0;
228}
229static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
230{
231 return 133;
232}
233static inline u32 ram_in_base_shift_v(void)
234{
235 return 0x0000000c;
236}
237static inline u32 ram_in_alloc_size_v(void)
238{
239 return 0x00001000;
240}
241static inline u32 ram_fc_size_val_v(void)
242{
243 return 0x00000200;
244}
245static inline u32 ram_fc_gp_put_w(void)
246{
247 return 0;
248}
249static inline u32 ram_fc_userd_w(void)
250{
251 return 2;
252}
253static inline u32 ram_fc_userd_hi_w(void)
254{
255 return 3;
256}
257static inline u32 ram_fc_signature_w(void)
258{
259 return 4;
260}
261static inline u32 ram_fc_gp_get_w(void)
262{
263 return 5;
264}
265static inline u32 ram_fc_pb_get_w(void)
266{
267 return 6;
268}
269static inline u32 ram_fc_pb_get_hi_w(void)
270{
271 return 7;
272}
273static inline u32 ram_fc_pb_top_level_get_w(void)
274{
275 return 8;
276}
277static inline u32 ram_fc_pb_top_level_get_hi_w(void)
278{
279 return 9;
280}
281static inline u32 ram_fc_acquire_w(void)
282{
283 return 12;
284}
285static inline u32 ram_fc_semaphorea_w(void)
286{
287 return 14;
288}
289static inline u32 ram_fc_semaphoreb_w(void)
290{
291 return 15;
292}
293static inline u32 ram_fc_semaphorec_w(void)
294{
295 return 16;
296}
297static inline u32 ram_fc_semaphored_w(void)
298{
299 return 17;
300}
301static inline u32 ram_fc_gp_base_w(void)
302{
303 return 18;
304}
305static inline u32 ram_fc_gp_base_hi_w(void)
306{
307 return 19;
308}
309static inline u32 ram_fc_gp_fetch_w(void)
310{
311 return 20;
312}
313static inline u32 ram_fc_pb_fetch_w(void)
314{
315 return 21;
316}
317static inline u32 ram_fc_pb_fetch_hi_w(void)
318{
319 return 22;
320}
321static inline u32 ram_fc_pb_put_w(void)
322{
323 return 23;
324}
325static inline u32 ram_fc_pb_put_hi_w(void)
326{
327 return 24;
328}
329static inline u32 ram_fc_pb_header_w(void)
330{
331 return 33;
332}
333static inline u32 ram_fc_pb_count_w(void)
334{
335 return 34;
336}
337static inline u32 ram_fc_subdevice_w(void)
338{
339 return 37;
340}
341static inline u32 ram_fc_formats_w(void)
342{
343 return 39;
344}
345static inline u32 ram_fc_allowed_syncpoints_w(void)
346{
347 return 58;
348}
349static inline u32 ram_fc_syncpointa_w(void)
350{
351 return 41;
352}
353static inline u32 ram_fc_syncpointb_w(void)
354{
355 return 42;
356}
357static inline u32 ram_fc_target_w(void)
358{
359 return 43;
360}
361static inline u32 ram_fc_hce_ctrl_w(void)
362{
363 return 57;
364}
365static inline u32 ram_fc_chid_w(void)
366{
367 return 58;
368}
369static inline u32 ram_fc_chid_id_f(u32 v)
370{
371 return (v & 0xfff) << 0;
372}
373static inline u32 ram_fc_chid_id_w(void)
374{
375 return 0;
376}
377static inline u32 ram_fc_runlist_timeslice_w(void)
378{
379 return 62;
380}
381static inline u32 ram_userd_base_shift_v(void)
382{
383 return 0x00000009;
384}
385static inline u32 ram_userd_chan_size_v(void)
386{
387 return 0x00000200;
388}
389static inline u32 ram_userd_put_w(void)
390{
391 return 16;
392}
393static inline u32 ram_userd_get_w(void)
394{
395 return 17;
396}
397static inline u32 ram_userd_ref_w(void)
398{
399 return 18;
400}
401static inline u32 ram_userd_put_hi_w(void)
402{
403 return 19;
404}
405static inline u32 ram_userd_ref_threshold_w(void)
406{
407 return 20;
408}
409static inline u32 ram_userd_top_level_get_w(void)
410{
411 return 22;
412}
413static inline u32 ram_userd_top_level_get_hi_w(void)
414{
415 return 23;
416}
417static inline u32 ram_userd_get_hi_w(void)
418{
419 return 24;
420}
421static inline u32 ram_userd_gp_get_w(void)
422{
423 return 34;
424}
425static inline u32 ram_userd_gp_put_w(void)
426{
427 return 35;
428}
429static inline u32 ram_userd_gp_top_level_get_w(void)
430{
431 return 22;
432}
433static inline u32 ram_userd_gp_top_level_get_hi_w(void)
434{
435 return 23;
436}
437static inline u32 ram_rl_entry_size_v(void)
438{
439 return 0x00000008;
440}
441static inline u32 ram_rl_entry_chid_f(u32 v)
442{
443 return (v & 0xfff) << 0;
444}
445static inline u32 ram_rl_entry_id_f(u32 v)
446{
447 return (v & 0xfff) << 0;
448}
449static inline u32 ram_rl_entry_type_f(u32 v)
450{
451 return (v & 0x1) << 13;
452}
453static inline u32 ram_rl_entry_type_chid_f(void)
454{
455 return 0x0;
456}
457static inline u32 ram_rl_entry_type_tsg_f(void)
458{
459 return 0x2000;
460}
461static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
462{
463 return (v & 0xf) << 14;
464}
465static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
466{
467 return 0xc000;
468}
469static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
470{
471 return (v & 0xff) << 18;
472}
473static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
474{
475 return 0x2000000;
476}
477static inline u32 ram_rl_entry_tsg_length_f(u32 v)
478{
479 return (v & 0x3f) << 26;
480}
481#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h
deleted file mode 100644
index 8a587b7c5..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h
+++ /dev/null
@@ -1,409 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_therm_gp10b_h_
51#define _hw_therm_gp10b_h_
52
53static inline u32 therm_use_a_r(void)
54{
55 return 0x00020798;
56}
57static inline u32 therm_use_a_ext_therm_0_enable_f(void)
58{
59 return 0x1;
60}
61static inline u32 therm_use_a_ext_therm_1_enable_f(void)
62{
63 return 0x2;
64}
65static inline u32 therm_use_a_ext_therm_2_enable_f(void)
66{
67 return 0x4;
68}
69static inline u32 therm_evt_ext_therm_0_r(void)
70{
71 return 0x00020700;
72}
73static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
74{
75 return (v & 0x3f) << 24;
76}
77static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
78{
79 return 0x00000001;
80}
81static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
82{
83 return (v & 0x3) << 30;
84}
85static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
86{
87 return 0x00000000;
88}
89static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
90{
91 return 0x00000001;
92}
93static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
94{
95 return 0x00000002;
96}
97static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
98{
99 return 0x00000003;
100}
101static inline u32 therm_evt_ext_therm_1_r(void)
102{
103 return 0x00020704;
104}
105static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
106{
107 return (v & 0x3f) << 24;
108}
109static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
110{
111 return 0x00000002;
112}
113static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
114{
115 return (v & 0x3) << 30;
116}
117static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
118{
119 return 0x00000000;
120}
121static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
122{
123 return 0x00000001;
124}
125static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
126{
127 return 0x00000002;
128}
129static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
130{
131 return 0x00000003;
132}
133static inline u32 therm_evt_ext_therm_2_r(void)
134{
135 return 0x00020708;
136}
137static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
138{
139 return (v & 0x3f) << 24;
140}
141static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
142{
143 return 0x00000003;
144}
145static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
146{
147 return (v & 0x3) << 30;
148}
149static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
150{
151 return 0x00000000;
152}
153static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
154{
155 return 0x00000001;
156}
157static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
158{
159 return 0x00000002;
160}
161static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
162{
163 return 0x00000003;
164}
165static inline u32 therm_weight_1_r(void)
166{
167 return 0x00020024;
168}
169static inline u32 therm_config1_r(void)
170{
171 return 0x00020050;
172}
173static inline u32 therm_config2_r(void)
174{
175 return 0x00020130;
176}
177static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
178{
179 return (v & 0x1) << 24;
180}
181static inline u32 therm_config2_grad_enable_f(u32 v)
182{
183 return (v & 0x1) << 31;
184}
185static inline u32 therm_gate_ctrl_r(u32 i)
186{
187 return 0x00020200 + i*4;
188}
189static inline u32 therm_gate_ctrl_eng_clk_m(void)
190{
191 return 0x3 << 0;
192}
193static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
194{
195 return 0x0;
196}
197static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
198{
199 return 0x1;
200}
201static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
202{
203 return 0x2;
204}
205static inline u32 therm_gate_ctrl_blk_clk_m(void)
206{
207 return 0x3 << 2;
208}
209static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
210{
211 return 0x0;
212}
213static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
214{
215 return 0x4;
216}
217static inline u32 therm_gate_ctrl_eng_pwr_m(void)
218{
219 return 0x3 << 4;
220}
221static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
222{
223 return 0x10;
224}
225static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
226{
227 return 0x00000002;
228}
229static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
230{
231 return 0x20;
232}
233static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
234{
235 return (v & 0x1f) << 8;
236}
237static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
238{
239 return 0x1f << 8;
240}
241static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
242{
243 return (v & 0x7) << 13;
244}
245static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
246{
247 return 0x7 << 13;
248}
249static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
250{
251 return (v & 0xf) << 16;
252}
253static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
254{
255 return 0xf << 16;
256}
257static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
258{
259 return (v & 0xf) << 20;
260}
261static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
262{
263 return 0xf << 20;
264}
265static inline u32 therm_fecs_idle_filter_r(void)
266{
267 return 0x00020288;
268}
269static inline u32 therm_fecs_idle_filter_value_m(void)
270{
271 return 0xffffffff << 0;
272}
273static inline u32 therm_hubmmu_idle_filter_r(void)
274{
275 return 0x0002028c;
276}
277static inline u32 therm_hubmmu_idle_filter_value_m(void)
278{
279 return 0xffffffff << 0;
280}
281static inline u32 therm_clk_slowdown_r(u32 i)
282{
283 return 0x00020160 + i*4;
284}
285static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
286{
287 return (v & 0x3f) << 16;
288}
289static inline u32 therm_clk_slowdown_idle_factor_m(void)
290{
291 return 0x3f << 16;
292}
293static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
294{
295 return (r >> 16) & 0x3f;
296}
297static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
298{
299 return 0x0;
300}
301static inline u32 therm_grad_stepping_table_r(u32 i)
302{
303 return 0x000202c8 + i*4;
304}
305static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
306{
307 return (v & 0x3f) << 0;
308}
309static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
310{
311 return 0x3f << 0;
312}
313static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
314{
315 return 0x1;
316}
317static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
318{
319 return 0x2;
320}
321static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
322{
323 return 0x6;
324}
325static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
326{
327 return 0xe;
328}
329static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
330{
331 return (v & 0x3f) << 6;
332}
333static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
334{
335 return 0x3f << 6;
336}
337static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
338{
339 return (v & 0x3f) << 12;
340}
341static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
342{
343 return 0x3f << 12;
344}
345static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
346{
347 return (v & 0x3f) << 18;
348}
349static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
350{
351 return 0x3f << 18;
352}
353static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
354{
355 return (v & 0x3f) << 24;
356}
357static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
358{
359 return 0x3f << 24;
360}
361static inline u32 therm_grad_stepping0_r(void)
362{
363 return 0x000202c0;
364}
365static inline u32 therm_grad_stepping0_feature_s(void)
366{
367 return 1;
368}
369static inline u32 therm_grad_stepping0_feature_f(u32 v)
370{
371 return (v & 0x1) << 0;
372}
373static inline u32 therm_grad_stepping0_feature_m(void)
374{
375 return 0x1 << 0;
376}
377static inline u32 therm_grad_stepping0_feature_v(u32 r)
378{
379 return (r >> 0) & 0x1;
380}
381static inline u32 therm_grad_stepping0_feature_enable_f(void)
382{
383 return 0x1;
384}
385static inline u32 therm_grad_stepping1_r(void)
386{
387 return 0x000202c4;
388}
389static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
390{
391 return (v & 0x1ffff) << 0;
392}
393static inline u32 therm_clk_timing_r(u32 i)
394{
395 return 0x000203c0 + i*4;
396}
397static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
398{
399 return (v & 0x1) << 16;
400}
401static inline u32 therm_clk_timing_grad_slowdown_m(void)
402{
403 return 0x1 << 16;
404}
405static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
406{
407 return 0x10000;
408}
409#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h
deleted file mode 100644
index df27154ff..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_timer_gp10b_h_
51#define _hw_timer_gp10b_h_
52
53static inline u32 timer_pri_timeout_r(void)
54{
55 return 0x00009080;
56}
57static inline u32 timer_pri_timeout_period_f(u32 v)
58{
59 return (v & 0xffffff) << 0;
60}
61static inline u32 timer_pri_timeout_period_m(void)
62{
63 return 0xffffff << 0;
64}
65static inline u32 timer_pri_timeout_period_v(u32 r)
66{
67 return (r >> 0) & 0xffffff;
68}
69static inline u32 timer_pri_timeout_en_f(u32 v)
70{
71 return (v & 0x1) << 31;
72}
73static inline u32 timer_pri_timeout_en_m(void)
74{
75 return 0x1 << 31;
76}
77static inline u32 timer_pri_timeout_en_v(u32 r)
78{
79 return (r >> 31) & 0x1;
80}
81static inline u32 timer_pri_timeout_en_en_enabled_f(void)
82{
83 return 0x80000000;
84}
85static inline u32 timer_pri_timeout_en_en_disabled_f(void)
86{
87 return 0x0;
88}
89static inline u32 timer_pri_timeout_save_0_r(void)
90{
91 return 0x00009084;
92}
93static inline u32 timer_pri_timeout_save_1_r(void)
94{
95 return 0x00009088;
96}
97static inline u32 timer_pri_timeout_fecs_errcode_r(void)
98{
99 return 0x0000908c;
100}
101static inline u32 timer_time_0_r(void)
102{
103 return 0x00009400;
104}
105static inline u32 timer_time_1_r(void)
106{
107 return 0x00009410;
108}
109#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h
deleted file mode 100644
index ab6f63736..000000000
--- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h
+++ /dev/null
@@ -1,161 +0,0 @@
1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_top_gp10b_h_
51#define _hw_top_gp10b_h_
52
53static inline u32 top_num_gpcs_r(void)
54{
55 return 0x00022430;
56}
57static inline u32 top_num_gpcs_value_v(u32 r)
58{
59 return (r >> 0) & 0x1f;
60}
61static inline u32 top_tpc_per_gpc_r(void)
62{
63 return 0x00022434;
64}
65static inline u32 top_tpc_per_gpc_value_v(u32 r)
66{
67 return (r >> 0) & 0x1f;
68}
69static inline u32 top_num_fbps_r(void)
70{
71 return 0x00022438;
72}
73static inline u32 top_num_fbps_value_v(u32 r)
74{
75 return (r >> 0) & 0x1f;
76}
77static inline u32 top_ltc_per_fbp_r(void)
78{
79 return 0x00022450;
80}
81static inline u32 top_ltc_per_fbp_value_v(u32 r)
82{
83 return (r >> 0) & 0x1f;
84}
85static inline u32 top_slices_per_ltc_r(void)
86{
87 return 0x0002245c;
88}
89static inline u32 top_slices_per_ltc_value_v(u32 r)
90{
91 return (r >> 0) & 0x1f;
92}
93static inline u32 top_num_ltcs_r(void)
94{
95 return 0x00022454;
96}
97static inline u32 top_device_info_r(u32 i)
98{
99 return 0x00022700 + i*4;
100}
101static inline u32 top_device_info__size_1_v(void)
102{
103 return 0x00000040;
104}
105static inline u32 top_device_info_chain_v(u32 r)
106{
107 return (r >> 31) & 0x1;
108}
109static inline u32 top_device_info_chain_enable_v(void)
110{
111 return 0x00000001;
112}
113static inline u32 top_device_info_engine_enum_v(u32 r)
114{
115 return (r >> 26) & 0xf;
116}
117static inline u32 top_device_info_runlist_enum_v(u32 r)
118{
119 return (r >> 21) & 0xf;
120}
121static inline u32 top_device_info_intr_enum_v(u32 r)
122{
123 return (r >> 15) & 0x1f;
124}
125static inline u32 top_device_info_reset_enum_v(u32 r)
126{
127 return (r >> 9) & 0x1f;
128}
129static inline u32 top_device_info_type_enum_v(u32 r)
130{
131 return (r >> 2) & 0x1fffffff;
132}
133static inline u32 top_device_info_type_enum_graphics_v(void)
134{
135 return 0x00000000;
136}
137static inline u32 top_device_info_type_enum_graphics_f(void)
138{
139 return 0x0;
140}
141static inline u32 top_device_info_type_enum_copy0_v(void)
142{
143 return 0x00000001;
144}
145static inline u32 top_device_info_type_enum_copy0_f(void)
146{
147 return 0x4;
148}
149static inline u32 top_device_info_entry_v(u32 r)
150{
151 return (r >> 0) & 0x3;
152}
153static inline u32 top_device_info_entry_not_valid_v(void)
154{
155 return 0x00000000;
156}
157static inline u32 top_device_info_entry_enum_v(void)
158{
159 return 0x00000002;
160}
161#endif
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
deleted file mode 100644
index e68e762d3..000000000
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ /dev/null
@@ -1,226 +0,0 @@
1/*
2 * GP10B L2
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17
18#include <dt-bindings/memory/tegra-swgroup.h>
19
20#include "gk20a/gk20a.h"
21#include "gm20b/ltc_gm20b.h"
22#include "hw_proj_gp10b.h"
23#include "hw_mc_gp10b.h"
24#include "hw_ltc_gp10b.h"
25
26#include "gk20a/ltc_common.c"
27
28static int gp10b_determine_L2_size_bytes(struct gk20a *g)
29{
30 u32 tmp;
31 int ret;
32
33 gk20a_dbg_fn("");
34
35 tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r());
36
37 ret = g->ltc_count *
38 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp)*1024 *
39 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp);
40
41 gk20a_dbg(gpu_dbg_info, "L2 size: %d\n", ret);
42
43 gk20a_dbg_fn("done");
44
45 return ret;
46}
47
48static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
49{
50 /* max memory size (MB) to cover */
51 u32 max_size = gr->max_comptag_mem;
52 /* one tag line covers 64KB */
53 u32 max_comptag_lines = max_size << 4;
54
55 u32 hw_max_comptag_lines =
56 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v();
57
58 u32 cbc_param =
59 gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r());
60 u32 comptags_per_cacheline =
61 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param);
62 u32 cacheline_size =
63 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param);
64 u32 slices_per_ltc =
65 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param);
66 u32 cbc_param2 =
67 gk20a_readl(g, ltc_ltcs_ltss_cbc_param2_r());
68 u32 gobs_per_comptagline_per_slice =
69 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(cbc_param2);
70
71 u32 compbit_backing_size;
72
73 int err;
74
75 gk20a_dbg_fn("");
76
77 if (max_comptag_lines == 0)
78 return 0;
79
80 if (max_comptag_lines > hw_max_comptag_lines)
81 max_comptag_lines = hw_max_comptag_lines;
82
83 compbit_backing_size =
84 roundup(max_comptag_lines * gobs_per_comptagline_per_slice,
85 cacheline_size);
86 compbit_backing_size =
87 roundup(compbit_backing_size * slices_per_ltc * g->ltc_count,
88 g->ops.fb.compressible_page_size(g));
89
90 /* aligned to 2KB * ltc_count */
91 compbit_backing_size +=
92 g->ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v();
93
94 /* must be a multiple of 64KB */
95 compbit_backing_size = roundup(compbit_backing_size, 64*1024);
96
97 gk20a_dbg_info("compbit backing store size : %d",
98 compbit_backing_size);
99 gk20a_dbg_info("max comptag lines : %d",
100 max_comptag_lines);
101 gk20a_dbg_info("gobs_per_comptagline_per_slice: %d",
102 gobs_per_comptagline_per_slice);
103
104 if (tegra_platform_is_linsim())
105 err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
106 else
107 err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);
108
109 if (err)
110 return err;
111
112 err = gk20a_comptag_allocator_init(&gr->comp_tags, max_comptag_lines);
113 if (err)
114 return err;
115
116 gr->comptags_per_cacheline = comptags_per_cacheline;
117 gr->slices_per_ltc = slices_per_ltc;
118 gr->cacheline_size = cacheline_size;
119 gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice;
120
121 return 0;
122}
123
124static void gp10b_ltc_isr(struct gk20a *g)
125{
126 u32 mc_intr, ltc_intr;
127 int ltc, slice;
128
129 mc_intr = gk20a_readl(g, mc_intr_ltc_r());
130 gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x",
131 mc_intr);
132 for (ltc = 0; ltc < g->ltc_count; ltc++) {
133 if ((mc_intr & 1 << ltc) == 0)
134 continue;
135 for (slice = 0; slice < g->gr.slices_per_ltc; slice++) {
136 u32 offset = proj_ltc_stride_v() * ltc +
137 proj_lts_stride_v() * slice;
138 ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset);
139
140 /* Detect and handle ECC errors */
141 if (ltc_intr &
142 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) {
143 u32 ecc_stats_reg_val;
144
145 gk20a_err(dev_from_gk20a(g),
146 "Single bit error detected in GPU L2!");
147
148 ecc_stats_reg_val =
149 gk20a_readl(g,
150 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
151 g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] +=
152 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
153 ecc_stats_reg_val &=
154 ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
155 gk20a_writel(g,
156 ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
157 ecc_stats_reg_val);
158
159 g->ops.mm.l2_flush(g, true);
160 }
161 if (ltc_intr &
162 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) {
163 u32 ecc_stats_reg_val;
164
165 gk20a_err(dev_from_gk20a(g),
166 "Double bit error detected in GPU L2!");
167
168 ecc_stats_reg_val =
169 gk20a_readl(g,
170 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
171 g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] +=
172 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
173 ecc_stats_reg_val &=
174 ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());
175 gk20a_writel(g,
176 ltc_ltc0_lts0_dstg_ecc_report_r() + offset,
177 ecc_stats_reg_val);
178 }
179
180 gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x",
181 ltc, slice, ltc_intr);
182 gk20a_writel(g, ltc_ltc0_lts0_intr_r() +
183 proj_ltc_stride_v() * ltc +
184 proj_lts_stride_v() * slice,
185 ltc_intr);
186 }
187 }
188}
189
190static void gp10b_ltc_init_fs_state(struct gk20a *g)
191{
192 u32 ltc_intr;
193
194 gm20b_ltc_init_fs_state(g);
195
196 gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(),
197 ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB));
198
199 /* Enable ECC interrupts */
200 ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r());
201 ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() |
202 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f();
203 gk20a_writel(g, ltc_ltcs_ltss_intr_r(),
204 ltc_intr);
205}
206
207void gp10b_init_ltc(struct gpu_ops *gops)
208{
209 gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes;
210 gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last;
211 gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry;
212 gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry;
213 gops->ltc.init_cbc = gk20a_ltc_init_cbc;
214
215 /* GM20b specific ops. */
216 gops->ltc.init_fs_state = gp10b_ltc_init_fs_state;
217 gops->ltc.init_comptags = gp10b_ltc_init_comptags;
218 gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl;
219 gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked;
220 gops->ltc.isr = gp10b_ltc_isr;
221 gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
222 gops->ltc.flush = gm20b_flush_ltc;
223#ifdef CONFIG_DEBUG_FS
224 gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
225#endif
226}
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h
deleted file mode 100644
index 7408348e7..000000000
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef LTC_GP10B_H
15#define LTC_GP10B_H
16struct gpu_ops;
17
18void gp10b_init_ltc(struct gpu_ops *gops);
19#endif
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
deleted file mode 100644
index 47c8fcc6f..000000000
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * GP20B master
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17
18#include "gk20a/gk20a.h"
19#include "mc_gp10b.h"
20#include "hw_mc_gp10b.h"
21
22void mc_gp10b_intr_enable(struct gk20a *g)
23{
24 u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
25
26 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
27 0xffffffff);
28 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] =
29 mc_intr_pfifo_pending_f()
30 | mc_intr_replayable_fault_pending_f()
31 | eng_intr_mask;
32 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
33 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
34
35 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
36 0xffffffff);
37 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
38 mc_intr_pfifo_pending_f()
39 | mc_intr_priv_ring_pending_f()
40 | mc_intr_ltc_pending_f()
41 | mc_intr_pbus_pending_f()
42 | eng_intr_mask;
43 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
44 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
45}
46
47void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
48 bool is_stalling, u32 mask)
49{
50 u32 intr_index = 0;
51 u32 reg = 0;
52
53 intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING :
54 NVGPU_MC_INTR_NONSTALLING);
55 if (enable) {
56 reg = mc_intr_en_set_r(intr_index);
57 g->ops.mc.intr_mask_restore[intr_index] |= mask;
58
59 } else {
60 reg = mc_intr_en_clear_r(intr_index);
61 g->ops.mc.intr_mask_restore[intr_index] &= ~mask;
62 }
63
64 gk20a_writel(g, reg, mask);
65}
66
67irqreturn_t mc_gp10b_isr_stall(struct gk20a *g)
68{
69 u32 mc_intr_0;
70
71 if (!g->power_on)
72 return IRQ_NONE;
73
74 /* not from gpu when sharing irq with others */
75 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
76 if (unlikely(!mc_intr_0))
77 return IRQ_NONE;
78
79 gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff);
80
81 return IRQ_WAKE_THREAD;
82}
83
84irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
85{
86 u32 mc_intr_1;
87
88 if (!g->power_on)
89 return IRQ_NONE;
90
91 /* not from gpu when sharing irq with others */
92 mc_intr_1 = gk20a_readl(g, mc_intr_r(1));
93 if (unlikely(!mc_intr_1))
94 return IRQ_NONE;
95
96 gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff);
97
98 return IRQ_WAKE_THREAD;
99}
100
101irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
102{
103 u32 mc_intr_0;
104
105 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
106
107 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
108
109 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
110
111 if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
112 gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
113 if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
114 && g->ops.ce2.isr_stall)
115 g->ops.ce2.isr_stall(g);
116 if (mc_intr_0 & mc_intr_pfifo_pending_f())
117 gk20a_fifo_isr(g);
118 if (mc_intr_0 & mc_intr_pmu_pending_f())
119 gk20a_pmu_isr(g);
120 if (mc_intr_0 & mc_intr_priv_ring_pending_f())
121 gk20a_priv_ring_isr(g);
122 if (mc_intr_0 & mc_intr_ltc_pending_f())
123 g->ops.ltc.isr(g);
124 if (mc_intr_0 & mc_intr_pbus_pending_f())
125 gk20a_pbus_isr(g);
126
127 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
128 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]);
129
130 return IRQ_HANDLED;
131}
132
133irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
134{
135 u32 mc_intr_1;
136
137 gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
138
139 mc_intr_1 = gk20a_readl(g, mc_intr_r(1));
140
141 gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1);
142
143 if (mc_intr_1 & mc_intr_pfifo_pending_f())
144 gk20a_fifo_nonstall_isr(g);
145 if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
146 gk20a_gr_nonstall_isr(g);
147 if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)
148 && g->ops.ce2.isr_nonstall)
149 g->ops.ce2.isr_nonstall(g);
150
151
152
153 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
154 g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
155
156 return IRQ_HANDLED;
157}
158
159void gp10b_init_mc(struct gpu_ops *gops)
160{
161 gops->mc.intr_enable = mc_gp10b_intr_enable;
162 gops->mc.intr_unit_config = mc_gp10b_intr_unit_config;
163 gops->mc.isr_stall = mc_gp10b_isr_stall;
164 gops->mc.isr_nonstall = mc_gp10b_isr_nonstall;
165 gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall;
166 gops->mc.isr_thread_nonstall = mc_gp10b_intr_thread_nonstall;
167}
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
deleted file mode 100644
index b2ec4be4c..000000000
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef MC_GP20B_H
15#define MC_GP20B_H
16struct gk20a;
17
18enum MC_INTERRUPT_REGLIST {
19 NVGPU_MC_INTR_STALLING = 0,
20 NVGPU_MC_INTR_NONSTALLING,
21};
22
23void gp10b_init_mc(struct gpu_ops *gops);
24void mc_gp10b_intr_enable(struct gk20a *g);
25void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
26 bool is_stalling, u32 mask);
27irqreturn_t mc_gp10b_isr_stall(struct gk20a *g);
28irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g);
29irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g);
30irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g);
31#endif
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
deleted file mode 100644
index d4a4e7f3d..000000000
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ /dev/null
@@ -1,391 +0,0 @@
1/*
2 * GP10B MMU
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/pm_runtime.h>
17#include <linux/dma-mapping.h>
18#include "gk20a/gk20a.h"
19#include "mm_gp10b.h"
20#include "rpfb_gp10b.h"
21#include "hw_ram_gp10b.h"
22#include "hw_bus_gp10b.h"
23#include "hw_gmmu_gp10b.h"
24#include "gk20a/semaphore_gk20a.h"
25
26static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g)
27{
28 return 36;
29}
30
31static int gp10b_init_mm_setup_hw(struct gk20a *g)
32{
33 struct mm_gk20a *mm = &g->mm;
34 struct mem_desc *inst_block = &mm->bar1.inst_block;
35 phys_addr_t inst_pa = gk20a_mem_phys(inst_block);
36 int err = 0;
37
38 gk20a_dbg_fn("");
39
40 g->ops.fb.set_mmu_page_size(g);
41
42 inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a());
43 gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa);
44
45 gk20a_writel(g, bus_bar1_block_r(),
46 bus_bar1_block_target_vid_mem_f() |
47 bus_bar1_block_mode_virtual_f() |
48 bus_bar1_block_ptr_f(inst_pa));
49
50 if (g->ops.mm.init_bar2_mm_hw_setup) {
51 err = g->ops.mm.init_bar2_mm_hw_setup(g);
52 if (err)
53 return err;
54 }
55
56 if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g))
57 return -EBUSY;
58
59 err = gp10b_replayable_pagefault_buffer_init(g);
60
61 gk20a_dbg_fn("done");
62 return err;
63
64}
65
66static int gb10b_init_bar2_vm(struct gk20a *g)
67{
68 int err;
69 struct mm_gk20a *mm = &g->mm;
70 struct vm_gk20a *vm = &mm->bar2.vm;
71 struct mem_desc *inst_block = &mm->bar2.inst_block;
72 u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size;
73
74 /* BAR2 aperture size is 32MB */
75 mm->bar2.aperture_size = 32 << 20;
76 gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size);
77 gk20a_init_vm(mm, vm, big_page_size, SZ_4K,
78 mm->bar2.aperture_size - SZ_4K,
79 mm->bar2.aperture_size, false, false, "bar2");
80
81 /* allocate instance mem for bar2 */
82 err = gk20a_alloc_inst_block(g, inst_block);
83 if (err)
84 goto clean_up_va;
85
86 gk20a_init_inst_block(inst_block, vm, big_page_size);
87
88 return 0;
89
90clean_up_va:
91 gk20a_deinit_vm(vm);
92 return err;
93}
94
95
96static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g)
97{
98 struct mm_gk20a *mm = &g->mm;
99 struct mem_desc *inst_block = &mm->bar2.inst_block;
100 phys_addr_t inst_pa = gk20a_mem_phys(inst_block);
101
102 gk20a_dbg_fn("");
103
104 g->ops.fb.set_mmu_page_size(g);
105
106 inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v());
107 gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa);
108
109 gk20a_writel(g, bus_bar2_block_r(),
110 bus_bar2_block_target_vid_mem_f() |
111 bus_bar2_block_mode_virtual_f() |
112 bus_bar2_block_ptr_f(inst_pa));
113
114 gk20a_dbg_fn("done");
115 return 0;
116}
117
118static u64 gp10b_mm_phys_addr_translate(struct gk20a *g, u64 phys_addr,
119 u32 flags)
120{
121 if (!device_is_iommuable(dev_from_gk20a(g)))
122 if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT)
123 return phys_addr |
124 1ULL << NVGPU_MM_GET_IO_COHERENCE_BIT;
125
126 return phys_addr;
127}
128
129static u64 gp10b_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl,
130 u32 flags)
131{
132 if (!device_is_iommuable(dev_from_gk20a(g)))
133 return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags);
134
135 if (sg_dma_address(sgl) == 0)
136 return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags);
137
138 if (sg_dma_address(sgl) == DMA_ERROR_CODE)
139 return 0;
140
141 return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl));
142}
143
144static u32 *pde3_from_index(struct gk20a_mm_entry *entry, u32 i)
145{
146 return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_pde__size_v());
147}
148
149static int update_gmmu_pde3_locked(struct vm_gk20a *vm,
150 struct gk20a_mm_entry *parent,
151 u32 i, u32 gmmu_pgsz_idx,
152 struct scatterlist **sgl,
153 u64 *offset,
154 u64 *iova,
155 u32 kind_v, u64 *ctag,
156 bool cacheable, bool unmapped_pte,
157 int rw_flag, bool sparse, bool priv)
158{
159 u64 pte_addr = 0;
160 u64 pde_addr = 0;
161 struct gk20a_mm_entry *pte = parent->entries + i;
162 u32 pde_v[2] = {0, 0};
163 u32 *pde;
164
165 gk20a_dbg_fn("");
166
167 pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v();
168 pde_addr = sg_phys(parent->sgt->sgl);
169
170 pde_v[0] |= gmmu_new_pde_aperture_video_memory_f();
171 pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr));
172 pde_v[0] |= gmmu_new_pde_vol_true_f();
173 pde_v[1] |= pte_addr >> 24;
174 pde = pde3_from_index(parent, i);
175
176 gk20a_mem_wr32(pde, 0, pde_v[0]);
177 gk20a_mem_wr32(pde, 1, pde_v[1]);
178
179 gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d = 0x%x,0x%08x",
180 i, gmmu_pgsz_idx, pde_v[1], pde_v[0]);
181 gk20a_dbg_fn("done");
182 return 0;
183}
184
185static u32 *pde0_from_index(struct gk20a_mm_entry *entry, u32 i)
186{
187 return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_dual_pde__size_v());
188}
189
190static int update_gmmu_pde0_locked(struct vm_gk20a *vm,
191 struct gk20a_mm_entry *pte,
192 u32 i, u32 gmmu_pgsz_idx,
193 struct scatterlist **sgl,
194 u64 *offset,
195 u64 *iova,
196 u32 kind_v, u64 *ctag,
197 bool cacheable, bool unmapped_pte,
198 int rw_flag, bool sparse, bool priv)
199{
200 bool small_valid, big_valid;
201 u32 pte_addr_small = 0, pte_addr_big = 0;
202 struct gk20a_mm_entry *entry = pte->entries + i;
203 u32 pde_v[4] = {0, 0, 0, 0};
204 u32 *pde;
205
206 gk20a_dbg_fn("");
207
208 small_valid = entry->size && entry->pgsz == gmmu_page_size_small;
209 big_valid = entry->size && entry->pgsz == gmmu_page_size_big;
210
211 if (small_valid)
212 pte_addr_small = sg_phys(entry->sgt->sgl)
213 >> gmmu_new_dual_pde_address_shift_v();
214
215 if (big_valid)
216 pte_addr_big = sg_phys(entry->sgt->sgl)
217 >> gmmu_new_dual_pde_address_big_shift_v();
218
219 if (small_valid) {
220 pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small);
221 pde_v[2] |= gmmu_new_dual_pde_aperture_small_video_memory_f();
222 pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f();
223 pde_v[3] |= pte_addr_small >> 24;
224 }
225
226 if (big_valid) {
227 pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big);
228 pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f();
229 pde_v[0] |= gmmu_new_dual_pde_aperture_big_video_memory_f();
230 pde_v[1] |= pte_addr_big >> 28;
231 }
232
233 pde = pde0_from_index(pte, i);
234
235 gk20a_mem_wr32(pde, 0, pde_v[0]);
236 gk20a_mem_wr32(pde, 1, pde_v[1]);
237 gk20a_mem_wr32(pde, 2, pde_v[2]);
238 gk20a_mem_wr32(pde, 3, pde_v[3]);
239
240 gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d [0x%08x, 0x%08x, 0x%x, 0x%08x]",
241 i, gmmu_pgsz_idx, pde_v[3], pde_v[2], pde_v[1], pde_v[0]);
242 gk20a_dbg_fn("done");
243 return 0;
244}
245
246static int update_gmmu_pte_locked(struct vm_gk20a *vm,
247 struct gk20a_mm_entry *pte,
248 u32 i, u32 gmmu_pgsz_idx,
249 struct scatterlist **sgl,
250 u64 *offset,
251 u64 *iova,
252 u32 kind_v, u64 *ctag,
253 bool cacheable, bool unmapped_pte,
254 int rw_flag, bool sparse, bool priv)
255{
256 struct gk20a *g = vm->mm->g;
257 u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx];
258 u64 ctag_granularity = g->ops.fb.compression_page_size(g);
259 u32 pte_w[2] = {0, 0}; /* invalid pte */
260
261 gk20a_dbg_fn("");
262
263 if (*iova) {
264 if (unmapped_pte)
265 pte_w[0] = gmmu_new_pte_valid_false_f();
266 else
267 pte_w[0] = gmmu_new_pte_valid_true_f();
268 pte_w[0] |= gmmu_new_pte_aperture_video_memory_f() |
269 gmmu_new_pte_address_sys_f(*iova
270 >> gmmu_new_pte_address_shift_v());
271
272 if (priv)
273 pte_w[0] |= gmmu_new_pte_privilege_true_f();
274
275 pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) |
276 gmmu_new_pte_kind_f(kind_v) |
277 gmmu_new_pte_comptagline_f((u32)(*ctag / ctag_granularity));
278
279 if (rw_flag == gk20a_mem_flag_read_only)
280 pte_w[0] |= gmmu_new_pte_read_only_true_f();
281 if (unmapped_pte && !cacheable)
282 pte_w[0] |= gmmu_new_pte_read_only_true_f();
283 else if (!cacheable)
284 pte_w[0] |= gmmu_new_pte_vol_true_f();
285
286 gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d"
287 " ctag=%d vol=%d"
288 " [0x%08x, 0x%08x]",
289 i, *iova,
290 kind_v, (u32)(*ctag / ctag_granularity), !cacheable,
291 pte_w[1], pte_w[0]);
292
293 if (*ctag)
294 *ctag += page_size;
295 } else if (sparse) {
296 pte_w[0] = gmmu_new_pte_valid_false_f();
297 pte_w[0] |= gmmu_new_pte_vol_true_f();
298 } else {
299 gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i);
300 }
301
302 gk20a_mem_wr32(pte->cpu_va + i*8, 0, pte_w[0]);
303 gk20a_mem_wr32(pte->cpu_va + i*8, 1, pte_w[1]);
304
305 if (*iova) {
306 *iova += page_size;
307 *offset += page_size;
308 if (*sgl && *offset + page_size > (*sgl)->length) {
309 u64 new_iova;
310 *sgl = sg_next(*sgl);
311 if (*sgl) {
312 new_iova = sg_phys(*sgl);
313 gk20a_dbg(gpu_dbg_pte, "chunk address %llx, size %d",
314 new_iova, (*sgl)->length);
315 if (new_iova) {
316 *offset = 0;
317 *iova = new_iova;
318 }
319 }
320 }
321 }
322 gk20a_dbg_fn("done");
323 return 0;
324}
325
326static const struct gk20a_mmu_level gp10b_mm_levels[] = {
327 {.hi_bit = {48, 48},
328 .lo_bit = {47, 47},
329 .update_entry = update_gmmu_pde3_locked,
330 .entry_size = 8},
331 {.hi_bit = {46, 46},
332 .lo_bit = {38, 38},
333 .update_entry = update_gmmu_pde3_locked,
334 .entry_size = 8},
335 {.hi_bit = {37, 37},
336 .lo_bit = {29, 29},
337 .update_entry = update_gmmu_pde3_locked,
338 .entry_size = 8},
339 {.hi_bit = {28, 28},
340 .lo_bit = {21, 21},
341 .update_entry = update_gmmu_pde0_locked,
342 .entry_size = 16},
343 {.hi_bit = {20, 20},
344 .lo_bit = {12, 16},
345 .update_entry = update_gmmu_pte_locked,
346 .entry_size = 8},
347 {.update_entry = NULL}
348};
349
350static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g,
351 u32 big_page_size)
352{
353 return gp10b_mm_levels;
354}
355
356static void gp10b_mm_init_pdb(struct gk20a *g, void *inst_ptr, u64 pdb_addr)
357{
358 u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v());
359 u32 pdb_addr_hi = u64_hi32(pdb_addr);
360
361 gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(),
362 ram_in_page_dir_base_target_vid_mem_f() |
363 ram_in_page_dir_base_vol_true_f() |
364 ram_in_page_dir_base_lo_f(pdb_addr_lo) |
365 1 << 10);
366
367 gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(),
368 ram_in_page_dir_base_hi_f(pdb_addr_hi));
369}
370
371static void gp10b_remove_bar2_vm(struct gk20a *g)
372{
373 struct mm_gk20a *mm = &g->mm;
374
375 gp10b_replayable_pagefault_buffer_deinit(g);
376 gk20a_remove_vm(&mm->bar2.vm, &mm->bar2.inst_block);
377}
378
379
380void gp10b_init_mm(struct gpu_ops *gops)
381{
382 gm20b_init_mm(gops);
383 gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits;
384 gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw;
385 gops->mm.init_bar2_vm = gb10b_init_bar2_vm;
386 gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup;
387 gops->mm.get_iova_addr = gp10b_mm_iova_addr;
388 gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels;
389 gops->mm.init_pdb = gp10b_mm_init_pdb;
390 gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm;
391}
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
deleted file mode 100644
index 034944e05..000000000
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef MM_GP10B_H
15#define MM_GP10B_H
16
17#define NVGPU_MM_GET_IO_COHERENCE_BIT 35
18
19struct gpu_ops;
20
21void gp10b_init_mm(struct gpu_ops *gops);
22#endif
diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
deleted file mode 100644
index 27274e955..000000000
--- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
+++ /dev/null
@@ -1,737 +0,0 @@
1/*
2 * drivers/video/tegra/host/gk20a/platform_gk20a_tegra.c
3 *
4 * GK20A Tegra Platform Interface
5 *
6 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#include <linux/of_platform.h>
19#include <linux/nvhost.h>
20#include <linux/debugfs.h>
21#include <linux/tegra-powergate.h>
22#include <linux/platform_data/tegra_edp.h>
23#include <uapi/linux/nvgpu.h>
24#include <linux/dma-buf.h>
25#include <linux/nvmap.h>
26#include <linux/tegra_pm_domains.h>
27#include <linux/reset.h>
28#include <soc/tegra/tegra_bpmp.h>
29#include <linux/hashtable.h>
30#include "gk20a/platform_gk20a.h"
31#include "gk20a/gk20a.h"
32#include "gk20a/gk20a_scale.h"
33#include "platform_tegra.h"
34#include "gr_gp10b.h"
35#include "ltc_gp10b.h"
36#include "hw_gr_gp10b.h"
37#include "hw_ltc_gp10b.h"
38#include "gp10b_sysfs.h"
39#include <linux/platform/tegra/emc_bwmgr.h>
40
41#define GP10B_MAX_SUPPORTED_FREQS 11
42static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS];
43
44#define TEGRA_GP10B_BW_PER_FREQ 64
45#define TEGRA_DDR4_BW_PER_FREQ 16
46
47#define EMC_BW_RATIO (TEGRA_GP10B_BW_PER_FREQ / TEGRA_DDR4_BW_PER_FREQ)
48
49static struct {
50 char *name;
51 unsigned long default_rate;
52} tegra_gp10b_clocks[] = {
53 {"gpu", 1000000000},
54 {"gpu_sys", 204000000} };
55
56static void gr_gp10b_remove_sysfs(struct device *dev);
57
58/*
59 * gp10b_tegra_get_clocks()
60 *
61 * This function finds clocks in tegra platform and populates
62 * the clock information to gp10b platform data.
63 */
64
65static int gp10b_tegra_get_clocks(struct platform_device *pdev)
66{
67 struct gk20a_platform *platform = platform_get_drvdata(pdev);
68 struct gk20a *g = get_gk20a(pdev);
69 struct device *dev = dev_from_gk20a(g);
70 int i;
71
72 if (tegra_platform_is_linsim())
73 return 0;
74
75 platform->num_clks = 0;
76 for (i = 0; i < ARRAY_SIZE(tegra_gp10b_clocks); i++) {
77 long rate = tegra_gp10b_clocks[i].default_rate;
78 struct clk *c;
79
80 c = clk_get(dev, tegra_gp10b_clocks[i].name);
81 if (IS_ERR(c)) {
82 gk20a_err(&pdev->dev, "cannot get clock %s",
83 tegra_gp10b_clocks[i].name);
84 } else {
85 clk_set_rate(c, rate);
86 platform->clk[i] = c;
87 }
88 }
89 platform->num_clks = i;
90
91 return 0;
92}
93
94static void gp10b_tegra_scale_init(struct platform_device *pdev)
95{
96 struct gk20a_platform *platform = gk20a_get_platform(pdev);
97 struct gk20a_scale_profile *profile = platform->g->scale_profile;
98 struct tegra_bwmgr_client *bwmgr_handle;
99
100 bwmgr_handle = tegra_bwmgr_register(TEGRA_BWMGR_CLIENT_GPU);
101 if (!bwmgr_handle)
102 return;
103
104 profile->private_data = (void *)bwmgr_handle;
105}
106
107static void gp10b_tegra_scale_exit(struct platform_device *pdev)
108{
109 struct gk20a_platform *platform = gk20a_get_platform(pdev);
110 struct gk20a_scale_profile *profile = platform->g->scale_profile;
111
112 if (profile)
113 tegra_bwmgr_unregister(
114 (struct tegra_bwmgr_client *)profile->private_data);
115}
116
117
118static int gp10b_tegra_probe(struct platform_device *pdev)
119{
120 struct gk20a_platform *platform = gk20a_get_platform(pdev);
121 struct device_node *np = pdev->dev.of_node;
122 struct device_node *host1x_node;
123 struct platform_device *host1x_pdev;
124 const __be32 *host1x_ptr;
125
126 host1x_ptr = of_get_property(np, "nvidia,host1x", NULL);
127 if (!host1x_ptr) {
128 gk20a_err(&pdev->dev, "host1x device not available");
129 return -ENOSYS;
130 }
131
132 host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr));
133 host1x_pdev = of_find_device_by_node(host1x_node);
134 if (!host1x_pdev) {
135 gk20a_err(&pdev->dev, "host1x device not available");
136 return -ENOSYS;
137 }
138
139 platform->g->host1x_dev = host1x_pdev;
140 platform->bypass_smmu = !device_is_iommuable(&pdev->dev);
141 platform->disable_bigpage = platform->bypass_smmu;
142
143 platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
144 = false;
145 platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
146 = false;
147
148 platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
149 platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
150
151 platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_gfxp =
152 debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR,
153 platform->debugfs,
154 &platform->g->gr.t18x.ctx_vars.force_preemption_gfxp);
155
156 platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_cilp =
157 debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR,
158 platform->debugfs,
159 &platform->g->gr.t18x.ctx_vars.force_preemption_cilp);
160
161 platform->g->gr.t18x.ctx_vars.debugfs_dump_ctxsw_stats =
162 debugfs_create_bool("dump_ctxsw_stats_on_channel_close",
163 S_IRUGO|S_IWUSR,
164 platform->debugfs,
165 &platform->g->gr.t18x.
166 ctx_vars.dump_ctxsw_stats_on_channel_close);
167
168 gp10b_tegra_get_clocks(pdev);
169
170 return 0;
171}
172
173static int gp10b_tegra_late_probe(struct platform_device *pdev)
174{
175 /* Make gk20a power domain a subdomain of host1x */
176 nvhost_register_client_domain(dev_to_genpd(&pdev->dev));
177 /*Create GP10B specific sysfs*/
178 gp10b_create_sysfs(pdev);
179
180 /* Initialise tegra specific scaling quirks */
181 gp10b_tegra_scale_init(pdev);
182 return 0;
183}
184
185static int gp10b_tegra_remove(struct platform_device *pdev)
186{
187 /* remove gk20a power subdomain from host1x */
188 nvhost_unregister_client_domain(dev_to_genpd(&pdev->dev));
189 gr_gp10b_remove_sysfs(&pdev->dev);
190 /*Remove GP10B specific sysfs*/
191 gp10b_remove_sysfs(&pdev->dev);
192
193 /* deinitialise tegra specific scaling quirks */
194 gp10b_tegra_scale_exit(pdev);
195
196 return 0;
197
198}
199
200static bool gp10b_tegra_is_railgated(struct platform_device *pdev)
201{
202 bool ret = false;
203
204 if (tegra_bpmp_running())
205 ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU);
206
207 return ret;
208}
209
210static int gp10b_tegra_railgate(struct platform_device *pdev)
211{
212 struct gk20a_platform *platform = gk20a_get_platform(pdev);
213
214 if (tegra_bpmp_running() &&
215 tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) {
216 int i;
217 for (i = 0; i < platform->num_clks; i++) {
218 if (platform->clk[i])
219 clk_disable_unprepare(platform->clk[i]);
220 }
221 tegra_powergate_partition(TEGRA_POWERGATE_GPU);
222 }
223 return 0;
224}
225
226static int gp10b_tegra_unrailgate(struct platform_device *pdev)
227{
228 int ret = 0;
229 struct gk20a_platform *platform = gk20a_get_platform(pdev);
230
231 if (tegra_bpmp_running()) {
232 int i;
233 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU);
234 for (i = 0; i < platform->num_clks; i++) {
235 if (platform->clk[i])
236 clk_prepare_enable(platform->clk[i]);
237 }
238 }
239 return ret;
240}
241
242static int gp10b_tegra_suspend(struct device *dev)
243{
244 return 0;
245}
246
247static int gp10b_tegra_reset_assert(struct platform_device *dev)
248{
249 struct gk20a_platform *platform = gk20a_get_platform(dev);
250 int ret = 0;
251
252 if (!platform->reset_control)
253 return -EINVAL;
254
255 ret = reset_control_assert(platform->reset_control);
256
257 return ret;
258}
259
260static int gp10b_tegra_reset_deassert(struct platform_device *dev)
261{
262 struct gk20a_platform *platform = gk20a_get_platform(dev);
263 int ret = 0;
264
265 if (!platform->reset_control)
266 return -EINVAL;
267
268 ret = reset_control_deassert(platform->reset_control);
269
270 return ret;
271}
272
273static void gp10b_tegra_prescale(struct platform_device *pdev)
274{
275 struct gk20a *g = get_gk20a(pdev);
276 u32 avg = 0;
277
278 gk20a_dbg_fn("");
279
280 gk20a_pmu_load_norm(g, &avg);
281
282 gk20a_dbg_fn("done");
283}
284
285static void gp10b_tegra_postscale(struct platform_device *pdev,
286 unsigned long freq)
287{
288 struct gk20a_platform *platform = gk20a_get_platform(pdev);
289 struct gk20a_scale_profile *profile = platform->g->scale_profile;
290 struct gk20a *g = get_gk20a(pdev);
291 unsigned long emc_rate;
292
293 gk20a_dbg_fn("");
294 if (profile) {
295 emc_rate = (freq * EMC_BW_RATIO * g->emc3d_ratio) / 1000;
296
297 if (emc_rate > tegra_bwmgr_get_max_emc_rate())
298 emc_rate = tegra_bwmgr_get_max_emc_rate();
299
300 tegra_bwmgr_set_emc(
301 (struct tegra_bwmgr_client *)profile->private_data,
302 emc_rate, TEGRA_BWMGR_SET_EMC_FLOOR);
303 }
304 gk20a_dbg_fn("done");
305}
306
307static unsigned long gp10b_get_clk_rate(struct platform_device *dev)
308{
309 struct gk20a_platform *platform = gk20a_get_platform(dev);
310
311 return clk_get_rate(platform->clk[0]);
312
313}
314
315static long gp10b_round_clk_rate(struct platform_device *dev,
316 unsigned long rate)
317{
318 struct gk20a_platform *platform = gk20a_get_platform(dev);
319
320 return clk_round_rate(platform->clk[0], rate);
321}
322
323static int gp10b_set_clk_rate(struct platform_device *dev, unsigned long rate)
324{
325 struct gk20a_platform *platform = gk20a_get_platform(dev);
326
327 return clk_set_rate(platform->clk[0], rate);
328}
329
330static int gp10b_clk_get_freqs(struct platform_device *pdev,
331 unsigned long **freqs, int *num_freqs)
332{
333 struct gk20a_platform *platform = gk20a_get_platform(pdev);
334 unsigned long min_rate, max_rate, freq_step, rate;
335 int i;
336
337 min_rate = clk_round_rate(platform->clk[0], 0);
338 max_rate = clk_round_rate(platform->clk[0], (UINT_MAX - 1));
339 freq_step = (max_rate - min_rate)/(GP10B_MAX_SUPPORTED_FREQS - 1);
340 gk20a_dbg_info("min rate: %ld max rate: %ld freq step %ld\n",
341 min_rate, max_rate, freq_step);
342
343 for (i = 0; i < GP10B_MAX_SUPPORTED_FREQS; i++) {
344 rate = min_rate + i * freq_step;
345 gp10b_freq_table[i] = clk_round_rate(platform->clk[0], rate);
346 }
347 /* Fill freq table */
348 *freqs = gp10b_freq_table;
349 *num_freqs = GP10B_MAX_SUPPORTED_FREQS;
350 return 0;
351}
352
353struct gk20a_platform t18x_gpu_tegra_platform = {
354 .has_syncpoints = true,
355
356 /* power management configuration */
357 .railgate_delay = 500,
358 .clockgate_delay = 50,
359
360 /* power management configuration */
361 .can_railgate = true,
362 .enable_elpg = true,
363 .enable_blcg = true,
364 .enable_slcg = true,
365 .enable_elcg = true,
366 .enable_aelpg = true,
367
368 /* ptimer src frequency in hz*/
369 .ptimer_src_freq = 31250000,
370
371 .ch_wdt_timeout_ms = 5000,
372
373 .probe = gp10b_tegra_probe,
374 .late_probe = gp10b_tegra_late_probe,
375 .remove = gp10b_tegra_remove,
376
377 /* power management callbacks */
378 .suspend = gp10b_tegra_suspend,
379 .railgate = gp10b_tegra_railgate,
380 .unrailgate = gp10b_tegra_unrailgate,
381 .is_railgated = gp10b_tegra_is_railgated,
382
383 .busy = gk20a_tegra_busy,
384 .idle = gk20a_tegra_idle,
385
386 .dump_platform_dependencies = gk20a_tegra_debug_dump,
387
388 .default_big_page_size = SZ_64K,
389
390 .has_cde = true,
391
392 .clk_get_rate = gp10b_get_clk_rate,
393 .clk_round_rate = gp10b_round_clk_rate,
394 .clk_set_rate = gp10b_set_clk_rate,
395 .get_clk_freqs = gp10b_clk_get_freqs,
396
397 /* frequency scaling configuration */
398 .prescale = gp10b_tegra_prescale,
399 .postscale = gp10b_tegra_postscale,
400
401 .devfreq_governor = "nvhost_podgov",
402 .qos_id = PM_QOS_GPU_FREQ_MIN,
403
404 .secure_alloc = gk20a_tegra_secure_alloc,
405 .secure_page_alloc = gk20a_tegra_secure_page_alloc,
406
407 .reset_assert = gp10b_tegra_reset_assert,
408 .reset_deassert = gp10b_tegra_reset_deassert,
409
410 .force_reset_in_do_idle = true,
411};
412
413
414#define ECC_STAT_NAME_MAX_SIZE 100
415
416
417static DEFINE_HASHTABLE(ecc_hash_table, 5);
418
419static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array;
420static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array;
421
422static struct device_attribute *dev_attr_sm_shm_ecc_sec_count_array;
423static struct device_attribute *dev_attr_sm_shm_ecc_sed_count_array;
424static struct device_attribute *dev_attr_sm_shm_ecc_ded_count_array;
425
426static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe0_count_array;
427static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe0_count_array;
428static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe0_count_array;
429static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe0_count_array;
430static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe1_count_array;
431static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe1_count_array;
432static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe1_count_array;
433static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe1_count_array;
434
435static struct device_attribute *dev_attr_l2_ecc_sec_count_array;
436static struct device_attribute *dev_attr_l2_ecc_ded_count_array;
437
438
439static u32 gen_ecc_hash_key(char *str)
440{
441 int i = 0;
442 u32 hash_key = 0;
443
444 while (str[i]) {
445 hash_key += (u32)(str[i]);
446 i++;
447 };
448
449 return hash_key;
450}
451
452static ssize_t ecc_stat_show(struct device *dev,
453 struct device_attribute *attr,
454 char *buf)
455{
456 const char *ecc_stat_full_name = attr->attr.name;
457 const char *ecc_stat_base_name;
458 unsigned int hw_unit;
459 struct ecc_stat *ecc_stat;
460 u32 hash_key;
461
462 if (sscanf(ecc_stat_full_name, "ltc%u", &hw_unit) == 1) {
463 ecc_stat_base_name = &(ecc_stat_full_name[strlen("ltc0_")]);
464 } else if (sscanf(ecc_stat_full_name, "gpc0_tpc%u", &hw_unit) == 1) {
465 ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_tpc0_")]);
466 } else {
467 return snprintf(buf,
468 PAGE_SIZE,
469 "Error: Invalid ECC stat name!\n");
470 }
471
472 hash_key = gen_ecc_hash_key((char *)ecc_stat_base_name);
473 hash_for_each_possible(ecc_hash_table,
474 ecc_stat,
475 hash_node,
476 hash_key) {
477 if (!strcmp(ecc_stat_full_name, ecc_stat->names[hw_unit]))
478 return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stat->counters[hw_unit]);
479 }
480
481 return snprintf(buf, PAGE_SIZE, "Error: No ECC stat found!\n");
482}
483
484static int ecc_stat_create(struct platform_device *dev,
485 int is_l2,
486 char *ecc_stat_name,
487 struct ecc_stat *ecc_stat,
488 struct device_attribute *dev_attr_array)
489{
490 int error = 0;
491 struct gk20a *g = get_gk20a(dev);
492 int num_hw_units = 0;
493 int hw_unit = 0;
494 u32 hash_key = 0;
495
496 if (is_l2)
497 num_hw_units = g->ltc_count;
498 else
499 num_hw_units = g->gr.tpc_count;
500
501 /* Allocate arrays */
502 dev_attr_array = kzalloc(sizeof(struct device_attribute) * num_hw_units, GFP_KERNEL);
503 ecc_stat->counters = kzalloc(sizeof(u32) * num_hw_units, GFP_KERNEL);
504 ecc_stat->names = kzalloc(sizeof(char *) * num_hw_units, GFP_KERNEL);
505 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
506 ecc_stat->names[hw_unit] = kzalloc(sizeof(char) * ECC_STAT_NAME_MAX_SIZE, GFP_KERNEL);
507 }
508
509 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
510 /* Fill in struct device_attribute members */
511 if (is_l2)
512 snprintf(ecc_stat->names[hw_unit],
513 ECC_STAT_NAME_MAX_SIZE,
514 "ltc%d_%s",
515 hw_unit,
516 ecc_stat_name);
517 else
518 snprintf(ecc_stat->names[hw_unit],
519 ECC_STAT_NAME_MAX_SIZE,
520 "gpc0_tpc%d_%s",
521 hw_unit,
522 ecc_stat_name);
523 dev_attr_array[hw_unit].attr.name = ecc_stat->names[hw_unit];
524 dev_attr_array[hw_unit].attr.mode = VERIFY_OCTAL_PERMISSIONS(S_IRUGO);
525 dev_attr_array[hw_unit].show = ecc_stat_show;
526 dev_attr_array[hw_unit].store = NULL;
527
528 /* Create sysfs file */
529 error |= device_create_file(&dev->dev,
530 &dev_attr_array[hw_unit]);
531 }
532
533 /* Add hash table entry */
534 hash_key = gen_ecc_hash_key(ecc_stat_name);
535 hash_add(ecc_hash_table,
536 &ecc_stat->hash_node,
537 hash_key);
538
539 return error;
540}
541
542static void ecc_stat_remove(struct device *dev,
543 int is_l2,
544 struct ecc_stat *ecc_stat,
545 struct device_attribute *dev_attr_array)
546{
547 struct platform_device *ndev = to_platform_device(dev);
548 struct gk20a *g = get_gk20a(ndev);
549 int num_hw_units = 0;
550 int hw_unit = 0;
551
552 if (is_l2)
553 num_hw_units = g->ltc_count;
554 else
555 num_hw_units = g->gr.tpc_count;
556
557 /* Remove sysfs files */
558 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
559 device_remove_file(dev, &dev_attr_array[hw_unit]);
560 }
561
562 /* Remove hash table entry */
563 hash_del(&ecc_stat->hash_node);
564
565 /* Free arrays */
566 kfree(ecc_stat->counters);
567 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
568 kfree(ecc_stat->names[hw_unit]);
569 }
570 kfree(ecc_stat->names);
571 kfree(dev_attr_array);
572}
573
574void gr_gp10b_create_sysfs(struct platform_device *dev)
575{
576 int error = 0;
577 struct gk20a *g = get_gk20a(dev);
578
579 /* This stat creation function is called on GR init. GR can get
580 initialized multiple times but we only need to create the ECC
581 stats once. Therefore, add the following check to avoid
582 creating duplicate stat sysfs nodes. */
583 if (g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters != NULL)
584 return;
585
586 error |= ecc_stat_create(dev,
587 0,
588 "sm_lrf_ecc_single_err_count",
589 &g->gr.t18x.ecc_stats.sm_lrf_single_err_count,
590 dev_attr_sm_lrf_ecc_single_err_count_array);
591 error |= ecc_stat_create(dev,
592 0,
593 "sm_lrf_ecc_double_err_count",
594 &g->gr.t18x.ecc_stats.sm_lrf_double_err_count,
595 dev_attr_sm_lrf_ecc_double_err_count_array);
596
597 error |= ecc_stat_create(dev,
598 0,
599 "sm_shm_ecc_sec_count",
600 &g->gr.t18x.ecc_stats.sm_shm_sec_count,
601 dev_attr_sm_shm_ecc_sec_count_array);
602 error |= ecc_stat_create(dev,
603 0,
604 "sm_shm_ecc_sed_count",
605 &g->gr.t18x.ecc_stats.sm_shm_sed_count,
606 dev_attr_sm_shm_ecc_sed_count_array);
607 error |= ecc_stat_create(dev,
608 0,
609 "sm_shm_ecc_ded_count",
610 &g->gr.t18x.ecc_stats.sm_shm_ded_count,
611 dev_attr_sm_shm_ecc_ded_count_array);
612
613 error |= ecc_stat_create(dev,
614 0,
615 "tex_ecc_total_sec_pipe0_count",
616 &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count,
617 dev_attr_tex_ecc_total_sec_pipe0_count_array);
618 error |= ecc_stat_create(dev,
619 0,
620 "tex_ecc_total_ded_pipe0_count",
621 &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count,
622 dev_attr_tex_ecc_total_ded_pipe0_count_array);
623 error |= ecc_stat_create(dev,
624 0,
625 "tex_ecc_unique_sec_pipe0_count",
626 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count,
627 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
628 error |= ecc_stat_create(dev,
629 0,
630 "tex_ecc_unique_ded_pipe0_count",
631 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count,
632 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
633 error |= ecc_stat_create(dev,
634 0,
635 "tex_ecc_total_sec_pipe1_count",
636 &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count,
637 dev_attr_tex_ecc_total_sec_pipe1_count_array);
638 error |= ecc_stat_create(dev,
639 0,
640 "tex_ecc_total_ded_pipe1_count",
641 &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count,
642 dev_attr_tex_ecc_total_ded_pipe1_count_array);
643 error |= ecc_stat_create(dev,
644 0,
645 "tex_ecc_unique_sec_pipe1_count",
646 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count,
647 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
648 error |= ecc_stat_create(dev,
649 0,
650 "tex_ecc_unique_ded_pipe1_count",
651 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count,
652 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
653
654 error |= ecc_stat_create(dev,
655 1,
656 "lts0_ecc_sec_count",
657 &g->gr.t18x.ecc_stats.l2_sec_count,
658 dev_attr_l2_ecc_sec_count_array);
659 error |= ecc_stat_create(dev,
660 1,
661 "lts0_ecc_ded_count",
662 &g->gr.t18x.ecc_stats.l2_ded_count,
663 dev_attr_l2_ecc_ded_count_array);
664
665 if (error)
666 dev_err(&dev->dev, "Failed to create sysfs attributes!\n");
667}
668
669static void gr_gp10b_remove_sysfs(struct device *dev)
670{
671 struct platform_device *ndev = to_platform_device(dev);
672 struct gk20a *g = get_gk20a(ndev);
673
674 ecc_stat_remove(dev,
675 0,
676 &g->gr.t18x.ecc_stats.sm_lrf_single_err_count,
677 dev_attr_sm_lrf_ecc_single_err_count_array);
678 ecc_stat_remove(dev,
679 0,
680 &g->gr.t18x.ecc_stats.sm_lrf_double_err_count,
681 dev_attr_sm_lrf_ecc_double_err_count_array);
682
683 ecc_stat_remove(dev,
684 0,
685 &g->gr.t18x.ecc_stats.sm_shm_sec_count,
686 dev_attr_sm_shm_ecc_sec_count_array);
687 ecc_stat_remove(dev,
688 0,
689 &g->gr.t18x.ecc_stats.sm_shm_sed_count,
690 dev_attr_sm_shm_ecc_sed_count_array);
691 ecc_stat_remove(dev,
692 0,
693 &g->gr.t18x.ecc_stats.sm_shm_ded_count,
694 dev_attr_sm_shm_ecc_ded_count_array);
695
696 ecc_stat_remove(dev,
697 0,
698 &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count,
699 dev_attr_tex_ecc_total_sec_pipe0_count_array);
700 ecc_stat_remove(dev,
701 0,
702 &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count,
703 dev_attr_tex_ecc_total_ded_pipe0_count_array);
704 ecc_stat_remove(dev,
705 0,
706 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count,
707 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
708 ecc_stat_remove(dev,
709 0,
710 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count,
711 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
712 ecc_stat_remove(dev,
713 0,
714 &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count,
715 dev_attr_tex_ecc_total_sec_pipe1_count_array);
716 ecc_stat_remove(dev,
717 0,
718 &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count,
719 dev_attr_tex_ecc_total_ded_pipe1_count_array);
720 ecc_stat_remove(dev,
721 0,
722 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count,
723 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
724 ecc_stat_remove(dev,
725 0,
726 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count,
727 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
728
729 ecc_stat_remove(dev,
730 1,
731 &g->gr.t18x.ecc_stats.l2_sec_count,
732 dev_attr_l2_ecc_sec_count_array);
733 ecc_stat_remove(dev,
734 1,
735 &g->gr.t18x.ecc_stats.l2_ded_count,
736 dev_attr_l2_ecc_ded_count_array);
737}
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
deleted file mode 100644
index 6a7048130..000000000
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
+++ /dev/null
@@ -1,419 +0,0 @@
1/*
2 * GP10B PMU
3 *
4 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/delay.h> /* for udelay */
17#include <linux/tegra-fuse.h>
18#include "gk20a/gk20a.h"
19#include "gk20a/pmu_gk20a.h"
20#include "gm20b/acr_gm20b.h"
21#include "gm20b/pmu_gm20b.h"
22
23#include "pmu_gp10b.h"
24#include "hw_pwr_gp10b.h"
25#include "gp10b_sysfs.h"
26
27#define gp10b_dbg_pmu(fmt, arg...) \
28 gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
29/*!
30 * Structure/object which single register write need to be done during PG init
31 * sequence to set PROD values.
32 */
33struct pg_init_sequence_list {
34 u32 regaddr;
35 u32 writeval;
36};
37
38/* PROD settings for ELPG sequencing registers*/
39static struct pg_init_sequence_list _pginitseq_gp10b[] = {
40 {0x0010ab10, 0x0000868B} ,
41 {0x0010e118, 0x8590848F} ,
42 {0x0010e000, 0} ,
43 {0x0010e06c, 0x000000A3} ,
44 {0x0010e06c, 0x000000A0} ,
45 {0x0010e06c, 0x00000095} ,
46 {0x0010e06c, 0x000000A6} ,
47 {0x0010e06c, 0x0000008C} ,
48 {0x0010e06c, 0x00000080} ,
49 {0x0010e06c, 0x00000081} ,
50 {0x0010e06c, 0x00000087} ,
51 {0x0010e06c, 0x00000088} ,
52 {0x0010e06c, 0x0000008D} ,
53 {0x0010e06c, 0x00000082} ,
54 {0x0010e06c, 0x00000083} ,
55 {0x0010e06c, 0x00000089} ,
56 {0x0010e06c, 0x0000008A} ,
57 {0x0010e06c, 0x000000A2} ,
58 {0x0010e06c, 0x00000097} ,
59 {0x0010e06c, 0x00000092} ,
60 {0x0010e06c, 0x00000099} ,
61 {0x0010e06c, 0x0000009B} ,
62 {0x0010e06c, 0x0000009D} ,
63 {0x0010e06c, 0x0000009F} ,
64 {0x0010e06c, 0x000000A1} ,
65 {0x0010e06c, 0x00000096} ,
66 {0x0010e06c, 0x00000091} ,
67 {0x0010e06c, 0x00000098} ,
68 {0x0010e06c, 0x0000009A} ,
69 {0x0010e06c, 0x0000009C} ,
70 {0x0010e06c, 0x0000009E} ,
71 {0x0010ab14, 0x00000000} ,
72 {0x0010e024, 0x00000000} ,
73 {0x0010e028, 0x00000000} ,
74 {0x0010e11c, 0x00000000} ,
75 {0x0010ab1c, 0x140B0BFF} ,
76 {0x0010e020, 0x0E2626FF} ,
77 {0x0010e124, 0x251010FF} ,
78 {0x0010ab20, 0x89abcdef} ,
79 {0x0010ab24, 0x00000000} ,
80 {0x0010e02c, 0x89abcdef} ,
81 {0x0010e030, 0x00000000} ,
82 {0x0010e128, 0x89abcdef} ,
83 {0x0010e12c, 0x00000000} ,
84 {0x0010ab28, 0x7FFFFFFF} ,
85 {0x0010ab2c, 0x70000000} ,
86 {0x0010e034, 0x7FFFFFFF} ,
87 {0x0010e038, 0x70000000} ,
88 {0x0010e130, 0x7FFFFFFF} ,
89 {0x0010e134, 0x70000000} ,
90 {0x0010ab30, 0x00000000} ,
91 {0x0010ab34, 0x00000001} ,
92 {0x00020004, 0x00000000} ,
93 {0x0010e138, 0x00000000} ,
94 {0x0010e040, 0x00000000} ,
95 {0x0010e168, 0x00000000} ,
96 {0x0010e114, 0x0000A5A4} ,
97 {0x0010e110, 0x00000000} ,
98 {0x0010e10c, 0x8590848F} ,
99 {0x0010e05c, 0x00000000} ,
100 {0x0010e044, 0x00000000} ,
101 {0x0010a644, 0x0000868B} ,
102 {0x0010a648, 0x00000000} ,
103 {0x0010a64c, 0x00829493} ,
104 {0x0010a650, 0x00000000} ,
105 {0x0010e000, 0} ,
106 {0x0010e068, 0x000000A3} ,
107 {0x0010e068, 0x000000A0} ,
108 {0x0010e068, 0x00000095} ,
109 {0x0010e068, 0x000000A6} ,
110 {0x0010e068, 0x0000008C} ,
111 {0x0010e068, 0x00000080} ,
112 {0x0010e068, 0x00000081} ,
113 {0x0010e068, 0x00000087} ,
114 {0x0010e068, 0x00000088} ,
115 {0x0010e068, 0x0000008D} ,
116 {0x0010e068, 0x00000082} ,
117 {0x0010e068, 0x00000083} ,
118 {0x0010e068, 0x00000089} ,
119 {0x0010e068, 0x0000008A} ,
120 {0x0010e068, 0x000000A2} ,
121 {0x0010e068, 0x00000097} ,
122 {0x0010e068, 0x00000092} ,
123 {0x0010e068, 0x00000099} ,
124 {0x0010e068, 0x0000009B} ,
125 {0x0010e068, 0x0000009D} ,
126 {0x0010e068, 0x0000009F} ,
127 {0x0010e068, 0x000000A1} ,
128 {0x0010e068, 0x00000096} ,
129 {0x0010e068, 0x00000091} ,
130 {0x0010e068, 0x00000098} ,
131 {0x0010e068, 0x0000009A} ,
132 {0x0010e068, 0x0000009C} ,
133 {0x0010e068, 0x0000009E} ,
134 {0x0010e000, 0} ,
135 {0x0010e004, 0x0000008E},
136};
137
138static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
139 u32 flags)
140{
141 struct pmu_gk20a *pmu = &g->pmu;
142 struct pmu_cmd cmd;
143 u32 seq;
144
145 gk20a_dbg_fn("");
146
147 gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone);
148 if (g->ops.pmu.lspmuwprinitdone) {
149 /* send message to load FECS falcon */
150 memset(&cmd, 0, sizeof(struct pmu_cmd));
151 cmd.hdr.unit_id = PMU_UNIT_ACR;
152 cmd.hdr.size = PMU_CMD_HDR_SIZE +
153 sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons);
154 cmd.cmd.acr.boot_falcons.cmd_type =
155 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS;
156 cmd.cmd.acr.boot_falcons.flags = flags;
157 cmd.cmd.acr.boot_falcons.falconidmask =
158 falconidmask;
159 cmd.cmd.acr.boot_falcons.usevamask = 0;
160 cmd.cmd.acr.boot_falcons.wprvirtualbase.lo =
161 u64_lo32(g->pmu.wpr_buf.gpu_va);
162 cmd.cmd.acr.boot_falcons.wprvirtualbase.hi =
163 u64_hi32(g->pmu.wpr_buf.gpu_va);
164 gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
165 falconidmask);
166 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
167 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
168 }
169
170 gk20a_dbg_fn("done");
171 return;
172}
173
174static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
175{
176 u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
177
178 /* GM20B PMU supports loading FECS and GPCCS only */
179 if (falconidmask == 0)
180 return -EINVAL;
181 if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
182 (1 << LSF_FALCON_ID_GPCCS)))
183 return -EINVAL;
184 g->ops.pmu.lsfloadedfalconid = 0;
185 /* check whether pmu is ready to bootstrap lsf if not wait for it */
186 if (!g->ops.pmu.lspmuwprinitdone) {
187 pmu_wait_message_cond(&g->pmu,
188 gk20a_get_gr_idle_timeout(g),
189 &g->ops.pmu.lspmuwprinitdone, 1);
190 /* check again if it still not ready indicate an error */
191 if (!g->ops.pmu.lspmuwprinitdone) {
192 gk20a_err(dev_from_gk20a(g),
193 "PMU not ready to load LSF");
194 return -ETIMEDOUT;
195 }
196 }
197 /* load falcon(s) */
198 gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
199 pmu_wait_message_cond(&g->pmu,
200 gk20a_get_gr_idle_timeout(g),
201 &g->ops.pmu.lsfloadedfalconid, falconidmask);
202 if (g->ops.pmu.lsfloadedfalconid != falconidmask)
203 return -ETIMEDOUT;
204 return 0;
205}
206
207static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg,
208 void *param, u32 handle, u32 status)
209{
210 gk20a_dbg_fn("");
211
212 if (status != 0) {
213 gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted");
214 /* TBD: disable ELPG */
215 return;
216 }
217
218 gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n",
219 msg->msg.pg.msg_type);
220
221 return;
222}
223
224static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask)
225{
226 struct pmu_gk20a *pmu = &g->pmu;
227 struct pmu_cmd cmd;
228 u32 seq;
229
230 memset(&cmd, 0, sizeof(struct pmu_cmd));
231 cmd.hdr.unit_id = PMU_UNIT_PG;
232 cmd.hdr.size = PMU_CMD_HDR_SIZE +
233 sizeof(struct pmu_pg_cmd_gr_init_param);
234 cmd.cmd.pg.gr_init_param.cmd_type =
235 PMU_PG_CMD_ID_PG_PARAM;
236 cmd.cmd.pg.gr_init_param.sub_cmd_id =
237 PMU_PG_PARAM_CMD_GR_INIT_PARAM;
238 cmd.cmd.pg.gr_init_param.featuremask =
239 grfeaturemask;
240
241 gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask);
242 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
243 pmu_handle_gr_param_msg, pmu, &seq, ~0);
244
245 return 0;
246}
247static void gp10b_pmu_elpg_statistics(struct gk20a *g,
248 u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt)
249{
250 struct pmu_gk20a *pmu = &g->pmu;
251 struct pmu_pg_stats_v1 stats;
252
253 pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset,
254 (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0);
255
256 *ingating_time = stats.total_sleep_timeus;
257 *ungating_time = stats.total_nonsleep_timeus;
258 *gating_cnt = stats.entry_count;
259}
260
261static int gp10b_pmu_setup_elpg(struct gk20a *g)
262{
263 int ret = 0;
264 u32 reg_writes;
265 u32 index;
266
267 gk20a_dbg_fn("");
268
269 if (g->elpg_enabled) {
270 reg_writes = ((sizeof(_pginitseq_gp10b) /
271 sizeof((_pginitseq_gp10b)[0])));
272 /* Initialize registers with production values*/
273 for (index = 0; index < reg_writes; index++) {
274 gk20a_writel(g, _pginitseq_gp10b[index].regaddr,
275 _pginitseq_gp10b[index].writeval);
276 }
277 }
278
279 gk20a_dbg_fn("done");
280 return ret;
281}
282
283static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
284{
285 gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
286 addr);
287 gk20a_writel(g, pwr_falcon_dmatrfbase1_r(),
288 0x0);
289}
290
291static int gp10b_init_pmu_setup_hw1(struct gk20a *g)
292{
293 struct pmu_gk20a *pmu = &g->pmu;
294 int err;
295
296 gk20a_dbg_fn("");
297
298 mutex_lock(&pmu->isr_mutex);
299 pmu_reset(pmu);
300 pmu->isr_enabled = true;
301 mutex_unlock(&pmu->isr_mutex);
302
303 /* setup apertures - virtual */
304 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
305 pwr_fbif_transcfg_mem_type_virtual_f());
306 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
307 pwr_fbif_transcfg_mem_type_virtual_f());
308
309 /* setup apertures - physical */
310 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
311 pwr_fbif_transcfg_mem_type_physical_f() |
312 pwr_fbif_transcfg_target_local_fb_f());
313 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
314 pwr_fbif_transcfg_mem_type_physical_f() |
315 pwr_fbif_transcfg_target_coherent_sysmem_f());
316 gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
317 pwr_fbif_transcfg_mem_type_physical_f() |
318 pwr_fbif_transcfg_target_noncoherent_sysmem_f());
319
320 err = pmu_bootstrap(pmu);
321 if (err)
322 return err;
323
324 gk20a_dbg_fn("done");
325 return 0;
326
327}
328
329static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg,
330 void *param, u32 handle, u32 status)
331{
332 struct pmu_gk20a *pmu = &g->pmu;
333 struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc =
334 &msg->msg.lrf_tex_ltc_dram.en_dis;
335 gk20a_dbg_fn("");
336
337 if (status != 0) {
338 gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted");
339 return;
340 }
341 if (msg->msg.lrf_tex_ltc_dram.msg_type !=
342 PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) {
343 gk20a_err(dev_from_gk20a(g),
344 "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd");
345 return;
346 } else if (ecc->pmu_status != 0) {
347 gk20a_err(dev_from_gk20a(g),
348 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x",
349 ecc->pmu_status);
350 gk20a_err(dev_from_gk20a(g),
351 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x",
352 ecc->en_fail_mask);
353 gk20a_err(dev_from_gk20a(g),
354 "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x",
355 ecc->dis_fail_mask);
356 } else
357 pmu->override_done = 1;
358 gk20a_dbg_fn("done");
359}
360
361static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask)
362{
363 struct pmu_gk20a *pmu = &g->pmu;
364 struct pmu_cmd cmd;
365 u32 seq;
366 int status;
367 gk20a_dbg_fn("");
368
369 if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) {
370 gk20a_err(dev_from_gk20a(g), "Board not ECC capable");
371 return -1;
372 }
373 if (!(g->acr.capabilities &
374 ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) {
375 gk20a_err(dev_from_gk20a(g), "check ACR capabilities");
376 return -1;
377 }
378 memset(&cmd, 0, sizeof(struct pmu_cmd));
379 cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE;
380 cmd.hdr.size = PMU_CMD_HDR_SIZE +
381 sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis);
382 cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type =
383 PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS;
384 cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff);
385
386 gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC");
387 pmu->override_done = 0;
388 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ,
389 pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0);
390 if (status)
391 gk20a_err(dev_from_gk20a(g), "ECC override failed");
392 else
393 pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g),
394 &pmu->override_done, 1);
395 gk20a_dbg_fn("done");
396 return status;
397}
398
399void gp10b_init_pmu_ops(struct gpu_ops *gops)
400{
401 if (gops->privsecurity) {
402 gm20b_init_secure_pmu(gops);
403 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
404 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
405 } else {
406 gk20a_init_pmu_ops(gops);
407 gops->pmu.load_lsfalcon_ucode = NULL;
408 gops->pmu.init_wpr_region = NULL;
409 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
410 }
411 gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg;
412 gops->pmu.lspmuwprinitdone = false;
413 gops->pmu.fecsbootstrapdone = false;
414 gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
415 gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics;
416 gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init;
417 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd =
418 send_ecc_overide_en_dis_cmd;
419}
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
deleted file mode 100644
index f61f6a93c..000000000
--- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * GP10B PMU
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef __PMU_GP10B_H_
17#define __PMU_GP10B_H_
18
19void gp10b_init_pmu_ops(struct gpu_ops *gops);
20
21#endif /*__PMU_GP10B_H_*/
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
deleted file mode 100644
index 8934c3248..000000000
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c
+++ /dev/null
@@ -1,505 +0,0 @@
1/*
2 * Tegra GK20A GPU Debugger Driver Register Ops
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/bsearch.h>
22#include <uapi/linux/nvgpu.h>
23
24#include "gk20a/gk20a.h"
25#include "gk20a/dbg_gpu_gk20a.h"
26#include "gk20a/regops_gk20a.h"
27#include "regops_gp10b.h"
28
29static const struct regop_offset_range gp10b_global_whitelist_ranges[] = {
30 { 0x000004f0, 1},
31 { 0x00001a00, 3},
32 { 0x00002800, 128},
33 { 0x00009400, 1},
34 { 0x00009410, 1},
35 { 0x00009480, 1},
36 { 0x00020200, 24},
37 { 0x00021c00, 4},
38 { 0x00021c14, 3},
39 { 0x00021c24, 1},
40 { 0x00021c2c, 69},
41 { 0x00021d44, 1},
42 { 0x00021d4c, 1},
43 { 0x00021d54, 1},
44 { 0x00021d5c, 1},
45 { 0x00021d64, 2},
46 { 0x00021d70, 16},
47 { 0x00022430, 7},
48 { 0x00022450, 1},
49 { 0x0002245c, 1},
50 { 0x00070000, 5},
51 { 0x000884e0, 1},
52 { 0x0008e00c, 1},
53 { 0x00100c18, 3},
54 { 0x00100c84, 1},
55 { 0x0010a0a8, 1},
56 { 0x0010a4f0, 1},
57 { 0x0013cc14, 1},
58 { 0x00140028, 1},
59 { 0x00140280, 1},
60 { 0x001402a0, 1},
61 { 0x00140350, 1},
62 { 0x00140480, 1},
63 { 0x001404a0, 1},
64 { 0x00140550, 1},
65 { 0x00142028, 1},
66 { 0x00142280, 1},
67 { 0x001422a0, 1},
68 { 0x00142350, 1},
69 { 0x00142480, 1},
70 { 0x001424a0, 1},
71 { 0x00142550, 1},
72 { 0x0017e028, 1},
73 { 0x0017e280, 1},
74 { 0x0017e294, 1},
75 { 0x0017e29c, 2},
76 { 0x0017e2ac, 1},
77 { 0x0017e350, 1},
78 { 0x0017e39c, 1},
79 { 0x0017e480, 1},
80 { 0x0017e4a0, 1},
81 { 0x0017e550, 1},
82 { 0x00180040, 41},
83 { 0x001800ec, 10},
84 { 0x00180240, 41},
85 { 0x001802ec, 10},
86 { 0x00180440, 41},
87 { 0x001804ec, 10},
88 { 0x00180640, 41},
89 { 0x001806ec, 10},
90 { 0x00180840, 41},
91 { 0x001808ec, 10},
92 { 0x00180a40, 41},
93 { 0x00180aec, 10},
94 { 0x00180c40, 41},
95 { 0x00180cec, 10},
96 { 0x00180e40, 41},
97 { 0x00180eec, 10},
98 { 0x001a0040, 41},
99 { 0x001a00ec, 10},
100 { 0x001a0240, 41},
101 { 0x001a02ec, 10},
102 { 0x001a0440, 41},
103 { 0x001a04ec, 10},
104 { 0x001a0640, 41},
105 { 0x001a06ec, 10},
106 { 0x001a0840, 41},
107 { 0x001a08ec, 10},
108 { 0x001a0a40, 41},
109 { 0x001a0aec, 10},
110 { 0x001a0c40, 41},
111 { 0x001a0cec, 10},
112 { 0x001a0e40, 41},
113 { 0x001a0eec, 10},
114 { 0x001b0040, 41},
115 { 0x001b00ec, 10},
116 { 0x001b0240, 41},
117 { 0x001b02ec, 10},
118 { 0x001b0440, 41},
119 { 0x001b04ec, 10},
120 { 0x001b0640, 41},
121 { 0x001b06ec, 10},
122 { 0x001b0840, 41},
123 { 0x001b08ec, 10},
124 { 0x001b0a40, 41},
125 { 0x001b0aec, 10},
126 { 0x001b0c40, 41},
127 { 0x001b0cec, 10},
128 { 0x001b0e40, 41},
129 { 0x001b0eec, 10},
130 { 0x001b4000, 1},
131 { 0x001b4008, 1},
132 { 0x001b4010, 3},
133 { 0x001b4020, 3},
134 { 0x001b4030, 3},
135 { 0x001b4040, 3},
136 { 0x001b4050, 3},
137 { 0x001b4060, 4},
138 { 0x001b4074, 7},
139 { 0x001b4094, 3},
140 { 0x001b40a4, 1},
141 { 0x001b4100, 6},
142 { 0x001b4124, 2},
143 { 0x001b8000, 1},
144 { 0x001b8008, 1},
145 { 0x001b8010, 3},
146 { 0x001bc000, 1},
147 { 0x001bc008, 1},
148 { 0x001bc010, 3},
149 { 0x001be000, 1},
150 { 0x001be008, 1},
151 { 0x001be010, 3},
152 { 0x00400500, 1},
153 { 0x0040415c, 1},
154 { 0x00404468, 1},
155 { 0x00404498, 1},
156 { 0x00405800, 1},
157 { 0x00405840, 2},
158 { 0x00405850, 1},
159 { 0x00405908, 1},
160 { 0x00405b40, 1},
161 { 0x00405b50, 1},
162 { 0x00406024, 5},
163 { 0x00407010, 1},
164 { 0x00407808, 1},
165 { 0x0040803c, 1},
166 { 0x00408804, 1},
167 { 0x0040880c, 1},
168 { 0x00408900, 2},
169 { 0x00408910, 1},
170 { 0x00408944, 1},
171 { 0x00408984, 1},
172 { 0x004090a8, 1},
173 { 0x004098a0, 1},
174 { 0x00409b00, 1},
175 { 0x0041000c, 1},
176 { 0x00410110, 1},
177 { 0x00410184, 1},
178 { 0x0041040c, 1},
179 { 0x00410510, 1},
180 { 0x00410584, 1},
181 { 0x00418000, 1},
182 { 0x00418008, 1},
183 { 0x00418380, 2},
184 { 0x00418400, 2},
185 { 0x004184a0, 1},
186 { 0x00418604, 1},
187 { 0x00418680, 1},
188 { 0x00418704, 1},
189 { 0x00418714, 1},
190 { 0x00418800, 1},
191 { 0x0041881c, 1},
192 { 0x00418830, 1},
193 { 0x00418884, 1},
194 { 0x004188b0, 1},
195 { 0x004188c8, 3},
196 { 0x004188fc, 1},
197 { 0x00418b04, 1},
198 { 0x00418c04, 1},
199 { 0x00418c10, 8},
200 { 0x00418c88, 1},
201 { 0x00418d00, 1},
202 { 0x00418e00, 1},
203 { 0x00418e08, 1},
204 { 0x00418e34, 1},
205 { 0x00418e40, 4},
206 { 0x00418e58, 16},
207 { 0x00418f08, 1},
208 { 0x00419000, 1},
209 { 0x0041900c, 1},
210 { 0x00419018, 1},
211 { 0x00419854, 1},
212 { 0x00419864, 1},
213 { 0x00419a04, 2},
214 { 0x00419a14, 1},
215 { 0x00419ab0, 1},
216 { 0x00419ab8, 3},
217 { 0x00419c0c, 1},
218 { 0x00419c8c, 2},
219 { 0x00419d00, 1},
220 { 0x00419d08, 2},
221 { 0x00419e00, 11},
222 { 0x00419e34, 2},
223 { 0x00419e44, 11},
224 { 0x00419e74, 10},
225 { 0x00419ea4, 1},
226 { 0x00419eac, 2},
227 { 0x00419ee8, 1},
228 { 0x00419ef0, 28},
229 { 0x00419f70, 1},
230 { 0x00419f78, 2},
231 { 0x00419f98, 2},
232 { 0x00419fdc, 1},
233 { 0x0041a02c, 2},
234 { 0x0041a0a0, 1},
235 { 0x0041a0a8, 1},
236 { 0x0041a890, 2},
237 { 0x0041a8a0, 3},
238 { 0x0041a8b0, 2},
239 { 0x0041b014, 1},
240 { 0x0041b0cc, 1},
241 { 0x0041b1dc, 1},
242 { 0x0041be0c, 3},
243 { 0x0041becc, 1},
244 { 0x0041bfdc, 1},
245 { 0x0041c054, 1},
246 { 0x0041c2b0, 1},
247 { 0x0041c2b8, 3},
248 { 0x0041c40c, 1},
249 { 0x0041c48c, 2},
250 { 0x0041c500, 1},
251 { 0x0041c508, 2},
252 { 0x0041c600, 11},
253 { 0x0041c634, 2},
254 { 0x0041c644, 11},
255 { 0x0041c674, 10},
256 { 0x0041c6a4, 1},
257 { 0x0041c6ac, 2},
258 { 0x0041c6e8, 1},
259 { 0x0041c6f0, 28},
260 { 0x0041c770, 1},
261 { 0x0041c778, 2},
262 { 0x0041c798, 2},
263 { 0x0041c7dc, 1},
264 { 0x0041c854, 1},
265 { 0x0041cab0, 1},
266 { 0x0041cab8, 3},
267 { 0x0041cc0c, 1},
268 { 0x0041cc8c, 2},
269 { 0x0041cd00, 1},
270 { 0x0041cd08, 2},
271 { 0x0041ce00, 11},
272 { 0x0041ce34, 2},
273 { 0x0041ce44, 11},
274 { 0x0041ce74, 10},
275 { 0x0041cea4, 1},
276 { 0x0041ceac, 2},
277 { 0x0041cee8, 1},
278 { 0x0041cef0, 28},
279 { 0x0041cf70, 1},
280 { 0x0041cf78, 2},
281 { 0x0041cf98, 2},
282 { 0x0041cfdc, 1},
283 { 0x00500384, 1},
284 { 0x005004a0, 1},
285 { 0x00500604, 1},
286 { 0x00500680, 1},
287 { 0x00500714, 1},
288 { 0x0050081c, 1},
289 { 0x00500884, 1},
290 { 0x005008b0, 1},
291 { 0x005008c8, 3},
292 { 0x005008fc, 1},
293 { 0x00500b04, 1},
294 { 0x00500c04, 1},
295 { 0x00500c10, 8},
296 { 0x00500c88, 1},
297 { 0x00500d00, 1},
298 { 0x00500e08, 1},
299 { 0x00500f08, 1},
300 { 0x00501000, 1},
301 { 0x0050100c, 1},
302 { 0x00501018, 1},
303 { 0x00501854, 1},
304 { 0x00501ab0, 1},
305 { 0x00501ab8, 3},
306 { 0x00501c0c, 1},
307 { 0x00501c8c, 2},
308 { 0x00501d00, 1},
309 { 0x00501d08, 2},
310 { 0x00501e00, 11},
311 { 0x00501e34, 2},
312 { 0x00501e44, 11},
313 { 0x00501e74, 10},
314 { 0x00501ea4, 1},
315 { 0x00501eac, 2},
316 { 0x00501ee8, 1},
317 { 0x00501ef0, 28},
318 { 0x00501f70, 1},
319 { 0x00501f78, 2},
320 { 0x00501f98, 2},
321 { 0x00501fdc, 1},
322 { 0x0050202c, 2},
323 { 0x005020a0, 1},
324 { 0x005020a8, 1},
325 { 0x00502890, 2},
326 { 0x005028a0, 3},
327 { 0x005028b0, 2},
328 { 0x00503014, 1},
329 { 0x005030cc, 1},
330 { 0x005031dc, 1},
331 { 0x00503e14, 1},
332 { 0x00503ecc, 1},
333 { 0x00503fdc, 1},
334 { 0x00504054, 1},
335 { 0x005042b0, 1},
336 { 0x005042b8, 3},
337 { 0x0050440c, 1},
338 { 0x0050448c, 2},
339 { 0x00504500, 1},
340 { 0x00504508, 2},
341 { 0x00504600, 11},
342 { 0x00504634, 2},
343 { 0x00504644, 11},
344 { 0x00504674, 10},
345 { 0x005046a4, 1},
346 { 0x005046ac, 2},
347 { 0x005046e8, 1},
348 { 0x005046f0, 28},
349 { 0x00504770, 1},
350 { 0x00504778, 2},
351 { 0x00504798, 2},
352 { 0x005047dc, 1},
353 { 0x00504854, 1},
354 { 0x00504ab0, 1},
355 { 0x00504ab8, 3},
356 { 0x00504c0c, 1},
357 { 0x00504c8c, 2},
358 { 0x00504d00, 1},
359 { 0x00504d08, 2},
360 { 0x00504e00, 11},
361 { 0x00504e34, 2},
362 { 0x00504e44, 11},
363 { 0x00504e74, 10},
364 { 0x00504ea4, 1},
365 { 0x00504eac, 2},
366 { 0x00504ee8, 1},
367 { 0x00504ef0, 28},
368 { 0x00504f70, 1},
369 { 0x00504f78, 2},
370 { 0x00504f98, 2},
371 { 0x00504fdc, 1},
372 { 0x00900100, 1},
373 { 0x009a0100, 1},
374};
375
376static const u32 gp10b_global_whitelist_ranges_count =
377 ARRAY_SIZE(gp10b_global_whitelist_ranges);
378
379/* context */
380
381/* runcontrol */
382static const u32 gp10b_runcontrol_whitelist[] = {
383};
384static const u32 gp10b_runcontrol_whitelist_count =
385 ARRAY_SIZE(gp10b_runcontrol_whitelist);
386
387static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = {
388};
389static const u32 gp10b_runcontrol_whitelist_ranges_count =
390 ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges);
391
392
393/* quad ctl */
394static const u32 gp10b_qctl_whitelist[] = {
395};
396static const u32 gp10b_qctl_whitelist_count =
397 ARRAY_SIZE(gp10b_qctl_whitelist);
398
399static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = {
400};
401static const u32 gp10b_qctl_whitelist_ranges_count =
402 ARRAY_SIZE(gp10b_qctl_whitelist_ranges);
403
404static const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void)
405{
406 return gp10b_global_whitelist_ranges;
407}
408
409static int gp10b_get_global_whitelist_ranges_count(void)
410{
411 return gp10b_global_whitelist_ranges_count;
412}
413
414static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void)
415{
416 return gp10b_global_whitelist_ranges;
417}
418
419static int gp10b_get_context_whitelist_ranges_count(void)
420{
421 return gp10b_global_whitelist_ranges_count;
422}
423
424static const u32 *gp10b_get_runcontrol_whitelist(void)
425{
426 return gp10b_runcontrol_whitelist;
427}
428
429static int gp10b_get_runcontrol_whitelist_count(void)
430{
431 return gp10b_runcontrol_whitelist_count;
432}
433
434static const
435struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void)
436{
437 return gp10b_runcontrol_whitelist_ranges;
438}
439
440static int gp10b_get_runcontrol_whitelist_ranges_count(void)
441{
442 return gp10b_runcontrol_whitelist_ranges_count;
443}
444
445static const u32 *gp10b_get_qctl_whitelist(void)
446{
447 return gp10b_qctl_whitelist;
448}
449
450static int gp10b_get_qctl_whitelist_count(void)
451{
452 return gp10b_qctl_whitelist_count;
453}
454
455static const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void)
456{
457 return gp10b_qctl_whitelist_ranges;
458}
459
460static int gp10b_get_qctl_whitelist_ranges_count(void)
461{
462 return gp10b_qctl_whitelist_ranges_count;
463}
464
465static int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
466{
467 /* Not needed on gp10b */
468 return 0;
469}
470
471void gp10b_init_regops(struct gpu_ops *gops)
472{
473 gops->regops.get_global_whitelist_ranges =
474 gp10b_get_global_whitelist_ranges;
475 gops->regops.get_global_whitelist_ranges_count =
476 gp10b_get_global_whitelist_ranges_count;
477
478 gops->regops.get_context_whitelist_ranges =
479 gp10b_get_context_whitelist_ranges;
480 gops->regops.get_context_whitelist_ranges_count =
481 gp10b_get_context_whitelist_ranges_count;
482
483 gops->regops.get_runcontrol_whitelist =
484 gp10b_get_runcontrol_whitelist;
485 gops->regops.get_runcontrol_whitelist_count =
486 gp10b_get_runcontrol_whitelist_count;
487
488 gops->regops.get_runcontrol_whitelist_ranges =
489 gp10b_get_runcontrol_whitelist_ranges;
490 gops->regops.get_runcontrol_whitelist_ranges_count =
491 gp10b_get_runcontrol_whitelist_ranges_count;
492
493 gops->regops.get_qctl_whitelist =
494 gp10b_get_qctl_whitelist;
495 gops->regops.get_qctl_whitelist_count =
496 gp10b_get_qctl_whitelist_count;
497
498 gops->regops.get_qctl_whitelist_ranges =
499 gp10b_get_qctl_whitelist_ranges;
500 gops->regops.get_qctl_whitelist_ranges_count =
501 gp10b_get_qctl_whitelist_ranges_count;
502
503 gops->regops.apply_smpc_war =
504 gp10b_apply_smpc_war;
505}
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
deleted file mode 100644
index 8727951a6..000000000
--- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 *
3 * Tegra GP10B GPU Debugger Driver Register Ops
4 *
5 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __REGOPS_GP10B_H_
20#define __REGOPS_GP10B_H_
21
22void gp10b_init_regops(struct gpu_ops *gops);
23
24#endif /* __REGOPS_GP10B_H_ */
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
deleted file mode 100644
index 59af5cded..000000000
--- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c
+++ /dev/null
@@ -1,150 +0,0 @@
1/*
2 * GP10B RPFB
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/pm_runtime.h>
17#include <linux/dma-mapping.h>
18#include "gk20a/gk20a.h"
19#include "rpfb_gp10b.h"
20#include "hw_fifo_gp10b.h"
21#include "hw_fb_gp10b.h"
22#include "hw_bus_gp10b.h"
23#include "hw_gmmu_gp10b.h"
24
25int gp10b_replayable_pagefault_buffer_init(struct gk20a *g)
26{
27 u32 addr_lo;
28 u32 addr_hi;
29 struct vm_gk20a *vm = &g->mm.bar2.vm;
30 int err;
31 size_t rbfb_size = NV_UVM_FAULT_BUF_SIZE *
32 fifo_replay_fault_buffer_size_hw_entries_v();
33
34 gk20a_dbg_fn("");
35
36 if (!g->mm.bar2_desc.gpu_va) {
37 err = gk20a_gmmu_alloc_map(vm, rbfb_size,
38 &g->mm.bar2_desc);
39 if (err) {
40 dev_err(dev_from_gk20a(g),
41 "%s Error in replayable fault buffer\n", __func__);
42 return err;
43 }
44 }
45 addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12);
46 addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va);
47 gk20a_writel(g, fifo_replay_fault_buffer_hi_r(),
48 fifo_replay_fault_buffer_hi_base_f(addr_hi));
49
50 gk20a_writel(g, fifo_replay_fault_buffer_lo_r(),
51 fifo_replay_fault_buffer_lo_base_f(addr_lo) |
52 fifo_replay_fault_buffer_lo_enable_true_v());
53 gk20a_dbg_fn("done");
54 return 0;
55}
56
57void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g)
58{
59 struct vm_gk20a *vm = &g->mm.bar2.vm;
60
61 gk20a_gmmu_unmap_free(vm, &g->mm.bar2_desc);
62}
63
64u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g)
65{
66 u32 get_idx = 0;
67
68 gk20a_dbg_fn("");
69
70 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
71
72 if (get_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
73 dev_err(dev_from_gk20a(g), "%s Error in replayable fault buffer\n",
74 __func__);
75 gk20a_dbg_fn("done");
76 return get_idx;
77}
78
79u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g)
80{
81 u32 put_idx = 0;
82
83 gk20a_dbg_fn("");
84 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
85
86 if (put_idx >= fifo_replay_fault_buffer_size_hw_entries_v())
87 dev_err(dev_from_gk20a(g), "%s Error in UVM\n",
88 __func__);
89 gk20a_dbg_fn("done");
90 return put_idx;
91}
92
93bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g)
94{
95 u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
96 u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
97
98 return (get_idx == put_idx ? true : false);
99}
100
101bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g)
102{
103 u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r());
104 u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r());
105 u32 hw_entries = gk20a_readl(g, fifo_replay_fault_buffer_size_r());
106
107 return (get_idx == ((put_idx + 1) % hw_entries) ? true : false);
108}
109
110bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g)
111{
112 u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
113
114 return fifo_replay_fault_buffer_info_overflow_f(info);
115}
116
117void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g)
118{
119 u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r());
120
121 info |= fifo_replay_fault_buffer_info_overflow_clear_v();
122 gk20a_writel(g, fifo_replay_fault_buffer_info_r(), info);
123
124}
125
126void gp10b_replayable_pagefault_buffer_info(struct gk20a *g)
127{
128
129 gk20a_dbg_fn("");
130 pr_info("rpfb low: 0x%x\n",
131 (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) >> 12));
132 pr_info("rpfb hi: 0x%x\n",
133 gk20a_readl(g, fifo_replay_fault_buffer_hi_r()));
134 pr_info("rpfb enabled: 0x%x\n",
135 (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) & 0x1));
136 pr_info("rpfb size: %d\n",
137 gk20a_readl(g, fifo_replay_fault_buffer_size_r()));
138 pr_info("rpfb get index: %d\n",
139 gp10b_replayable_pagefault_buffer_get_index(g));
140 pr_info("rpfb put index: %d\n",
141 gp10b_replayable_pagefault_buffer_put_index(g));
142 pr_info("rpfb empty: %d\n",
143 gp10b_replayable_pagefault_buffer_is_empty(g));
144 pr_info("rpfb full %d\n",
145 gp10b_replayable_pagefault_buffer_is_full(g));
146 pr_info("rpfb overflow %d\n",
147 gp10b_replayable_pagefault_buffer_is_overflow(g));
148
149 gk20a_dbg_fn("done");
150}
diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h
deleted file mode 100644
index 965c9573c..000000000
--- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef RPFB_GP20B_H
15#define RPFB_GP20B_H
16struct gk20a;
17
18#define NV_UVM_FAULT_BUF_SIZE 32
19
20int gp10b_replayable_pagefault_buffer_init(struct gk20a *g);
21u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g);
22u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g);
23bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g);
24bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g);
25bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g);
26void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g);
27void gp10b_replayable_pagefault_buffer_info(struct gk20a *g);
28void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g);
29
30#endif
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
deleted file mode 100644
index 687593b05..000000000
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * drivers/gpu/nvgpu/gm20b/therm_gk20a.c
3 *
4 * GP10B Therm
5 *
6 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 */
17
18#include "gk20a/gk20a.h"
19#include "hw_therm_gp10b.h"
20
21static int gp10b_init_therm_setup_hw(struct gk20a *g)
22{
23 u32 v;
24
25 gk20a_dbg_fn("");
26
27 /* program NV_THERM registers */
28 gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
29 therm_use_a_ext_therm_1_enable_f() |
30 therm_use_a_ext_therm_2_enable_f());
31 gk20a_writel(g, therm_evt_ext_therm_0_r(),
32 therm_evt_ext_therm_0_slow_factor_f(0x2));
33 gk20a_writel(g, therm_evt_ext_therm_1_r(),
34 therm_evt_ext_therm_1_slow_factor_f(0x6));
35 gk20a_writel(g, therm_evt_ext_therm_2_r(),
36 therm_evt_ext_therm_2_slow_factor_f(0xe));
37
38 gk20a_writel(g, therm_grad_stepping_table_r(0),
39 therm_grad_stepping_table_slowdown_factor0_f(
40 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
41 therm_grad_stepping_table_slowdown_factor1_f(
42 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
43 therm_grad_stepping_table_slowdown_factor2_f(
44 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
45 therm_grad_stepping_table_slowdown_factor3_f(
46 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
47 therm_grad_stepping_table_slowdown_factor4_f(
48 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
49
50 gk20a_writel(g, therm_grad_stepping_table_r(1),
51 therm_grad_stepping_table_slowdown_factor0_f(
52 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
53 therm_grad_stepping_table_slowdown_factor1_f(
54 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
55 therm_grad_stepping_table_slowdown_factor2_f(
56 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
57 therm_grad_stepping_table_slowdown_factor3_f(
58 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
59 therm_grad_stepping_table_slowdown_factor4_f(
60 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
61
62 v = gk20a_readl(g, therm_clk_timing_r(0));
63 v |= therm_clk_timing_grad_slowdown_enabled_f();
64 gk20a_writel(g, therm_clk_timing_r(0), v);
65
66 v = gk20a_readl(g, therm_config2_r());
67 v |= therm_config2_grad_enable_f(1);
68 v |= therm_config2_slowdown_factor_extended_f(1);
69 gk20a_writel(g, therm_config2_r(), v);
70
71 gk20a_writel(g, therm_grad_stepping1_r(),
72 therm_grad_stepping1_pdiv_duration_f(32));
73
74 v = gk20a_readl(g, therm_grad_stepping0_r());
75 v |= therm_grad_stepping0_feature_enable_f();
76 gk20a_writel(g, therm_grad_stepping0_r(), v);
77
78 return 0;
79}
80
81static int gp10b_update_therm_gate_ctrl(struct gk20a *g)
82{
83 u32 gate_ctrl;
84
85 gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A));
86 gate_ctrl = set_field(gate_ctrl,
87 therm_gate_ctrl_eng_delay_before_m(),
88 therm_gate_ctrl_eng_delay_before_f(4));
89 gk20a_writel(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A), gate_ctrl);
90
91 return 0;
92}
93
94void gp10b_init_therm_ops(struct gpu_ops *gops)
95{
96 gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw;
97 gops->therm.update_therm_gate_ctrl = gp10b_update_therm_gate_ctrl;
98
99}
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/therm_gp10b.h
deleted file mode 100644
index 18c102fe4..000000000
--- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef THERM_GP10B_H
14#define THERM_GP10B_H
15
16struct gpu_ops;
17void gp10b_init_therm_ops(struct gpu_ops *gops);
18
19#endif /* THERM_GP10B_H */
diff --git a/drivers/gpu/nvgpu/gr_t18x.h b/drivers/gpu/nvgpu/gr_t18x.h
deleted file mode 100644
index 95601116f..000000000
--- a/drivers/gpu/nvgpu/gr_t18x.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * NVIDIA T18x GR
3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15#ifndef _NVGPU_GR_T18X_H_
16#define _NVGPU_GR_T18X_H_
17
18#include "gp10b/gr_gp10b.h"
19
20#endif
diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h
deleted file mode 100644
index 96f021252..000000000
--- a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * NVIDIA GPU ID functions, definitions.
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15#ifndef _NVGPU_GPUID_T18X_H_
16#define _NVGPU_GPUID_T18X_H_
17
18#define NVGPU_GPUID_GP10B \
19 GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP10B)
20
21#define NVGPU_COMPAT_TEGRA_GP10B "nvidia,tegra186-gp10b"
22#define NVGPU_COMPAT_GENERIC_GP10B "nvidia,generic-gp10b"
23
24#define TEGRA_18x_GPUID NVGPU_GPUID_GP10B
25#define TEGRA_18x_GPUID_HAL gp10b_init_hal
26#define TEGRA_18x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GP10B
27#define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B
28struct gpu_ops;
29extern int gp10b_init_hal(struct gk20a *);
30extern struct gk20a_platform t18x_gpu_tegra_platform;
31
32#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
33#define TEGRA_18x_GPUID_VGPU_HAL vgpu_gp10b_init_hal
34extern int vgpu_gp10b_init_hal(struct gk20a *);
35#endif
36#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c
deleted file mode 100644
index 34d942c15..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "vgpu_fifo_gp10b.h"
15
16void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops)
17{
18 /* syncpoint protection not supported yet */
19 gops->fifo.resetup_ramfc = NULL;
20}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
deleted file mode 100644
index 4ede0b6df..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __VGPU_FIFO_GP10B_H__
15#define __VGPU_FIFO_GP10B_H__
16
17#include "gk20a/gk20a.h"
18
19void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops);
20
21#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
deleted file mode 100644
index 3023ef4b1..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ /dev/null
@@ -1,206 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "vgpu/vgpu.h"
15#include "vgpu_gr_gp10b.h"
16#include "vgpu/gm20b/vgpu_gr_gm20b.h"
17
18#include "gp10b/hw_gr_gp10b.h"
19
20static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
21 struct gr_ctx_desc *gr_ctx)
22{
23 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
24 struct tegra_vgpu_cmd_msg msg;
25 struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx;
26 int err;
27
28 gk20a_dbg_fn("");
29
30 if (!gr_ctx || !gr_ctx->mem.gpu_va)
31 return;
32
33 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX;
34 msg.handle = platform->virt_handle;
35 p->handle = gr_ctx->virt_ctx;
36 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
37 WARN_ON(err || msg.ret);
38
39 gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, 0);
40
41 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer);
42 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer);
43 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer);
44 gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer);
45
46 kfree(gr_ctx);
47}
48
49static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
50 struct gr_ctx_desc **__gr_ctx,
51 struct vm_gk20a *vm,
52 u32 class,
53 u32 flags)
54{
55 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
56 struct tegra_vgpu_cmd_msg msg;
57 struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p =
58 &msg.params.gr_bind_ctxsw_buffers;
59 struct gr_ctx_desc *gr_ctx = *__gr_ctx;
60 int err;
61
62 gk20a_dbg_fn("");
63
64 WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX !=
65 TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST);
66
67 err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags);
68 if (err)
69 return err;
70
71 if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp)
72 flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP;
73
74 if (class == PASCAL_COMPUTE_A &&
75 g->gr.t18x.ctx_vars.force_preemption_cilp)
76 flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP;
77
78 if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) {
79 u32 spill_size =
80 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() *
81 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v();
82 u32 pagepool_size = g->ops.gr.pagepool_default_size(g) *
83 gr_scc_pagepool_total_pages_byte_granularity_v();
84 u32 betacb_size = g->gr.attrib_cb_default_size +
85 (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() -
86 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v());
87 u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) *
88 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() *
89 g->gr.max_tpc_count;
90 struct mem_desc *desc;
91
92 attrib_cb_size = ALIGN(attrib_cb_size, 128);
93
94 gk20a_dbg_info("gfxp context preempt size=%d",
95 g->gr.t18x.ctx_vars.preempt_image_size);
96 gk20a_dbg_info("gfxp context spill size=%d", spill_size);
97 gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size);
98 gk20a_dbg_info("gfxp context attrib cb size=%d",
99 attrib_cb_size);
100
101 err = gr_gp10b_alloc_buffer(vm,
102 g->gr.t18x.ctx_vars.preempt_image_size,
103 &gr_ctx->t18x.preempt_ctxsw_buffer);
104 if (err) {
105 err = -ENOMEM;
106 goto fail;
107 }
108 desc = &gr_ctx->t18x.preempt_ctxsw_buffer;
109 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va;
110 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size;
111
112 err = gr_gp10b_alloc_buffer(vm,
113 spill_size,
114 &gr_ctx->t18x.spill_ctxsw_buffer);
115 if (err) {
116 err = -ENOMEM;
117 goto fail;
118 }
119 desc = &gr_ctx->t18x.spill_ctxsw_buffer;
120 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va;
121 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size;
122
123 err = gr_gp10b_alloc_buffer(vm,
124 pagepool_size,
125 &gr_ctx->t18x.pagepool_ctxsw_buffer);
126 if (err) {
127 err = -ENOMEM;
128 goto fail;
129 }
130 desc = &gr_ctx->t18x.pagepool_ctxsw_buffer;
131 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] =
132 desc->gpu_va;
133 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size;
134
135 err = gr_gp10b_alloc_buffer(vm,
136 attrib_cb_size,
137 &gr_ctx->t18x.betacb_ctxsw_buffer);
138 if (err) {
139 err = -ENOMEM;
140 goto fail;
141 }
142 desc = &gr_ctx->t18x.betacb_ctxsw_buffer;
143 p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] =
144 desc->gpu_va;
145 p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size;
146
147 gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP;
148 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP;
149 }
150
151 if (class == PASCAL_COMPUTE_A) {
152 if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) {
153 gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP;
154 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP;
155 } else {
156 gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA;
157 p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA;
158 }
159 }
160
161 if (gr_ctx->preempt_mode) {
162 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS;
163 msg.handle = platform->virt_handle;
164 p->handle = gr_ctx->virt_ctx;
165 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
166 if (err || msg.ret) {
167 err = -ENOMEM;
168 goto fail;
169 }
170 }
171
172 gk20a_dbg_fn("done");
173 return err;
174
175fail:
176 vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx);
177 return err;
178}
179
180static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
181{
182 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
183 int err;
184
185 gk20a_dbg_fn("");
186
187 err = vgpu_gr_init_ctx_state(g);
188 if (err)
189 return err;
190
191 vgpu_get_attribute(platform->virt_handle,
192 TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE,
193 &g->gr.t18x.ctx_vars.preempt_image_size);
194 if (!g->gr.t18x.ctx_vars.preempt_image_size)
195 return -ENXIO;
196
197 return 0;
198}
199
200void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops)
201{
202 vgpu_gm20b_init_gr_ops(gops);
203 gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx;
204 gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx;
205 gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state;
206}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
deleted file mode 100644
index b3be49a77..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __VGPU_GR_GP10B_H__
15#define __VGPU_GR_GP10B_H__
16
17#include "gk20a/gk20a.h"
18
19void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops);
20
21#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
deleted file mode 100644
index b665a8dd6..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "vgpu/vgpu.h"
15#include "gp10b/hal_gp10b.h"
16#include "vgpu_gr_gp10b.h"
17#include "vgpu_fifo_gp10b.h"
18#include "vgpu_mm_gp10b.h"
19#include "nvgpu_gpuid_t18x.h"
20
21int vgpu_gp10b_init_hal(struct gk20a *g)
22{
23 int err;
24
25 gk20a_dbg_fn("");
26
27 err = gp10b_init_hal(g);
28 if (err)
29 return err;
30
31 vgpu_init_hal_common(g);
32 vgpu_gp10b_init_gr_ops(&g->ops);
33 vgpu_gp10b_init_fifo_ops(&g->ops);
34 vgpu_gp10b_init_mm_ops(&g->ops);
35 return 0;
36}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
deleted file mode 100644
index 3a286249c..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
+++ /dev/null
@@ -1,185 +0,0 @@
1/*
2 * Virtualized GPU Memory Management
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/dma-mapping.h>
17#include "vgpu/vgpu.h"
18#include "vgpu_mm_gp10b.h"
19#include "gk20a/semaphore_gk20a.h"
20#include "gk20a/mm_gk20a.h"
21
22static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g)
23{
24 g->mm.bypass_smmu = true;
25 g->mm.disable_bigpage = true;
26 return 0;
27}
28
29static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc,
30 u64 addr, u64 size, size_t *oob_size)
31{
32 if (*oob_size < sizeof(*mem_desc))
33 return -ENOMEM;
34
35 mem_desc->addr = addr;
36 mem_desc->length = size;
37 *oob_size -= sizeof(*mem_desc);
38 return 0;
39}
40
41static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
42 u64 map_offset,
43 struct sg_table *sgt,
44 u64 buffer_offset,
45 u64 size,
46 int pgsz_idx,
47 u8 kind_v,
48 u32 ctag_offset,
49 u32 flags,
50 int rw_flag,
51 bool clear_ctags,
52 bool sparse,
53 bool priv,
54 struct vm_gk20a_mapping_batch *batch)
55{
56 int err = 0;
57 struct device *d = dev_from_vm(vm);
58 struct gk20a *g = gk20a_from_vm(vm);
59 struct gk20a_platform *platform = gk20a_get_platform(g->dev);
60 struct tegra_vgpu_cmd_msg msg;
61 struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex;
62 struct tegra_vgpu_mem_desc *mem_desc;
63 u32 page_size = vm->gmmu_page_sizes[pgsz_idx];
64 u64 space_to_skip = buffer_offset;
65 u64 buffer_size = 0;
66 u32 mem_desc_count = 0;
67 struct scatterlist *sgl;
68 void *handle = NULL;
69 size_t oob_size;
70 u8 prot;
71
72 gk20a_dbg_fn("");
73
74 /* FIXME: add support for sparse mappings */
75
76 if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu))
77 return -EINVAL;
78
79 if (space_to_skip & (page_size - 1))
80 return -EINVAL;
81
82 /* Allocate (or validate when map_offset != 0) the virtual address. */
83 if (!map_offset) {
84 map_offset = gk20a_vm_alloc_va(vm, size, pgsz_idx);
85 if (!map_offset) {
86 gk20a_err(d, "failed to allocate va space");
87 err = -ENOMEM;
88 goto fail;
89 }
90 }
91
92 handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT,
93 tegra_gr_comm_get_server_vmid(),
94 TEGRA_VGPU_QUEUE_CMD,
95 (void **)&mem_desc, &oob_size);
96 if (!handle) {
97 err = -EINVAL;
98 goto fail;
99 }
100
101 sgl = sgt->sgl;
102 while (space_to_skip && sgl &&
103 (space_to_skip + page_size > sgl->length)) {
104 space_to_skip -= sgl->length;
105 sgl = sg_next(sgl);
106 }
107 WARN_ON(!sgl);
108
109 if (add_mem_desc(&mem_desc[mem_desc_count++],
110 sg_phys(sgl) + space_to_skip,
111 sgl->length - space_to_skip,
112 &oob_size)) {
113 err = -ENOMEM;
114 goto fail;
115 }
116 buffer_size += sgl->length - space_to_skip;
117
118 sgl = sg_next(sgl);
119 while (sgl && buffer_size < size) {
120 if (add_mem_desc(&mem_desc[mem_desc_count++], sg_phys(sgl),
121 sgl->length, &oob_size)) {
122 err = -ENOMEM;
123 goto fail;
124 }
125
126 buffer_size += sgl->length;
127 sgl = sg_next(sgl);
128 }
129
130 if (rw_flag == gk20a_mem_flag_read_only)
131 prot = TEGRA_VGPU_MAP_PROT_READ_ONLY;
132 else if (rw_flag == gk20a_mem_flag_write_only)
133 prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY;
134 else
135 prot = TEGRA_VGPU_MAP_PROT_NONE;
136
137 if (pgsz_idx == gmmu_page_size_kernel) {
138 if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) {
139 pgsz_idx = gmmu_page_size_small;
140 } else if (page_size ==
141 vm->gmmu_page_sizes[gmmu_page_size_big]) {
142 pgsz_idx = gmmu_page_size_big;
143 } else {
144 gk20a_err(d, "invalid kernel page size %d\n",
145 page_size);
146 goto fail;
147 }
148 }
149
150 msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX;
151 msg.handle = platform->virt_handle;
152 p->handle = vm->handle;
153 p->gpu_va = map_offset;
154 p->size = size;
155 p->mem_desc_count = mem_desc_count;
156 p->pgsz_idx = pgsz_idx;
157 p->iova = 0;
158 p->kind = kind_v;
159 p->cacheable =
160 (flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0;
161 p->prot = prot;
162 p->ctag_offset = ctag_offset;
163 p->clear_ctags = clear_ctags;
164 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
165 if (err || msg.ret)
166 goto fail;
167
168 /* TLB invalidate handled on server side */
169
170 tegra_gr_comm_oob_put_ptr(handle);
171 return map_offset;
172fail:
173 if (handle)
174 tegra_gr_comm_oob_put_ptr(handle);
175 gk20a_err(d, "%s: failed with err=%d\n", __func__, err);
176 return 0;
177}
178
179void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops)
180{
181 gk20a_dbg_fn("");
182
183 gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map;
184 gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw;
185}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
deleted file mode 100644
index 5bdc9d1b5..000000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __VGPU_MM_GP10B_H__
15#define __VGPU_MM_GP10B_H__
16
17#include "gk20a/gk20a.h"
18
19void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops);
20
21#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 22:24:30 -0400