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authorLaxman Dewangan <ldewangan@nvidia.com>2017-11-20 05:53:26 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-21 04:00:05 -0500
commit5cc787821864112e7c0239fd44920d8a9d58a4a8 (patch)
treedbe4fee070a992206501091b10ed2c5cf2e01b95 /drivers/gpio
parent457393cdc5420904c14ea87028582c40b28132b2 (diff)
gpio: t186: Rename some of variables
Rename some of variables and functions to make more readable and easy to understands. Change-Id: Ida56d340150a875d6ed7d28b8f0dcf71b6d8f91a Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1601621 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/gpio-tegra186.c78
1 files changed, 39 insertions, 39 deletions
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index 7370c4a50..6f5755b8a 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -619,17 +619,17 @@ struct tegra_gpio_soc_info {
619 int nports; 619 int nports;
620 const int *wake_table; 620 const int *wake_table;
621 int nwakes; 621 int nwakes;
622 int interrupt_out_count; 622 int num_irq_line;
623 int num_banks; 623 int num_banks;
624 int interrupt_valid_offset; 624 int start_irq_line;
625}; 625};
626 626
627struct tegra_gpio_controller { 627struct tegra_gpio_controller {
628 int controller; 628 int bank;
629 int irq[MAX_IRQS]; 629 int irq[MAX_IRQS];
630 struct tegra_gpio_info *tgi; 630 struct tegra_gpio_info *tgi;
631 int route_map[MAX_IRQS][MAX_GPIO_PORTS]; 631 int irq_map[MAX_IRQS][MAX_GPIO_PORTS];
632 int ports_in_controller; 632 int num_ports;
633}; 633};
634 634
635struct tegra_gpio_saved_register { 635struct tegra_gpio_saved_register {
@@ -1001,23 +1001,23 @@ static void tegra_gpio_irq_handler_desc(struct irq_desc *desc)
1001 unsigned long val; 1001 unsigned long val;
1002 u32 addr; 1002 u32 addr;
1003 int port_map[MAX_GPIO_PORTS]; 1003 int port_map[MAX_GPIO_PORTS];
1004 int route_map_read; 1004 int irq_map_read;
1005 1005
1006 for (i = 0; i < MAX_GPIO_PORTS; ++i) 1006 for (i = 0; i < MAX_GPIO_PORTS; ++i)
1007 port_map[i] = -1; 1007 port_map[i] = -1;
1008 1008
1009 for (i = 0; i < tgi->soc->nports; ++i) { 1009 for (i = 0; i < tgi->soc->nports; ++i) {
1010 if (tgi->soc->port[i].cont_id == tg_cont->controller) 1010 if (tgi->soc->port[i].cont_id == tg_cont->bank)
1011 port_map[tgi->soc->port[i].port_index] = i; 1011 port_map[tgi->soc->port[i].port_index] = i;
1012 } 1012 }
1013 1013
1014 chained_irq_enter(chip, desc); 1014 chained_irq_enter(chip, desc);
1015 if (tgi->soc->interrupt_out_count > 1) { 1015 if (tgi->soc->num_irq_line > 1) {
1016 for (i = 0; i < MAX_GPIO_PORTS; i++) { 1016 for (i = 0; i < MAX_GPIO_PORTS; i++) {
1017 for (j = 0; j < 8; j++) { 1017 for (j = 0; j < 8; j++) {
1018 route_map_read = tg_cont->route_map[i + 1018 irq_map_read = tg_cont->irq_map[i +
1019 tgi->soc->interrupt_valid_offset][j]; 1019 tgi->soc->start_irq_line][j];
1020 if (route_map_read & 0xFF) { 1020 if (irq_map_read & 0xFF) {
1021 port = port_map[j]; 1021 port = port_map[j];
1022 addr = tgi->soc->port[port].reg_offset; 1022 addr = tgi->soc->port[port].reg_offset;
1023 val = __raw_readl( 1023 val = __raw_readl(
@@ -1103,8 +1103,7 @@ static inline int tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
1103} 1103}
1104#endif 1104#endif
1105 1105
1106static int tegra_update_ports_in_controller(struct tegra_gpio_info *tgi, 1106static int tegra_gpio_get_num_ports(struct tegra_gpio_info *tgi, int bank)
1107 int bank)
1108{ 1107{
1109 int i; 1108 int i;
1110 int count = 0; 1109 int count = 0;
@@ -1116,23 +1115,25 @@ static int tegra_update_ports_in_controller(struct tegra_gpio_info *tgi,
1116 return count; 1115 return count;
1117} 1116}
1118 1117
1119static void tegra_read_routemap(struct tegra_gpio_info *tgi, int bank, 1118static void tegra_gpio_read_irq_routemap(struct tegra_gpio_info *tgi, int bank,
1120 int interrupt_count) 1119 int irq_count)
1121{ 1120{
1121 struct tegra_gpio_controller *tgcont;
1122 int j; 1122 int j;
1123 1123
1124 for (j = 0; j < tgi->tg_contrlr[bank].ports_in_controller; j++) { 1124 for (j = 0; j < tgi->tg_contrlr[bank].num_ports; j++) {
1125 tgi->tg_contrlr[bank].route_map[interrupt_count + 1125 tgcont = &tgi->tg_contrlr[bank];
1126 tgi->soc->interrupt_valid_offset][j] = 1126 tgcont->irq_map[irq_count + tgi->soc->start_irq_line][j] =
1127 __raw_readl(tgi->scr_regs + (bank * 0x1000) + 0x800 + 1127 __raw_readl(tgi->scr_regs + (bank * 0x1000) + 0x800 +
1128 (j * GPIO_REG_DIFF) + ROUTE_MAP_OFFSET + 1128 (j * GPIO_REG_DIFF) + ROUTE_MAP_OFFSET +
1129 (interrupt_count * 4)); 1129 (irq_count * 4));
1130 } 1130 }
1131} 1131}
1132 1132
1133static int tegra_gpio_probe(struct platform_device *pdev) 1133static int tegra_gpio_probe(struct platform_device *pdev)
1134{ 1134{
1135 struct tegra_gpio_info *tgi; 1135 struct tegra_gpio_info *tgi;
1136 struct tegra_gpio_controller *tgcont;
1136 struct resource *res; 1137 struct resource *res;
1137 int bank; 1138 int bank;
1138 int gpio; 1139 int gpio;
@@ -1223,23 +1224,22 @@ static int tegra_gpio_probe(struct platform_device *pdev)
1223 } 1224 }
1224 1225
1225 for (bank = 0; bank < tgi->nbanks; bank++) { 1226 for (bank = 0; bank < tgi->nbanks; bank++) {
1226 tgi->tg_contrlr[bank].ports_in_controller = 1227 tgcont = &tgi->tg_contrlr[bank];
1227 tegra_update_ports_in_controller(tgi, bank); 1228 tgcont->num_ports = tegra_gpio_get_num_ports(tgi, bank);
1228 for (i = 0; i < tgi->soc->interrupt_out_count; i++) { 1229 for (i = 0; i < tgi->soc->num_irq_line; i++) {
1229 res = platform_get_resource(pdev, IORESOURCE_IRQ, i + 1230 res = platform_get_resource(pdev, IORESOURCE_IRQ, i +
1230 (bank * tgi->soc->interrupt_out_count)); 1231 (bank * tgi->soc->num_irq_line));
1231 if (!res) { 1232 if (!res) {
1232 dev_err(&pdev->dev, "Missing IRQ resource\n"); 1233 dev_err(&pdev->dev, "Missing IRQ resource\n");
1233 return -ENODEV; 1234 return -ENODEV;
1234 } 1235 }
1235 tgi->tg_contrlr[bank].irq[i + 1236 tgcont->irq[i + tgi->soc->start_irq_line] = res->start;
1236 tgi->soc->interrupt_valid_offset] = res->start; 1237 /* read each port IRQ routemap */
1237 /* read each port routemap */ 1238 if (tgi->soc->num_irq_line > 1)
1238 if (tgi->soc->interrupt_out_count > 1) 1239 tegra_gpio_read_irq_routemap(tgi, bank, i);
1239 tegra_read_routemap(tgi, bank, i);
1240 } 1240 }
1241 tgi->tg_contrlr[bank].controller = bank; 1241 tgcont->bank = bank;
1242 tgi->tg_contrlr[bank].tgi = tgi; 1242 tgcont->tgi = tgi;
1243 } 1243 }
1244 1244
1245 ret = gpiochip_add_data(&tgi->gc, tgi); 1245 ret = gpiochip_add_data(&tgi->gc, tgi);
@@ -1268,7 +1268,7 @@ static int tegra_gpio_probe(struct platform_device *pdev)
1268 } 1268 }
1269 1269
1270 for (bank = 0; bank < tgi->nbanks; bank++) { 1270 for (bank = 0; bank < tgi->nbanks; bank++) {
1271 for (i = 0; i < tgi->soc->interrupt_out_count; i++) { 1271 for (i = 0; i < tgi->soc->num_irq_line; i++) {
1272 irq_set_chained_handler_and_data( 1272 irq_set_chained_handler_and_data(
1273 tgi->tg_contrlr[bank].irq[i], 1273 tgi->tg_contrlr[bank].irq[i],
1274 tegra_gpio_irq_handler_desc, 1274 tegra_gpio_irq_handler_desc,
@@ -1331,9 +1331,9 @@ static const struct tegra_gpio_soc_info t186_gpio_soc = {
1331 .nports = ARRAY_SIZE(tegra186_gpio_cinfo), 1331 .nports = ARRAY_SIZE(tegra186_gpio_cinfo),
1332 .wake_table = tegra186_gpio_wakes, 1332 .wake_table = tegra186_gpio_wakes,
1333 .nwakes = ARRAY_SIZE(tegra186_gpio_wakes), 1333 .nwakes = ARRAY_SIZE(tegra186_gpio_wakes),
1334 .interrupt_out_count = 1, 1334 .num_irq_line = 1,
1335 .num_banks = 0, 1335 .num_banks = 0,
1336 .interrupt_valid_offset = 0, 1336 .start_irq_line = 0,
1337}; 1337};
1338 1338
1339static const struct tegra_gpio_soc_info t186_aon_gpio_soc = { 1339static const struct tegra_gpio_soc_info t186_aon_gpio_soc = {
@@ -1343,9 +1343,9 @@ static const struct tegra_gpio_soc_info t186_aon_gpio_soc = {
1343 .nports = ARRAY_SIZE(tegra186_aon_gpio_cinfo), 1343 .nports = ARRAY_SIZE(tegra186_aon_gpio_cinfo),
1344 .wake_table = tegra186_aon_gpio_wakes, 1344 .wake_table = tegra186_aon_gpio_wakes,
1345 .nwakes = ARRAY_SIZE(tegra186_aon_gpio_wakes), 1345 .nwakes = ARRAY_SIZE(tegra186_aon_gpio_wakes),
1346 .interrupt_out_count = 1, 1346 .num_irq_line = 1,
1347 .num_banks = 0, 1347 .num_banks = 0,
1348 .interrupt_valid_offset = 0, 1348 .start_irq_line = 0,
1349}; 1349};
1350 1350
1351static const struct tegra_gpio_soc_info t194_gpio_soc = { 1351static const struct tegra_gpio_soc_info t194_gpio_soc = {
@@ -1355,9 +1355,9 @@ static const struct tegra_gpio_soc_info t194_gpio_soc = {
1355 .nports = ARRAY_SIZE(tegra194_gpio_cinfo), 1355 .nports = ARRAY_SIZE(tegra194_gpio_cinfo),
1356 .wake_table = tegra194_gpio_wakes, 1356 .wake_table = tegra194_gpio_wakes,
1357 .nwakes = ARRAY_SIZE(tegra194_gpio_wakes), 1357 .nwakes = ARRAY_SIZE(tegra194_gpio_wakes),
1358 .interrupt_out_count = 8, 1358 .num_irq_line = 8,
1359 .num_banks = 6, 1359 .num_banks = 6,
1360 .interrupt_valid_offset = 0, 1360 .start_irq_line = 0,
1361}; 1361};
1362 1362
1363static const struct tegra_gpio_soc_info t194_aon_gpio_soc = { 1363static const struct tegra_gpio_soc_info t194_aon_gpio_soc = {
@@ -1367,9 +1367,9 @@ static const struct tegra_gpio_soc_info t194_aon_gpio_soc = {
1367 .nports = ARRAY_SIZE(tegra194_aon_gpio_cinfo), 1367 .nports = ARRAY_SIZE(tegra194_aon_gpio_cinfo),
1368 .wake_table = tegra194_aon_gpio_wakes, 1368 .wake_table = tegra194_aon_gpio_wakes,
1369 .nwakes = ARRAY_SIZE(tegra194_aon_gpio_wakes), 1369 .nwakes = ARRAY_SIZE(tegra194_aon_gpio_wakes),
1370 .interrupt_out_count = 4, 1370 .num_irq_line = 4,
1371 .num_banks = 1, 1371 .num_banks = 1,
1372 .interrupt_valid_offset = 4, 1372 .start_irq_line = 4,
1373}; 1373};
1374 1374
1375static struct of_device_id tegra_gpio_of_match[] = { 1375static struct of_device_id tegra_gpio_of_match[] = {