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authorVenkat Reddy Talla <vreddytalla@nvidia.com>2016-09-09 10:04:26 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-09-19 11:14:36 -0400
commit1666f1964a3fc345f6daa96fb9ea112dc256b98b (patch)
tree47211a3a576205a03c8228c2a050306c0e1f4e17 /arch
parent5c7ae255f4c11a40d6924800e59c30a6330eb321 (diff)
ARM64: dts: delete SIM dts and dtsi files
SIM dts files and dtsi include files moved to new repo $TOP/hardware/nvidia/platform/t18x/sim, deleting sim dts and dtsi files from kernel/t18x repo. Bug 200217137 Change-Id: I7fc9ccc67e417a5f69602c2fc1d5387789707a94 Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Reviewed-on: http://git-master/r/1217977 GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi684
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-hdmi.dtsi186
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-private.dts408
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-virtual-clock.dtsi103
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34324618-private.dtsi16
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539-private.dtsi15
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539.dts31
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-sim-fpga.dtsi280
8 files changed, 0 insertions, 1723 deletions
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi
deleted file mode 100644
index 4c7ac1019..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi
+++ /dev/null
@@ -1,684 +0,0 @@
1/*
2 * arch/arm/boot/dts/panel-sim.dtsi
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20#include <dt-bindings/display/tegra-dc.h>
21#include <dt-bindings/display/tegra-panel.h>
22
23/ {
24 host1x {
25 sor {
26 panel-nvidia-sim {
27 compatible = "nvidia,sim-panel";
28 nvidia,tx-pu-disable = <1>;
29 disp-default-out {
30 nvidia,out-type = <TEGRA_DC_OUT_FAKE_DP>;
31 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
32 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
33 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
34 nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
35 TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
36 TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
37 TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
38 nvidia,out-depth = <18>;
39 nvidia,out-parent-clk = "pll_d_out0";
40 nvidia,out-xres = <128>;
41 nvidia,out-yres = <96>;
42 };
43 display-timings {
44 128x96-32 {
45 clock-frequency = <27000000>;
46 hactive = <128>;
47 vactive = <96>;
48 hfront-porch = <8>;
49 hback-porch = <16>;
50 hsync-len = <8>;
51 vfront-porch = <3>;
52 vback-porch = <3>;
53 vsync-len = <4>;
54 nvidia,h-ref-to-sync = <1>;
55 nvidia,v-ref-to-sync = <1>;
56 };
57 };
58 };
59
60 dp-ufpga-panel {
61 compatible = "nvidia,dp-ufpga-panel";
62 nvidia,tx-pu-disable = <1>;
63 disp-default-out {
64 nvidia,out-type = <TEGRA_DC_OUT_DP>;
65 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
66 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
67 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
68 nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
69 TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
70 TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
71 TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
72 nvidia,out-depth = <18>;
73 nvidia,out-parent-clk = "pll_d_out0";
74 nvidia,out-xres = <720>;
75 nvidia,out-yres = <480>;
76 };
77 display-timings {
78 720x480-32 {
79 clock-frequency = <27000000>;
80 hactive = <720>;
81 vactive = <480>;
82 hfront-porch = <48>;
83 hback-porch = <80>;
84 hsync-len = <32>;
85 vfront-porch = <24>;
86 vback-porch = <126>;
87 vsync-len = <10>;
88 nvidia,h-ref-to-sync = <1>;
89 nvidia,v-ref-to-sync = <1>;
90 };
91 };
92 dp-lt-settings {
93 lt-setting@0 {
94 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
95 nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
96 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
97 nvidia,tx-pu = <0>;
98 nvidia,load-adj = <0x3>;
99 };
100 lt-setting@1 {
101 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
102 nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
103 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
104 nvidia,tx-pu = <0>;
105 nvidia,load-adj = <0x4>;
106 };
107 lt-setting@2 {
108 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
109 nvidia,lane-preemphasis = <PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1>;
110 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
111 nvidia,tx-pu = <0>;
112 nvidia,load-adj = <0x6>;
113 };
114 };
115 };
116 };
117
118 sor1 {
119 panel-nvidia-sim {
120 compatible = "nvidia,sim-panel";
121 nvidia,tx-pu-disable = <1>;
122 disp-default-out {
123 nvidia,out-type = <TEGRA_DC_OUT_FAKE_DP>;
124 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
125 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
126 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
127 nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
128 TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
129 TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
130 TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
131 nvidia,out-depth = <18>;
132 nvidia,out-parent-clk = "pll_d_out0";
133 nvidia,out-xres = <128>;
134 nvidia,out-yres = <96>;
135 };
136 display-timings {
137 128x96-32 {
138 clock-frequency = <27000000>;
139 hactive = <128>;
140 vactive = <96>;
141 hfront-porch = <8>;
142 hback-porch = <16>;
143 hsync-len = <8>;
144 vfront-porch = <3>;
145 vback-porch = <3>;
146 vsync-len = <4>;
147 nvidia,h-ref-to-sync = <1>;
148 nvidia,v-ref-to-sync = <1>;
149 };
150 420x280-32 {
151 clock-frequency = <27000000>;
152 hactive = <420>;
153 vactive = <280>;
154 hfront-porch = <16>;
155 hback-porch = <12>;
156 hsync-len = <16>;
157 vfront-porch = <3>;
158 vback-porch = <19>;
159 vsync-len = <14>;
160 nvidia,h-ref-to-sync = <11>;
161 nvidia,v-ref-to-sync = <1>;
162 };
163 };
164 dp-lt-settings {
165 lt-setting@0 {
166 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
167 nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
168 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
169 nvidia,tx-pu = <0>;
170 nvidia,load-adj = <0x3>;
171 };
172 lt-setting@1 {
173 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
174 nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
175 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
176 nvidia,tx-pu = <0>;
177 nvidia,load-adj = <0x4>;
178 };
179 lt-setting@2 {
180 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
181 nvidia,lane-preemphasis = <PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1>;
182 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
183 nvidia,tx-pu = <0>;
184 nvidia,load-adj = <0x6>;
185 };
186 };
187 };
188 };
189 dsi {
190 panel-s-wuxga-8-0 {
191 status = "okay";
192 compatible = "s,wuxga-8-0";
193 nvidia,dsi-instance = <DSI_INSTANCE_0>;
194 nvidia,dsi-n-data-lanes = <8>;
195 nvidia,dsi-pixel-format = <TEGRA_DSI_PIXEL_FORMAT_24BIT_P>;
196 nvidia,dsi-refresh-rate = <60>;
197 nvidia,dsi-video-data-type = <0>;
198 nvidia,dsi-video-clock-mode = <0>;
199 nvidia,dsi-video-burst-mode = <0>;
200 nvidia,dsi-ganged-type = <TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT>;
201 nvidia,dsi-ganged-swap-links = <1>;
202 nvidia,dsi-ganged-write-to-all-links = <1>;
203 nvidia,dsi-controller-vs = <DSI_VS_1>;
204 nvidia,dsi-virtual-channel = <TEGRA_DSI_VIRTUAL_CHANNEL_0>;
205 nvidia,dsi-panel-reset = <TEGRA_DSI_ENABLE>;
206 nvidia,dsi-power-saving-suspend = <TEGRA_DSI_ENABLE>;
207 nvidia,dsi-ulpm-not-support = <TEGRA_DSI_ENABLE>;
208 nvidia,dsi-suspend-stop-stream-late = <1>;
209 nvidia,dsi-init-cmd =
210 /* Long Packet: <PACKETTYPE[u8] COMMANDID[u8] PAYLOADCOUNT[u16] ECC[u8] PAYLOAD[..] CHECKSUM[u16]> */
211 /* Short Packet: <PACKETTYPE[u8] COMMANDID[u8] DATA0[u8] DATA1[u8] ECC[u8]> */
212 /* For DSI packets each DT cell is interpreted as u8 not u32 */
213
214 <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_EXIT_SLEEP_MODE 0x0 0x0>,
215 /* This panel has a very sensitive power on/off sequence.
216 * Send a few more frames for safety. No max limit from vendor. */
217 <TEGRA_DSI_SEND_FRAME 10>,
218 <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_ON 0x0 0x0>;
219 nvidia,dsi-n-init-cmd = <3>;
220 nvidia,dsi-suspend-cmd =
221 <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_SET_DISPLAY_OFF 0x0 0x0>,
222 <TEGRA_DSI_SEND_FRAME 3>,
223 <TEGRA_DSI_PACKET_CMD DSI_DCS_WRITE_0_PARAM DSI_DCS_ENTER_SLEEP_MODE 0x0 0x0>,
224 <TEGRA_DSI_SEND_FRAME 10>;
225 nvidia,dsi-n-suspend-cmd = <4>;
226 nvidia,dsi-pkt-seq =
227 <CMD_VS LEN_SHORT PKT_LP LINE_STOP>,
228 <CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
229 <CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
230 <CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
231 <CMD_HS LEN_SHORT PKT_LP LINE_STOP>,
232 <CMD_HS LEN_SHORT CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;
233 nvdia,panel-rst-gpio = <0x11 0x7b 0x1>;
234 nvidia,panel-bl-pwm-gpio = <0x11 0xa0 0x1>;
235 nvidia,panel-bl-en-gpio = <0x11 0xa3 0x1>;
236 nvidia,en-vmm-vpp-with-i2c-config;
237 disp-default-out {
238 nvidia,out-type = <TEGRA_DC_OUT_DSI>;
239 nvidia,out-width = <107>;
240 nvidia,out-height = <172>;
241 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
242 nvidia,out-parent-clk = "pll_d_out0";
243 nvidia,out-xres = <1200>;
244 nvidia,out-yres = <1920>;
245 };
246 display-timings {
247 1200x1920-32-60Hz {
248 clock-frequency = <193224000>;
249 hactive = <1200>;
250 vactive = <1920>;
251 hfront-porch = <107>;
252 hback-porch = <20>;
253 hsync-len = <1>;
254 vfront-porch = <497>;
255 vback-porch = <7>;
256 vsync-len = <1>;
257 nvidia,h-ref-to-sync = <1>;
258 nvidia,v-ref-to-sync = <11>;
259 };
260 };
261 smartdimmer {
262 status = "disabled";
263 nvidia,use-auto-pwm = <0>;
264 nvidia,hw-update-delay = <0>;
265 nvidia,bin-width = <0xffffffff>;
266 nvidia,aggressiveness = <5>;
267 nvidia,use-vid-luma = <0>;
268 nvidia,phase-in-settings = <0>;
269 nvidia,phase-in-adjustments = <0>;
270 nvidia,k-limit-enable = <1>;
271 nvidia,k-limit = <200>;
272 nvidia,sd-window-enable = <0>;
273 nvidia,soft-clipping-enable= <1>;
274 nvidia,soft-clipping-threshold = <128>;
275 nvidia,smooth-k-enable = <1>;
276 nvidia,smooth-k-incr = <4>;
277 nvidia,coeff = <5 9 2>;
278 nvidia,fc = <0 0>;
279 nvidia,blp = <1024 255>;
280 nvidia,bltf = <57 65 73 82
281 92 103 114 125
282 138 150 164 178
283 193 208 224 241>;
284 nvidia,lut = <255 255 255
285 199 199 199
286 153 153 153
287 116 116 116
288 85 85 85
289 59 59 59
290 36 36 36
291 17 17 17
292 0 0 0>;
293 nvidia,use-vpulse2 = <1>;
294 nvidia,bl-device-name = "pwm-backlight";
295 };
296 nvdisp-cmu {
297 nvidia,panel-csc = <0xd581 0x2979 0xc5 0x0 0x831 0xcac1 0x20c 0x0 0x189 0x625 0xcc4a 0x0>;
298 nvidia,cmu-lut = <0x6000 0x6000 0x6000 0x6191 0x6191 0x6191 0x6322 0x6322 0x6322
299 0x643b 0x643b 0x643b 0x64ba 0x64ba 0x64ba 0x6539 0x6539 0x6539
300 0x65b8 0x65b8 0x65b8 0x6637 0x6637 0x6637 0x66b6 0x66b6 0x66b6
301 0x6735 0x6735 0x6735 0x67b4 0x67b4 0x67b4 0x6826 0x6826 0x6826
302 0x687d 0x687d 0x687d 0x68d4 0x68d4 0x68d4 0x692b 0x692b 0x692b
303 0x6983 0x6983 0x6983 0x69da 0x69da 0x69da 0x6a31 0x6a31 0x6a31
304 0x6a88 0x6a88 0x6a88 0x6ae0 0x6ae0 0x6ae0 0x6b37 0x6b37 0x6b37
305 0x6b8e 0x6b8e 0x6b8e 0x6be5 0x6be5 0x6be5 0x6c28 0x6c28 0x6c28
306 0x6c5b 0x6c5b 0x6c5b 0x6c8e 0x6c8e 0x6c8e 0x6cc1 0x6cc1 0x6cc1
307 0x6cf4 0x6cf4 0x6cf4 0x6d27 0x6d27 0x6d27 0x6d5a 0x6d5a 0x6d5a
308 0x6d8d 0x6d8d 0x6d8d 0x6dbf 0x6dbf 0x6dbf 0x6df2 0x6df2 0x6df2
309 0x6e25 0x6e25 0x6e25 0x6e58 0x6e58 0x6e58 0x6e8b 0x6e8b 0x6e8b
310 0x6ebe 0x6ebe 0x6ebe 0x6ef1 0x6ef1 0x6ef1 0x6f24 0x6f24 0x6f24
311 0x6f57 0x6f57 0x6f57 0x6f8a 0x6f8a 0x6f8a 0x6fbd 0x6fbd 0x6fbd
312 0x6ff0 0x6ff0 0x6ff0 0x701a 0x701a 0x701a 0x7037 0x7037 0x7037
313 0x7053 0x7053 0x7053 0x706f 0x706f 0x706f 0x708c 0x708c 0x708c
314 0x70a8 0x70a8 0x70a8 0x70c5 0x70c5 0x70c5 0x70e1 0x70e1 0x70e1
315 0x70fe 0x70fe 0x70fe 0x711a 0x711a 0x711a 0x7136 0x7136 0x7136
316 0x7153 0x7153 0x7153 0x716f 0x716f 0x716f 0x718c 0x718c 0x718c
317 0x71a8 0x71a8 0x71a8 0x71c4 0x71c4 0x71c4 0x71e1 0x71e1 0x71e1
318 0x71fd 0x71fd 0x71fd 0x721a 0x721a 0x721a 0x7236 0x7236 0x7236
319 0x7253 0x7253 0x7253 0x726f 0x726f 0x726f 0x728b 0x728b 0x728b
320 0x72a8 0x72a8 0x72a8 0x72c4 0x72c4 0x72c4 0x72e1 0x72e1 0x72e1
321 0x72fd 0x72fd 0x72fd 0x731a 0x731a 0x731a 0x7336 0x7336 0x7336
322 0x7352 0x7352 0x7352 0x736f 0x736f 0x736f 0x738b 0x738b 0x738b
323 0x73a8 0x73a8 0x73a8 0x73c4 0x73c4 0x73c4 0x73e1 0x73e1 0x73e1
324 0x73fd 0x73fd 0x73fd 0x741b 0x741b 0x741b 0x743f 0x743f 0x743f
325 0x7463 0x7463 0x7463 0x7486 0x7486 0x7486 0x74aa 0x74aa 0x74aa
326 0x74ce 0x74ce 0x74ce 0x74f2 0x74f2 0x74f2 0x7516 0x7516 0x7516
327 0x753a 0x753a 0x753a 0x755d 0x755d 0x755d 0x7581 0x7581 0x7581
328 0x75a5 0x75a5 0x75a5 0x75c9 0x75c9 0x75c9 0x75ed 0x75ed 0x75ed
329 0x7611 0x7611 0x7611 0x7634 0x7634 0x7634 0x7658 0x7658 0x7658
330 0x767c 0x767c 0x767c 0x76a0 0x76a0 0x76a0 0x76c4 0x76c4 0x76c4
331 0x76e8 0x76e8 0x76e8 0x770b 0x770b 0x770b 0x772f 0x772f 0x772f
332 0x7753 0x7753 0x7753 0x7777 0x7777 0x7777 0x779b 0x779b 0x779b
333 0x77bf 0x77bf 0x77bf 0x77e2 0x77e2 0x77e2 0x7806 0x7806 0x7806
334 0x7825 0x7825 0x7825 0x7840 0x7840 0x7840 0x785b 0x785b 0x785b
335 0x7876 0x7876 0x7876 0x7891 0x7891 0x7891 0x78ac 0x78ac 0x78ac
336 0x78c7 0x78c7 0x78c7 0x78e2 0x78e2 0x78e2 0x78fd 0x78fd 0x78fd
337 0x7918 0x7918 0x7918 0x7933 0x7933 0x7933 0x794e 0x794e 0x794e
338 0x7969 0x7969 0x7969 0x7984 0x7984 0x7984 0x799f 0x799f 0x799f
339 0x79ba 0x79ba 0x79ba 0x79d5 0x79d5 0x79d5 0x79f0 0x79f0 0x79f0
340 0x7a0b 0x7a0b 0x7a0b 0x7a26 0x7a26 0x7a26 0x7a41 0x7a41 0x7a41
341 0x7a5c 0x7a5c 0x7a5c 0x7a77 0x7a77 0x7a77 0x7a92 0x7a92 0x7a92
342 0x7aad 0x7aad 0x7aad 0x7ac8 0x7ac8 0x7ac8 0x7ae3 0x7ae3 0x7ae3
343 0x7afe 0x7afe 0x7afe 0x7b19 0x7b19 0x7b19 0x7b34 0x7b34 0x7b34
344 0x7b4f 0x7b4f 0x7b4f 0x7b6a 0x7b6a 0x7b6a 0x7b85 0x7b85 0x7b85
345 0x7ba0 0x7ba0 0x7ba0 0x7bbb 0x7bbb 0x7bbb 0x7bd5 0x7bd5 0x7bd5
346 0x7bf0 0x7bf0 0x7bf0 0x7c0b 0x7c0b 0x7c0b 0x7c23 0x7c23 0x7c23
347 0x7c35 0x7c35 0x7c35 0x7c47 0x7c47 0x7c47 0x7c59 0x7c59 0x7c59
348 0x7c6b 0x7c6b 0x7c6b 0x7c7d 0x7c7d 0x7c7d 0x7c90 0x7c90 0x7c90
349 0x7ca2 0x7ca2 0x7ca2 0x7cb4 0x7cb4 0x7cb4 0x7cc6 0x7cc6 0x7cc6
350 0x7cd8 0x7cd8 0x7cd8 0x7cea 0x7cea 0x7cea 0x7cfc 0x7cfc 0x7cfc
351 0x7d0f 0x7d0f 0x7d0f 0x7d21 0x7d21 0x7d21 0x7d33 0x7d33 0x7d33
352 0x7d45 0x7d45 0x7d45 0x7d57 0x7d57 0x7d57 0x7d69 0x7d69 0x7d69
353 0x7d7b 0x7d7b 0x7d7b 0x7d8e 0x7d8e 0x7d8e 0x7da0 0x7da0 0x7da0
354 0x7db2 0x7db2 0x7db2 0x7dc4 0x7dc4 0x7dc4 0x7dd6 0x7dd6 0x7dd6
355 0x7de8 0x7de8 0x7de8 0x7dfa 0x7dfa 0x7dfa 0x7e0d 0x7e0d 0x7e0d
356 0x7e1f 0x7e1f 0x7e1f 0x7e31 0x7e31 0x7e31 0x7e43 0x7e43 0x7e43
357 0x7e55 0x7e55 0x7e55 0x7e67 0x7e67 0x7e67 0x7e79 0x7e79 0x7e79
358 0x7e8c 0x7e8c 0x7e8c 0x7e9e 0x7e9e 0x7e9e 0x7eb0 0x7eb0 0x7eb0
359 0x7ec2 0x7ec2 0x7ec2 0x7ed4 0x7ed4 0x7ed4 0x7ee6 0x7ee6 0x7ee6
360 0x7ef8 0x7ef8 0x7ef8 0x7f0b 0x7f0b 0x7f0b 0x7f1d 0x7f1d 0x7f1d
361 0x7f2f 0x7f2f 0x7f2f 0x7f41 0x7f41 0x7f41 0x7f53 0x7f53 0x7f53
362 0x7f65 0x7f65 0x7f65 0x7f77 0x7f77 0x7f77 0x7f8a 0x7f8a 0x7f8a
363 0x7f9c 0x7f9c 0x7f9c 0x7fae 0x7fae 0x7fae 0x7fc0 0x7fc0 0x7fc0
364 0x7fd2 0x7fd2 0x7fd2 0x7fe4 0x7fe4 0x7fe4 0x7ff7 0x7ff7 0x7ff7
365 0x8009 0x8009 0x8009 0x801b 0x801b 0x801b 0x802b 0x802b 0x802b
366 0x803a 0x803a 0x803a 0x804a 0x804a 0x804a 0x8059 0x8059 0x8059
367 0x8069 0x8069 0x8069 0x8078 0x8078 0x8078 0x8087 0x8087 0x8087
368 0x8097 0x8097 0x8097 0x80a6 0x80a6 0x80a6 0x80b6 0x80b6 0x80b6
369 0x80c5 0x80c5 0x80c5 0x80d5 0x80d5 0x80d5 0x80e4 0x80e4 0x80e4
370 0x80f4 0x80f4 0x80f4 0x8103 0x8103 0x8103 0x8112 0x8112 0x8112
371 0x8122 0x8122 0x8122 0x8131 0x8131 0x8131 0x8141 0x8141 0x8141
372 0x8150 0x8150 0x8150 0x8160 0x8160 0x8160 0x816f 0x816f 0x816f
373 0x817e 0x817e 0x817e 0x818e 0x818e 0x818e 0x819d 0x819d 0x819d
374 0x81ad 0x81ad 0x81ad 0x81bc 0x81bc 0x81bc 0x81cc 0x81cc 0x81cc
375 0x81db 0x81db 0x81db 0x81eb 0x81eb 0x81eb 0x81fa 0x81fa 0x81fa
376 0x8209 0x8209 0x8209 0x8219 0x8219 0x8219 0x8228 0x8228 0x8228
377 0x8238 0x8238 0x8238 0x8247 0x8247 0x8247 0x8257 0x8257 0x8257
378 0x8266 0x8266 0x8266 0x8275 0x8275 0x8275 0x8285 0x8285 0x8285
379 0x8294 0x8294 0x8294 0x82a4 0x82a4 0x82a4 0x82b3 0x82b3 0x82b3
380 0x82c3 0x82c3 0x82c3 0x82d2 0x82d2 0x82d2 0x82e2 0x82e2 0x82e2
381 0x82f1 0x82f1 0x82f1 0x8300 0x8300 0x8300 0x8310 0x8310 0x8310
382 0x831f 0x831f 0x831f 0x832f 0x832f 0x832f 0x833e 0x833e 0x833e
383 0x834e 0x834e 0x834e 0x835d 0x835d 0x835d 0x836c 0x836c 0x836c
384 0x837c 0x837c 0x837c 0x838b 0x838b 0x838b 0x839b 0x839b 0x839b
385 0x83aa 0x83aa 0x83aa 0x83ba 0x83ba 0x83ba 0x83c9 0x83c9 0x83c9
386 0x83d8 0x83d8 0x83d8 0x83e8 0x83e8 0x83e8 0x83f7 0x83f7 0x83f7
387 0x8407 0x8407 0x8407 0x8416 0x8416 0x8416 0x8425 0x8425 0x8425
388 0x8431 0x8431 0x8431 0x843d 0x843d 0x843d 0x8449 0x8449 0x8449
389 0x8455 0x8455 0x8455 0x8462 0x8462 0x8462 0x846e 0x846e 0x846e
390 0x847a 0x847a 0x847a 0x8486 0x8486 0x8486 0x8492 0x8492 0x8492
391 0x849e 0x849e 0x849e 0x84aa 0x84aa 0x84aa 0x84b6 0x84b6 0x84b6
392 0x84c2 0x84c2 0x84c2 0x84ce 0x84ce 0x84ce 0x84da 0x84da 0x84da
393 0x84e7 0x84e7 0x84e7 0x84f3 0x84f3 0x84f3 0x84ff 0x84ff 0x84ff
394 0x850b 0x850b 0x850b 0x8517 0x8517 0x8517 0x8523 0x8523 0x8523
395 0x852f 0x852f 0x852f 0x853b 0x853b 0x853b 0x8547 0x8547 0x8547
396 0x8553 0x8553 0x8553 0x855f 0x855f 0x855f 0x856c 0x856c 0x856c
397 0x8578 0x8578 0x8578 0x8584 0x8584 0x8584 0x8590 0x8590 0x8590
398 0x859c 0x859c 0x859c 0x85a8 0x85a8 0x85a8 0x85b4 0x85b4 0x85b4
399 0x85c0 0x85c0 0x85c0 0x85cc 0x85cc 0x85cc 0x85d8 0x85d8 0x85d8
400 0x85e4 0x85e4 0x85e4 0x85f0 0x85f0 0x85f0 0x85fd 0x85fd 0x85fd
401 0x8609 0x8609 0x8609 0x8615 0x8615 0x8615 0x8621 0x8621 0x8621
402 0x862d 0x862d 0x862d 0x8639 0x8639 0x8639 0x8645 0x8645 0x8645
403 0x8651 0x8651 0x8651 0x865d 0x865d 0x865d 0x8669 0x8669 0x8669
404 0x8675 0x8675 0x8675 0x8682 0x8682 0x8682 0x868e 0x868e 0x868e
405 0x869a 0x869a 0x869a 0x86a6 0x86a6 0x86a6 0x86b2 0x86b2 0x86b2
406 0x86be 0x86be 0x86be 0x86ca 0x86ca 0x86ca 0x86d6 0x86d6 0x86d6
407 0x86e2 0x86e2 0x86e2 0x86ee 0x86ee 0x86ee 0x86fa 0x86fa 0x86fa
408 0x8707 0x8707 0x8707 0x8713 0x8713 0x8713 0x871f 0x871f 0x871f
409 0x872b 0x872b 0x872b 0x8737 0x8737 0x8737 0x8743 0x8743 0x8743
410 0x874f 0x874f 0x874f 0x875b 0x875b 0x875b 0x8767 0x8767 0x8767
411 0x8773 0x8773 0x8773 0x877f 0x877f 0x877f 0x878b 0x878b 0x878b
412 0x8798 0x8798 0x8798 0x87a4 0x87a4 0x87a4 0x87b0 0x87b0 0x87b0
413 0x87bc 0x87bc 0x87bc 0x87c8 0x87c8 0x87c8 0x87d4 0x87d4 0x87d4
414 0x87e0 0x87e0 0x87e0 0x87ec 0x87ec 0x87ec 0x87f8 0x87f8 0x87f8
415 0x8804 0x8804 0x8804 0x8810 0x8810 0x8810 0x881d 0x881d 0x881d
416 0x8829 0x8829 0x8829 0x8834 0x8834 0x8834 0x883f 0x883f 0x883f
417 0x884b 0x884b 0x884b 0x8856 0x8856 0x8856 0x8862 0x8862 0x8862
418 0x886d 0x886d 0x886d 0x8879 0x8879 0x8879 0x8884 0x8884 0x8884
419 0x8890 0x8890 0x8890 0x889b 0x889b 0x889b 0x88a6 0x88a6 0x88a6
420 0x88b2 0x88b2 0x88b2 0x88bd 0x88bd 0x88bd 0x88c9 0x88c9 0x88c9
421 0x88d4 0x88d4 0x88d4 0x88e0 0x88e0 0x88e0 0x88eb 0x88eb 0x88eb
422 0x88f6 0x88f6 0x88f6 0x8902 0x8902 0x8902 0x890d 0x890d 0x890d
423 0x8919 0x8919 0x8919 0x8924 0x8924 0x8924 0x8930 0x8930 0x8930
424 0x893b 0x893b 0x893b 0x8947 0x8947 0x8947 0x8952 0x8952 0x8952
425 0x895d 0x895d 0x895d 0x8969 0x8969 0x8969 0x8974 0x8974 0x8974
426 0x8980 0x8980 0x8980 0x898b 0x898b 0x898b 0x8997 0x8997 0x8997
427 0x89a2 0x89a2 0x89a2 0x89ae 0x89ae 0x89ae 0x89b9 0x89b9 0x89b9
428 0x89c4 0x89c4 0x89c4 0x89d0 0x89d0 0x89d0 0x89db 0x89db 0x89db
429 0x89e7 0x89e7 0x89e7 0x89f2 0x89f2 0x89f2 0x89fe 0x89fe 0x89fe
430 0x8a09 0x8a09 0x8a09 0x8a15 0x8a15 0x8a15 0x8a20 0x8a20 0x8a20
431 0x8a2b 0x8a2b 0x8a2b 0x8a37 0x8a37 0x8a37 0x8a42 0x8a42 0x8a42
432 0x8a4e 0x8a4e 0x8a4e 0x8a59 0x8a59 0x8a59 0x8a65 0x8a65 0x8a65
433 0x8a70 0x8a70 0x8a70 0x8a7b 0x8a7b 0x8a7b 0x8a87 0x8a87 0x8a87
434 0x8a92 0x8a92 0x8a92 0x8a9e 0x8a9e 0x8a9e 0x8aa9 0x8aa9 0x8aa9
435 0x8ab5 0x8ab5 0x8ab5 0x8ac0 0x8ac0 0x8ac0 0x8acc 0x8acc 0x8acc
436 0x8ad7 0x8ad7 0x8ad7 0x8ae2 0x8ae2 0x8ae2 0x8aee 0x8aee 0x8aee
437 0x8af9 0x8af9 0x8af9 0x8b05 0x8b05 0x8b05 0x8b10 0x8b10 0x8b10
438 0x8b1c 0x8b1c 0x8b1c 0x8b27 0x8b27 0x8b27 0x8b33 0x8b33 0x8b33
439 0x8b3e 0x8b3e 0x8b3e 0x8b49 0x8b49 0x8b49 0x8b55 0x8b55 0x8b55
440 0x8b60 0x8b60 0x8b60 0x8b6c 0x8b6c 0x8b6c 0x8b77 0x8b77 0x8b77
441 0x8b83 0x8b83 0x8b83 0x8b8e 0x8b8e 0x8b8e 0x8b99 0x8b99 0x8b99
442 0x8ba5 0x8ba5 0x8ba5 0x8bb0 0x8bb0 0x8bb0 0x8bbc 0x8bbc 0x8bbc
443 0x8bc7 0x8bc7 0x8bc7 0x8bd3 0x8bd3 0x8bd3 0x8bde 0x8bde 0x8bde
444 0x8bea 0x8bea 0x8bea 0x8bf5 0x8bf5 0x8bf5 0x8c00 0x8c00 0x8c00
445 0x8c0c 0x8c0c 0x8c0c 0x8c17 0x8c17 0x8c17 0x8c23 0x8c23 0x8c23
446 0x8c2e 0x8c2e 0x8c2e 0x8c38 0x8c38 0x8c38 0x8c43 0x8c43 0x8c43
447 0x8c4d 0x8c4d 0x8c4d 0x8c58 0x8c58 0x8c58 0x8c62 0x8c62 0x8c62
448 0x8c6c 0x8c6c 0x8c6c 0x8c77 0x8c77 0x8c77 0x8c81 0x8c81 0x8c81
449 0x8c8c 0x8c8c 0x8c8c 0x8c96 0x8c96 0x8c96 0x8ca0 0x8ca0 0x8ca0
450 0x8cab 0x8cab 0x8cab 0x8cb5 0x8cb5 0x8cb5 0x8cc0 0x8cc0 0x8cc0
451 0x8cca 0x8cca 0x8cca 0x8cd4 0x8cd4 0x8cd4 0x8cdf 0x8cdf 0x8cdf
452 0x8ce9 0x8ce9 0x8ce9 0x8cf4 0x8cf4 0x8cf4 0x8cfe 0x8cfe 0x8cfe
453 0x8d09 0x8d09 0x8d09 0x8d13 0x8d13 0x8d13 0x8d1d 0x8d1d 0x8d1d
454 0x8d28 0x8d28 0x8d28 0x8d32 0x8d32 0x8d32 0x8d3d 0x8d3d 0x8d3d
455 0x8d47 0x8d47 0x8d47 0x8d51 0x8d51 0x8d51 0x8d5c 0x8d5c 0x8d5c
456 0x8d66 0x8d66 0x8d66 0x8d71 0x8d71 0x8d71 0x8d7b 0x8d7b 0x8d7b
457 0x8d85 0x8d85 0x8d85 0x8d90 0x8d90 0x8d90 0x8d9a 0x8d9a 0x8d9a
458 0x8da5 0x8da5 0x8da5 0x8daf 0x8daf 0x8daf 0x8db9 0x8db9 0x8db9
459 0x8dc4 0x8dc4 0x8dc4 0x8dce 0x8dce 0x8dce 0x8dd9 0x8dd9 0x8dd9
460 0x8de3 0x8de3 0x8de3 0x8ded 0x8ded 0x8ded 0x8df8 0x8df8 0x8df8
461 0x8e02 0x8e02 0x8e02 0x8e0d 0x8e0d 0x8e0d 0x8e17 0x8e17 0x8e17
462 0x8e22 0x8e22 0x8e22 0x8e2c 0x8e2c 0x8e2c 0x8e36 0x8e36 0x8e36
463 0x8e41 0x8e41 0x8e41 0x8e4b 0x8e4b 0x8e4b 0x8e56 0x8e56 0x8e56
464 0x8e60 0x8e60 0x8e60 0x8e6a 0x8e6a 0x8e6a 0x8e75 0x8e75 0x8e75
465 0x8e7f 0x8e7f 0x8e7f 0x8e8a 0x8e8a 0x8e8a 0x8e94 0x8e94 0x8e94
466 0x8e9e 0x8e9e 0x8e9e 0x8ea9 0x8ea9 0x8ea9 0x8eb3 0x8eb3 0x8eb3
467 0x8ebe 0x8ebe 0x8ebe 0x8ec8 0x8ec8 0x8ec8 0x8ed2 0x8ed2 0x8ed2
468 0x8edd 0x8edd 0x8edd 0x8ee7 0x8ee7 0x8ee7 0x8ef2 0x8ef2 0x8ef2
469 0x8efc 0x8efc 0x8efc 0x8f07 0x8f07 0x8f07 0x8f11 0x8f11 0x8f11
470 0x8f1b 0x8f1b 0x8f1b 0x8f26 0x8f26 0x8f26 0x8f30 0x8f30 0x8f30
471 0x8f3b 0x8f3b 0x8f3b 0x8f45 0x8f45 0x8f45 0x8f4f 0x8f4f 0x8f4f
472 0x8f5a 0x8f5a 0x8f5a 0x8f64 0x8f64 0x8f64 0x8f6f 0x8f6f 0x8f6f
473 0x8f79 0x8f79 0x8f79 0x8f83 0x8f83 0x8f83 0x8f8e 0x8f8e 0x8f8e
474 0x8f98 0x8f98 0x8f98 0x8fa3 0x8fa3 0x8fa3 0x8fad 0x8fad 0x8fad
475 0x8fb7 0x8fb7 0x8fb7 0x8fc2 0x8fc2 0x8fc2 0x8fcc 0x8fcc 0x8fcc
476 0x8fd7 0x8fd7 0x8fd7 0x8fe1 0x8fe1 0x8fe1 0x8feb 0x8feb 0x8feb
477 0x8ff6 0x8ff6 0x8ff6 0x9000 0x9000 0x9000 0x900b 0x900b 0x900b
478 0x9015 0x9015 0x9015 0x9020 0x9020 0x9020 0x902a 0x902a 0x902a
479 0x9034 0x9034 0x9034 0x903e 0x903e 0x903e 0x9048 0x9048 0x9048
480 0x9052 0x9052 0x9052 0x905c 0x905c 0x905c 0x9066 0x9066 0x9066
481 0x9070 0x9070 0x9070 0x907a 0x907a 0x907a 0x9084 0x9084 0x9084
482 0x908e 0x908e 0x908e 0x9098 0x9098 0x9098 0x90a2 0x90a2 0x90a2
483 0x90ac 0x90ac 0x90ac 0x90b6 0x90b6 0x90b6 0x90c0 0x90c0 0x90c0
484 0x90ca 0x90ca 0x90ca 0x90d4 0x90d4 0x90d4 0x90de 0x90de 0x90de
485 0x90e8 0x90e8 0x90e8 0x90f2 0x90f2 0x90f2 0x90fc 0x90fc 0x90fc
486 0x9106 0x9106 0x9106 0x9110 0x9110 0x9110 0x911a 0x911a 0x911a
487 0x9123 0x9123 0x9123 0x912d 0x912d 0x912d 0x9137 0x9137 0x9137
488 0x9141 0x9141 0x9141 0x914b 0x914b 0x914b 0x9155 0x9155 0x9155
489 0x915f 0x915f 0x915f 0x9169 0x9169 0x9169 0x9173 0x9173 0x9173
490 0x917d 0x917d 0x917d 0x9187 0x9187 0x9187 0x9191 0x9191 0x9191
491 0x919b 0x919b 0x919b 0x91a5 0x91a5 0x91a5 0x91af 0x91af 0x91af
492 0x91b9 0x91b9 0x91b9 0x91c3 0x91c3 0x91c3 0x91cd 0x91cd 0x91cd
493 0x91d7 0x91d7 0x91d7 0x91e1 0x91e1 0x91e1 0x91eb 0x91eb 0x91eb
494 0x91f5 0x91f5 0x91f5 0x91ff 0x91ff 0x91ff 0x9209 0x9209 0x9209
495 0x9213 0x9213 0x9213 0x921d 0x921d 0x921d 0x9227 0x9227 0x9227
496 0x9231 0x9231 0x9231 0x923b 0x923b 0x923b 0x9245 0x9245 0x9245
497 0x924f 0x924f 0x924f 0x9259 0x9259 0x9259 0x9263 0x9263 0x9263
498 0x926d 0x926d 0x926d 0x9277 0x9277 0x9277 0x9281 0x9281 0x9281
499 0x928b 0x928b 0x928b 0x9295 0x9295 0x9295 0x929f 0x929f 0x929f
500 0x92a8 0x92a8 0x92a8 0x92b2 0x92b2 0x92b2 0x92bc 0x92bc 0x92bc
501 0x92c6 0x92c6 0x92c6 0x92d0 0x92d0 0x92d0 0x92da 0x92da 0x92da
502 0x92e4 0x92e4 0x92e4 0x92ee 0x92ee 0x92ee 0x92f8 0x92f8 0x92f8
503 0x9302 0x9302 0x9302 0x930c 0x930c 0x930c 0x9316 0x9316 0x9316
504 0x9320 0x9320 0x9320 0x932a 0x932a 0x932a 0x9334 0x9334 0x9334
505 0x933e 0x933e 0x933e 0x9348 0x9348 0x9348 0x9352 0x9352 0x9352
506 0x935c 0x935c 0x935c 0x9366 0x9366 0x9366 0x9370 0x9370 0x9370
507 0x937a 0x937a 0x937a 0x9384 0x9384 0x9384 0x938e 0x938e 0x938e
508 0x9398 0x9398 0x9398 0x93a2 0x93a2 0x93a2 0x93ac 0x93ac 0x93ac
509 0x93b6 0x93b6 0x93b6 0x93c0 0x93c0 0x93c0 0x93ca 0x93ca 0x93ca
510 0x93d4 0x93d4 0x93d4 0x93de 0x93de 0x93de 0x93e8 0x93e8 0x93e8
511 0x93f2 0x93f2 0x93f2 0x93fc 0x93fc 0x93fc 0x9406 0x9406 0x9406
512 0x9410 0x9410 0x9410 0x941a 0x941a 0x941a 0x9423 0x9423 0x9423
513 0x942d 0x942d 0x942d 0x9437 0x9437 0x9437 0x9440 0x9440 0x9440
514 0x9449 0x9449 0x9449 0x9451 0x9451 0x9451 0x945a 0x945a 0x945a
515 0x9463 0x9463 0x9463 0x946c 0x946c 0x946c 0x9475 0x9475 0x9475
516 0x947e 0x947e 0x947e 0x9486 0x9486 0x9486 0x948f 0x948f 0x948f
517 0x9498 0x9498 0x9498 0x94a1 0x94a1 0x94a1 0x94aa 0x94aa 0x94aa
518 0x94b3 0x94b3 0x94b3 0x94bb 0x94bb 0x94bb 0x94c4 0x94c4 0x94c4
519 0x94cd 0x94cd 0x94cd 0x94d6 0x94d6 0x94d6 0x94df 0x94df 0x94df
520 0x94e8 0x94e8 0x94e8 0x94f0 0x94f0 0x94f0 0x94f9 0x94f9 0x94f9
521 0x9502 0x9502 0x9502 0x950b 0x950b 0x950b 0x9514 0x9514 0x9514
522 0x951d 0x951d 0x951d 0x9525 0x9525 0x9525 0x952e 0x952e 0x952e
523 0x9537 0x9537 0x9537 0x9540 0x9540 0x9540 0x9549 0x9549 0x9549
524 0x9552 0x9552 0x9552 0x955a 0x955a 0x955a 0x9563 0x9563 0x9563
525 0x956c 0x956c 0x956c 0x9575 0x9575 0x9575 0x957e 0x957e 0x957e
526 0x9587 0x9587 0x9587 0x958f 0x958f 0x958f 0x9598 0x9598 0x9598
527 0x95a1 0x95a1 0x95a1 0x95aa 0x95aa 0x95aa 0x95b3 0x95b3 0x95b3
528 0x95bc 0x95bc 0x95bc 0x95c4 0x95c4 0x95c4 0x95cd 0x95cd 0x95cd
529 0x95d6 0x95d6 0x95d6 0x95df 0x95df 0x95df 0x95e8 0x95e8 0x95e8
530 0x95f1 0x95f1 0x95f1 0x95f9 0x95f9 0x95f9 0x9602 0x9602 0x9602
531 0x960b 0x960b 0x960b 0x9614 0x9614 0x9614 0x961d 0x961d 0x961d
532 0x9626 0x9626 0x9626 0x962e 0x962e 0x962e 0x9637 0x9637 0x9637
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535 0x9675 0x9675 0x9675 0x967e 0x967e 0x967e 0x9687 0x9687 0x9687
536 0x9690 0x9690 0x9690 0x9698 0x9698 0x9698 0x96a1 0x96a1 0x96a1
537 0x96aa 0x96aa 0x96aa 0x96b3 0x96b3 0x96b3 0x96bc 0x96bc 0x96bc
538 0x96c5 0x96c5 0x96c5 0x96cd 0x96cd 0x96cd 0x96d6 0x96d6 0x96d6
539 0x96df 0x96df 0x96df 0x96e8 0x96e8 0x96e8 0x96f1 0x96f1 0x96f1
540 0x96f9 0x96f9 0x96f9 0x9702 0x9702 0x9702 0x970b 0x970b 0x970b
541 0x9714 0x9714 0x9714 0x971d 0x971d 0x971d 0x9726 0x9726 0x9726
542 0x972e 0x972e 0x972e 0x9737 0x9737 0x9737 0x9740 0x9740 0x9740
543 0x9749 0x9749 0x9749 0x9752 0x9752 0x9752 0x975b 0x975b 0x975b
544 0x9763 0x9763 0x9763 0x976c 0x976c 0x976c 0x9775 0x9775 0x9775
545 0x977e 0x977e 0x977e 0x9787 0x9787 0x9787 0x9790 0x9790 0x9790
546 0x9798 0x9798 0x9798 0x97a1 0x97a1 0x97a1 0x97aa 0x97aa 0x97aa
547 0x97b3 0x97b3 0x97b3 0x97bc 0x97bc 0x97bc 0x97c5 0x97c5 0x97c5
548 0x97cd 0x97cd 0x97cd 0x97d6 0x97d6 0x97d6 0x97df 0x97df 0x97df
549 0x97e8 0x97e8 0x97e8 0x97f1 0x97f1 0x97f1 0x97fa 0x97fa 0x97fa
550 0x9802 0x9802 0x9802 0x980b 0x980b 0x980b 0x9814 0x9814 0x9814
551 0x981d 0x981d 0x981d 0x9826 0x9826 0x9826 0x982f 0x982f 0x982f
552 0x9837 0x9837 0x9837 0x983f 0x983f 0x983f 0x9847 0x9847 0x9847
553 0x984f 0x984f 0x984f 0x9857 0x9857 0x9857 0x985f 0x985f 0x985f
554 0x9867 0x9867 0x9867 0x986e 0x986e 0x986e 0x9876 0x9876 0x9876
555 0x987e 0x987e 0x987e 0x9886 0x9886 0x9886 0x988e 0x988e 0x988e
556 0x9896 0x9896 0x9896 0x989e 0x989e 0x989e 0x98a5 0x98a5 0x98a5
557 0x98ad 0x98ad 0x98ad 0x98b5 0x98b5 0x98b5 0x98bd 0x98bd 0x98bd
558 0x98c5 0x98c5 0x98c5 0x98cd 0x98cd 0x98cd 0x98d5 0x98d5 0x98d5
559 0x98dc 0x98dc 0x98dc 0x98e4 0x98e4 0x98e4 0x98ec 0x98ec 0x98ec
560 0x98f4 0x98f4 0x98f4 0x98fc 0x98fc 0x98fc 0x9904 0x9904 0x9904
561 0x990c 0x990c 0x990c 0x9913 0x9913 0x9913 0x991b 0x991b 0x991b
562 0x9923 0x9923 0x9923 0x992b 0x992b 0x992b 0x9933 0x9933 0x9933
563 0x993b 0x993b 0x993b 0x9943 0x9943 0x9943 0x994a 0x994a 0x994a
564 0x9952 0x9952 0x9952 0x995a 0x995a 0x995a 0x9962 0x9962 0x9962
565 0x996a 0x996a 0x996a 0x9972 0x9972 0x9972 0x997a 0x997a 0x997a
566 0x9981 0x9981 0x9981 0x9989 0x9989 0x9989 0x9991 0x9991 0x9991
567 0x9999 0x9999 0x9999 0x99a1 0x99a1 0x99a1 0x99a9 0x99a9 0x99a9
568 0x99b1 0x99b1 0x99b1 0x99b8 0x99b8 0x99b8 0x99c0 0x99c0 0x99c0
569 0x99c8 0x99c8 0x99c8 0x99d0 0x99d0 0x99d0 0x99d8 0x99d8 0x99d8
570 0x99e0 0x99e0 0x99e0 0x99e8 0x99e8 0x99e8 0x99ef 0x99ef 0x99ef
571 0x99f7 0x99f7 0x99f7 0x99ff 0x99ff 0x99ff 0x9a07 0x9a07 0x9a07
572 0x9a0f 0x9a0f 0x9a0f 0x9a17 0x9a17 0x9a17 0x9a1f 0x9a1f 0x9a1f
573 0x9a26 0x9a26 0x9a26 0x9a2e 0x9a2e 0x9a2e 0x9a36 0x9a36 0x9a36
574 0x9a3e 0x9a3e 0x9a3e 0x9a46 0x9a46 0x9a46 0x9a4e 0x9a4e 0x9a4e
575 0x9a56 0x9a56 0x9a56 0x9a5d 0x9a5d 0x9a5d 0x9a65 0x9a65 0x9a65
576 0x9a6d 0x9a6d 0x9a6d 0x9a75 0x9a75 0x9a75 0x9a7d 0x9a7d 0x9a7d
577 0x9a85 0x9a85 0x9a85 0x9a8d 0x9a8d 0x9a8d 0x9a94 0x9a94 0x9a94
578 0x9a9c 0x9a9c 0x9a9c 0x9aa4 0x9aa4 0x9aa4 0x9aac 0x9aac 0x9aac
579 0x9ab4 0x9ab4 0x9ab4 0x9abc 0x9abc 0x9abc 0x9ac4 0x9ac4 0x9ac4
580 0x9acb 0x9acb 0x9acb 0x9ad3 0x9ad3 0x9ad3 0x9adb 0x9adb 0x9adb
581 0x9ae3 0x9ae3 0x9ae3 0x9aeb 0x9aeb 0x9aeb 0x9af3 0x9af3 0x9af3
582 0x9afb 0x9afb 0x9afb 0x9b02 0x9b02 0x9b02 0x9b0a 0x9b0a 0x9b0a
583 0x9b12 0x9b12 0x9b12 0x9b1a 0x9b1a 0x9b1a 0x9b22 0x9b22 0x9b22
584 0x9b2a 0x9b2a 0x9b2a 0x9b32 0x9b32 0x9b32 0x9b39 0x9b39 0x9b39
585 0x9b41 0x9b41 0x9b41 0x9b49 0x9b49 0x9b49 0x9b51 0x9b51 0x9b51
586 0x9b59 0x9b59 0x9b59 0x9b61 0x9b61 0x9b61 0x9b69 0x9b69 0x9b69
587 0x9b70 0x9b70 0x9b70 0x9b78 0x9b78 0x9b78 0x9b80 0x9b80 0x9b80
588 0x9b88 0x9b88 0x9b88 0x9b90 0x9b90 0x9b90 0x9b98 0x9b98 0x9b98
589 0x9ba0 0x9ba0 0x9ba0 0x9ba7 0x9ba7 0x9ba7 0x9baf 0x9baf 0x9baf
590 0x9bb7 0x9bb7 0x9bb7 0x9bbf 0x9bbf 0x9bbf 0x9bc7 0x9bc7 0x9bc7
591 0x9bcf 0x9bcf 0x9bcf 0x9bd7 0x9bd7 0x9bd7 0x9bde 0x9bde 0x9bde
592 0x9be6 0x9be6 0x9be6 0x9bee 0x9bee 0x9bee 0x9bf6 0x9bf6 0x9bf6
593 0x9bfe 0x9bfe 0x9bfe 0x9c06 0x9c06 0x9c06 0x9c0e 0x9c0e 0x9c0e
594 0x9c15 0x9c15 0x9c15 0x9c1d 0x9c1d 0x9c1d 0x9c25 0x9c25 0x9c25
595 0x9c2d 0x9c2d 0x9c2d 0x9c35 0x9c35 0x9c35 0x9c3d 0x9c3d 0x9c3d
596 0x9c44 0x9c44 0x9c44 0x9c4b 0x9c4b 0x9c4b 0x9c53 0x9c53 0x9c53
597 0x9c5a 0x9c5a 0x9c5a 0x9c61 0x9c61 0x9c61 0x9c69 0x9c69 0x9c69
598 0x9c70 0x9c70 0x9c70 0x9c77 0x9c77 0x9c77 0x9c7f 0x9c7f 0x9c7f
599 0x9c86 0x9c86 0x9c86 0x9c8d 0x9c8d 0x9c8d 0x9c95 0x9c95 0x9c95
600 0x9c9c 0x9c9c 0x9c9c 0x9ca3 0x9ca3 0x9ca3 0x9cab 0x9cab 0x9cab
601 0x9cb2 0x9cb2 0x9cb2 0x9cb9 0x9cb9 0x9cb9 0x9cc1 0x9cc1 0x9cc1
602 0x9cc8 0x9cc8 0x9cc8 0x9ccf 0x9ccf 0x9ccf 0x9cd7 0x9cd7 0x9cd7
603 0x9cde 0x9cde 0x9cde 0x9ce5 0x9ce5 0x9ce5 0x9ced 0x9ced 0x9ced
604 0x9cf4 0x9cf4 0x9cf4 0x9cfb 0x9cfb 0x9cfb 0x9d03 0x9d03 0x9d03
605 0x9d0a 0x9d0a 0x9d0a 0x9d12 0x9d12 0x9d12 0x9d19 0x9d19 0x9d19
606 0x9d20 0x9d20 0x9d20 0x9d28 0x9d28 0x9d28 0x9d2f 0x9d2f 0x9d2f
607 0x9d36 0x9d36 0x9d36 0x9d3e 0x9d3e 0x9d3e 0x9d45 0x9d45 0x9d45
608 0x9d4c 0x9d4c 0x9d4c 0x9d54 0x9d54 0x9d54 0x9d5b 0x9d5b 0x9d5b
609 0x9d62 0x9d62 0x9d62 0x9d6a 0x9d6a 0x9d6a 0x9d71 0x9d71 0x9d71
610 0x9d78 0x9d78 0x9d78 0x9d80 0x9d80 0x9d80 0x9d87 0x9d87 0x9d87
611 0x9d8e 0x9d8e 0x9d8e 0x9d96 0x9d96 0x9d96 0x9d9d 0x9d9d 0x9d9d
612 0x9da4 0x9da4 0x9da4 0x9dac 0x9dac 0x9dac 0x9db3 0x9db3 0x9db3
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614 0x9dd0 0x9dd0 0x9dd0 0x9dd8 0x9dd8 0x9dd8 0x9ddf 0x9ddf 0x9ddf
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619 0x9e3f 0x9e3f 0x9e3f 0x9e46 0x9e46 0x9e46 0x9e4d 0x9e4d 0x9e4d
620 0x9e55 0x9e55 0x9e55 0x9e5c 0x9e5c 0x9e5c 0x9e63 0x9e63 0x9e63
621 0x9e6b 0x9e6b 0x9e6b 0x9e72 0x9e72 0x9e72 0x9e79 0x9e79 0x9e79
622 0x9e81 0x9e81 0x9e81 0x9e88 0x9e88 0x9e88 0x9e8f 0x9e8f 0x9e8f
623 0x9e97 0x9e97 0x9e97 0x9e9e 0x9e9e 0x9e9e 0x9ea5 0x9ea5 0x9ea5
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625 0x9ec3 0x9ec3 0x9ec3 0x9eca 0x9eca 0x9eca 0x9ed1 0x9ed1 0x9ed1
626 0x9ed9 0x9ed9 0x9ed9 0x9ee0 0x9ee0 0x9ee0 0x9ee7 0x9ee7 0x9ee7
627 0x9eef 0x9eef 0x9eef 0x9ef6 0x9ef6 0x9ef6 0x9efd 0x9efd 0x9efd
628 0x9f05 0x9f05 0x9f05 0x9f0c 0x9f0c 0x9f0c 0x9f14 0x9f14 0x9f14
629 0x9f1b 0x9f1b 0x9f1b 0x9f22 0x9f22 0x9f22 0x9f2a 0x9f2a 0x9f2a
630 0x9f31 0x9f31 0x9f31 0x9f38 0x9f38 0x9f38 0x9f40 0x9f40 0x9f40
631 0x9f47 0x9f47 0x9f47 0x9f4e 0x9f4e 0x9f4e 0x9f56 0x9f56 0x9f56
632 0x9f5d 0x9f5d 0x9f5d 0x9f64 0x9f64 0x9f64 0x9f6c 0x9f6c 0x9f6c
633 0x9f73 0x9f73 0x9f73 0x9f7a 0x9f7a 0x9f7a 0x9f82 0x9f82 0x9f82
634 0x9f89 0x9f89 0x9f89 0x9f90 0x9f90 0x9f90 0x9f98 0x9f98 0x9f98
635 0x9f9f 0x9f9f 0x9f9f 0x9fa6 0x9fa6 0x9fa6 0x9fae 0x9fae 0x9fae
636 0x9fb5 0x9fb5 0x9fb5 0x9fbc 0x9fbc 0x9fbc 0x9fc4 0x9fc4 0x9fc4
637 0x9fcb 0x9fcb 0x9fcb 0x9fd2 0x9fd2 0x9fd2 0x9fda 0x9fda 0x9fda
638 0x9fe1 0x9fe1 0x9fe1 0x9fe8 0x9fe8 0x9fe8 0x9ff0 0x9ff0 0x9ff0
639 0x9ff7 0x9ff7 0x9ff7 0x9fff 0x9fff 0x9fff>;
640 };
641 };
642 };
643 };
644 backlight {
645 panel-a-edp-1080p-14-0-bl {
646 status = "okay";
647 compatible = "a-edp,1080p-14-0-bl";
648 max-brightness = <255>;
649 default-brightness = <224>;
650 bl-measured = < 0 0 1 2 3 4 5 6
651 7 8 9 9 10 11 12 13
652 13 14 15 16 17 17 18 19
653 20 21 22 22 23 24 25 26
654 27 27 28 29 30 31 32 32
655 33 34 35 36 37 37 38 39
656 40 41 42 42 43 44 45 46
657 47 48 48 49 50 51 52 53
658 54 55 56 57 57 58 59 60
659 61 62 63 64 65 66 67 68
660 69 70 71 71 72 73 74 75
661 76 77 77 78 79 80 81 82
662 83 84 85 87 88 89 90 91
663 92 93 94 95 96 97 98 99
664 100 101 102 103 104 105 106 107
665 108 109 110 111 112 113 115 116
666 117 118 119 120 121 122 123 124
667 125 126 127 128 129 130 131 132
668 133 134 135 136 137 138 139 141
669 142 143 144 146 147 148 149 151
670 152 153 154 155 156 157 158 158
671 159 160 161 162 163 165 166 167
672 168 169 170 171 172 173 174 176
673 177 178 179 180 182 183 184 185
674 186 187 188 189 190 191 192 194
675 195 196 197 198 199 200 201 202
676 203 204 205 206 207 208 209 210
677 211 212 213 214 215 216 217 219
678 220 221 222 224 225 226 227 229
679 230 231 232 233 234 235 236 238
680 239 240 241 242 243 244 245 246
681 247 248 249 250 251 252 253 255 >;
682 };
683 };
684};
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-hdmi.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-hdmi.dtsi
deleted file mode 100644
index 78eadf858..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-hdmi.dtsi
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * arch/arm64/boot/dts/tegra186-sim-hdmi.dtsi
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20
21#include <dt-bindings/display/tegra-dc.h>
22
23/ {
24 host1x {
25 sor1 {
26 status = "okay";
27 /*nvidia,ddc-i2c-bus = <&hdmi_ddc>;*/
28 /*nvidia,hpd-gpio = <&tegra_gpio 0xFFFFFFFF 1>;*/ /* hotplug less */
29 hdmi-display {
30 status = "okay";
31 compatible = "hdmi,display";
32 disp-default-out {
33 nvidia,out-type = <TEGRA_DC_OUT_HDMI>;
34 nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_LOW>;
35 nvidia,out-parent-clk = "plld2";
36 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
37 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
38 nvidia,out-xres = <720>;
39 nvidia,out-yres = <480>;
40 };
41 display-timings {
42 720x480-32 {
43 clock-frequency = <27000000>;
44 hactive = <720>;
45 vactive = <480>;
46 hfront-porch = <26>;
47 hback-porch = <80>;
48 hsync-len = <32>;
49 vfront-porch = <9>;
50 vback-porch = <26>;
51 vsync-len = <10>;
52 nvidia,h-ref-to-sync = <1>;
53 nvidia,v-ref-to-sync = <1>;
54 };
55 };
56 tmds-config {
57 tmds-cfg@0 {
58 version = <1 0>;
59 pclk = <27000000>;
60 pll0 = <0x01003010>;
61 pll1 = <0x00301b00>;
62 pe-current = <0x00000000>;
63 drive-current = <0x1c1c1c1c>;
64 peak-current = <0x00000000>;
65 pad-ctls0-mask = <0xfffff0ff>;
66 pad-ctls0-setting = <0x00000400>;
67 };
68 tmds-cfg@1 {
69 version = <1 0>;
70 pclk = <74250000>;
71 pll0 = <0x01003110>;
72 pll1 = <0x00301500>;
73 pe-current = <0x00000000>;
74 drive-current = <0x23232323>;
75 peak-current = <0x00000000>;
76 pad-ctls0-mask = <0xfffff0ff>;
77 pad-ctls0-setting = <0x00000400>;
78 };
79 tmds-cfg@2 {
80 version = <1 0>;
81 pclk = <148500000>;
82 pll0 = <0x01003310>;
83 pll1 = <0x10300f00>;
84 pe-current = <0x00000000>;
85 drive-current = <0x2a2c2c2a>;
86 peak-current = <0x00000000>;
87 pad-ctls0-mask = <0xfffff0ff>;
88 pad-ctls0-setting = <0x00000400>;
89 };
90 tmds-cfg@3 {
91 version = <1 0>;
92 pclk = <0x7fffffff>;
93 pll0 = <0x01003f10>;
94 pll1 = <0x10300700>;
95 pe-current = <0x00000000>;
96 drive-current = <0x30323333>;
97 peak-current = <0x10101010>;
98 pad-ctls0-mask = <0xfffff0ff>;
99 pad-ctls0-setting = <0x00000600>;
100 };
101 };
102 };
103 };
104
105 sor {
106 status = "okay";
107 hdmi-display {
108 status = "okay";
109 compatible = "hdmi,display";
110 disp-default-out {
111 nvidia,out-type = <TEGRA_DC_OUT_HDMI>;
112 nvidia,out-flags = <TEGRA_DC_OUT_HOTPLUG_LOW>;
113 nvidia,out-parent-clk = "plld2";
114 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
115 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
116 nvidia,out-xres = <720>;
117 nvidia,out-yres = <480>;
118 };
119 display-timings {
120 720x480-32 {
121 clock-frequency = <27000000>;
122 hactive = <720>;
123 vactive = <480>;
124 hfront-porch = <26>;
125 hback-porch = <80>;
126 hsync-len = <32>;
127 vfront-porch = <9>;
128 vback-porch = <26>;
129 vsync-len = <10>;
130 nvidia,h-ref-to-sync = <1>;
131 nvidia,v-ref-to-sync = <1>;
132 };
133 };
134 tmds-config {
135 tmds-cfg@0 {
136 version = <1 0>;
137 pclk = <27000000>;
138 pll0 = <0x01003010>;
139 pll1 = <0x00301b00>;
140 pe-current = <0x00000000>;
141 drive-current = <0x1c1c1c1c>;
142 peak-current = <0x00000000>;
143 pad-ctls0-mask = <0xfffff0ff>;
144 pad-ctls0-setting = <0x00000400>;
145 };
146 tmds-cfg@1 {
147 version = <1 0>;
148 pclk = <74250000>;
149 pll0 = <0x01003110>;
150 pll1 = <0x00301500>;
151 pe-current = <0x00000000>;
152 drive-current = <0x23232323>;
153 peak-current = <0x00000000>;
154 pad-ctls0-mask = <0xfffff0ff>;
155 pad-ctls0-setting = <0x00000400>;
156 };
157 tmds-cfg@2 {
158 version = <1 0>;
159 pclk = <148500000>;
160 pll0 = <0x01003310>;
161 pll1 = <0x10300f00>;
162 pe-current = <0x00000000>;
163 drive-current = <0x2a2c2c2a>;
164 peak-current = <0x00000000>;
165 pad-ctls0-mask = <0xfffff0ff>;
166 pad-ctls0-setting = <0x00000400>;
167 };
168 tmds-cfg@3 {
169 version = <1 0>;
170 pclk = <0x7fffffff>;
171 pll0 = <0x01003f10>;
172 pll1 = <0x10300700>;
173 pe-current = <0x00000000>;
174 drive-current = <0x30323333>;
175 peak-current = <0x10101010>;
176 pad-ctls0-mask = <0xfffff0ff>;
177 pad-ctls0-setting = <0x00000600>;
178 };
179 };
180 };
181 };
182 };
183 /*hdmi_ddc: i2c@7000c700 {
184 clock-frequency = <100000>;
185 };*/
186};
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-private.dts b/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-private.dts
deleted file mode 100644
index 217f84c94..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-private.dts
+++ /dev/null
@@ -1,408 +0,0 @@
1/*
2 * arch/arm64/boot/dts/tegra186-sim-private.dts
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21/dts-v1/;
22
23/memreserve/ 0x80000000 0x00010000;
24
25#include "tegra186-soc/tegra186-soc-sim-fpga.dtsi"
26#include "tegra186-soc/tegra186-cpus-2D4A.dtsi"
27#include "panel-sim.dtsi"
28#include "tegra186-sim-hdmi.dtsi"
29#include "tegra186-platforms/tegra186-sunstreaker-eqos.dtsi"
30#include <dt-bindings/sound/tegra-asoc-alt.h>
31
32/ {
33 model = "t186ref";
34 compatible = "nvidia,tegra186";
35
36 reserved-memory {
37 vpr: vpr-carveout {
38 status = "disabled";
39 };
40 };
41
42 chosen {
43 bootargs ="mem=1024M@2048M console=ttyS0,115200 earlyprintk=uart8250-32bit,0x03100000";
44 stdout-path = &uarta;
45 };
46
47 /* chosen */
48
49 firmware {
50 android {
51 compatible = "android,firmware";
52 hardware = "t186ref";
53 };
54 };
55
56 memory@80000000 {
57 device_type = "memory";
58 reg = < 0x0 0x80000000 0x0 0xc0000000 >;
59 };
60
61 clock@5000000 {
62 status = "disabled";
63 };
64
65 ethernet@0x7ffff000 {
66 compatible = "smsc,lan9115";
67 reg = <0x0 0x03b40000 0x0 0x00000100>;
68 interrupts = <0 218 0x4>;
69 reg-io-width = <4>;
70 smsc,irq-active-high;
71 smsc,irq-push-pull;
72 };
73
74 asim {
75 compatible = "nvidia,tegra210-asim";
76 reg = < 0x0 0x03b41000 0x0 0x00001000 >;
77 };
78
79 adma@2930000 {
80 dma-channels = <10>;
81 status = "disabled";
82 };
83
84 adsp_audio {
85 compr-ops = <1>;
86 num-plugin = <4>;
87 plugin-info-1 {
88 plugin-name = "mp3-dec1";
89 firmware-name = "nvmp3dec.elf";
90 widget-name = "MP3-DEC1";
91 };
92 plugin-info-2 {
93 plugin-name = "spkprot";
94 firmware-name = "nvspkprot.elf";
95 widget-name = "SPKPROT-SW";
96 };
97 plugin-info-3 {
98 plugin-name = "src";
99 firmware-name = "nvsrc.elf";
100 widget-name = "SRC";
101 };
102 plugin-info-4 {
103 plugin-name = "aac-dec1";
104 firmware-name = "nvaacdec.elf";
105 widget-name = "AAC-DEC1";
106 };
107 };
108
109 ahub {
110 i2s@02901000 {
111 fsync-width = <31>;
112 };
113
114 i2s@02901100 {
115 fsync-width = <31>;
116 };
117
118 i2s@02901200 {
119 fsync-width = <31>;
120 };
121
122 i2s@02901300 {
123 fsync-width = <31>;
124 };
125
126 i2s@02901400 {
127 fsync-width = <31>;
128 };
129
130 i2s@02901500 {
131 fsync-width = <31>;
132 };
133 };
134
135 sound_ref {
136 compatible = "nvidia,tegra-audio-t186ref";
137 nvidia,model = "tegra-snd-t186ref";
138 nvidia,num-codec-link = <5>;
139 nvidia,num-amx = <1>;
140 nvidia,num-adx = <1>;
141 nvidia,amx-slot-size = <32 32>;
142 nvidia,adx-slot-size = <32 32>;
143 nvidia,addr-max9485 = <0>;
144 nvidia,amx-slot-map = <
145 /* jack 0 */
146 TDM_SLOT_MAP(0, 0, 0)
147 TDM_SLOT_MAP(0, 0, 0)
148 TDM_SLOT_MAP(0, 1, 0)
149 TDM_SLOT_MAP(0, 1, 1)
150 TDM_SLOT_MAP(0, 0, 0)
151 TDM_SLOT_MAP(0, 0, 0)
152 TDM_SLOT_MAP(0, 2, 0)
153 TDM_SLOT_MAP(0, 2, 1)
154 /* jack 1 */
155 TDM_SLOT_MAP(0, 0, 0)
156 TDM_SLOT_MAP(0, 0, 0)
157 TDM_SLOT_MAP(1, 1, 0)
158 TDM_SLOT_MAP(1, 1, 1)
159 TDM_SLOT_MAP(0, 0, 0)
160 TDM_SLOT_MAP(0, 0, 0)
161 TDM_SLOT_MAP(1, 2, 0)
162 TDM_SLOT_MAP(1, 2, 1)
163 /* jack 2 */
164 TDM_SLOT_MAP(0, 0, 0)
165 TDM_SLOT_MAP(0, 0, 0)
166 TDM_SLOT_MAP(2, 1, 0)
167 TDM_SLOT_MAP(2, 1, 1)
168 TDM_SLOT_MAP(0, 0, 0)
169 TDM_SLOT_MAP(0, 0, 0)
170 TDM_SLOT_MAP(2, 2, 0)
171 TDM_SLOT_MAP(2, 2, 1)
172 /* jack 3 */
173 TDM_SLOT_MAP(0, 0, 0)
174 TDM_SLOT_MAP(0, 0, 0)
175 TDM_SLOT_MAP(3, 1, 0)
176 TDM_SLOT_MAP(3, 1, 1)
177 TDM_SLOT_MAP(0, 0, 0)
178 TDM_SLOT_MAP(0, 0, 0)
179 TDM_SLOT_MAP(3, 2, 0)
180 TDM_SLOT_MAP(3, 2, 1)>;
181 nvidia,adx-slot-map = <
182 /* jack 0 */
183 TDM_SLOT_MAP(0, 0, 0)
184 TDM_SLOT_MAP(0, 0, 0)
185 TDM_SLOT_MAP(0, 1, 0)
186 TDM_SLOT_MAP(0, 1, 1)
187 TDM_SLOT_MAP(0, 0, 0)
188 TDM_SLOT_MAP(0, 0, 0)
189 TDM_SLOT_MAP(0, 2, 0)
190 TDM_SLOT_MAP(0, 2, 1)
191 /* jack 1 */
192 TDM_SLOT_MAP(0, 0, 0)
193 TDM_SLOT_MAP(0, 0, 0)
194 TDM_SLOT_MAP(1, 1, 0)
195 TDM_SLOT_MAP(1, 1, 1)
196 TDM_SLOT_MAP(0, 0, 0)
197 TDM_SLOT_MAP(0, 0, 0)
198 TDM_SLOT_MAP(1, 2, 0)
199 TDM_SLOT_MAP(1, 2, 1)
200 /* jack 2 */
201 TDM_SLOT_MAP(0, 0, 0)
202 TDM_SLOT_MAP(0, 0, 0)
203 TDM_SLOT_MAP(2, 1, 0)
204 TDM_SLOT_MAP(2, 1, 1)
205 TDM_SLOT_MAP(0, 0, 0)
206 TDM_SLOT_MAP(0, 0, 0)
207 TDM_SLOT_MAP(2, 2, 0)
208 TDM_SLOT_MAP(2, 2, 1)
209 /* jack 3 */
210 TDM_SLOT_MAP(0, 0, 0)
211 TDM_SLOT_MAP(0, 0, 0)
212 TDM_SLOT_MAP(3, 1, 0)
213 TDM_SLOT_MAP(3, 1, 1)
214 TDM_SLOT_MAP(0, 0, 0)
215 TDM_SLOT_MAP(0, 0, 0)
216 TDM_SLOT_MAP(3, 2, 0)
217 TDM_SLOT_MAP(3, 2, 1)>;
218
219 nvidia,audio-routing =
220 "Headphone-x", "x OUT",
221 "x IN", "LineIn-x";
222
223 nvidia,xbar = <&tegra_axbar>;
224
225 nvidia,dai-link-1 {
226 link-name = "spdif-dit-0";
227 cpu-dai = <&tegra_i2s3>;
228 codec-dai = <&spdif_dit0>;
229 cpu-dai-name = "I2S3";
230 codec-dai-name = "dit-hifi";
231 tx-mask = <0xFF>;
232 rx-mask = <0xFF>;
233 format = "dsp_a";
234 bitclock-slave;
235 frame-slave;
236 bitclock-noninversion;
237 frame-noninversion;
238 bit-format = "s32_le";
239 bclk_ratio = <1>;
240 srate = <48000>;
241 num-channel = <8>;
242 name-prefix = "x";
243 };
244 nvidia,dai-link-2 {
245 link-name = "spdif-dit-1";
246 cpu-dai = <&tegra_i2s5>;
247 codec-dai = <&spdif_dit0>;
248 cpu-dai-name = "I2S5";
249 codec-dai-name = "dit-hifi";
250 tx-mask = <0xFF>;
251 rx-mask = <0xFF>;
252 format = "i2s";
253 bitclock-slave;
254 frame-slave;
255 bitclock-noninversion;
256 frame-noninversion;
257 bit-format = "s16_le";
258 bclk_ratio = <2>;
259 srate = <48000>;
260 num-channel = <2>;
261 name-prefix = "x";
262 };
263 nvidia,dai-link-3 {
264 link-name = "spdif-dit-2";
265 cpu-dai = <&tegra_i2s1>;
266 codec-dai = <&spdif_dit0>;
267 cpu-dai-name = "I2S1";
268 codec-dai-name = "dit-hifi";
269 tx-mask = <0xFF>;
270 rx-mask = <0xFF>;
271 format = "i2s";
272 bitclock-slave;
273 frame-slave;
274 bitclock-noninversion;
275 frame-noninversion;
276 bit-format = "s16_le";
277 bclk_ratio = <2>;
278 srate = <8000>;
279 num-channel = <2>;
280 name-prefix = "x";
281 };
282 nvidia,dai-link-4 {
283 link-name = "spdif-dit-3";
284 cpu-dai = <&tegra_dmic1>;
285 codec-dai = <&spdif_dit0>;
286 cpu-dai-name = "DMIC1";
287 codec-dai-name = "dit-hifi";
288 format = "i2s";
289 bit-format = "s16_le";
290 srate = <48000>;
291 num-channel = <2>;
292 name-prefix = "dmic-x";
293 };
294 nvidia,dai-link-5 {
295 link-name = "spdif-dit-4";
296 cpu-dai = <&tegra_dspk1>;
297 codec-dai = <&spdif_dit0>;
298 cpu-dai-name = "DSPK1";
299 codec-dai-name = "dit-hifi";
300 format = "i2s";
301 bit-format = "s16_le";
302 srate = <48000>;
303 num-channel = <2>;
304 name-prefix = "dspk-x";
305 };
306
307 };
308
309 spi6: spi@3270000{
310 status = "okay";
311 spi@0 {
312 compatible = "spidev";
313 reg = <1>;
314 spi-max-frequency = <20000000>;
315
316 controller-data {
317 nvidia,x1-len-limit = <16>;
318 nvidia,x1-bus-speed = <20000000>; /* In Mhz */
319 nvidia,x1-dymmy-cycle = <0>;
320 nvidia,x4-bus-speed = <20000000>;
321 nvidia,x4-dymmy-cycle = <8>;
322 nvidia,ifddr-div2-sdr = <1>;
323 nvidia,x4-is-ddr=<1>;
324 };
325
326 };
327 spiflash@1 {
328 #address-cells = <1>;
329 #size-cells = <1>;
330 compatible = "s25fs256s";
331 reg = <0>;
332 spi-max-frequency = <20000000>;
333 partition@0 {
334 label = "Bootloader";
335 reg = <0x00000000 0x2000000>;
336 };
337 controller-data {
338 nvidia,x1-len-limit = <16>;
339 nvidia,x1-bus-speed = <20000000>; /* In Mhz */
340 nvidia,x1-dymmy-cycle = <8>;
341 nvidia,x4-bus-speed = <20000000>;
342 nvidia,x4-dymmy-cycle = <8>;
343 nvidia,ifddr-div2-sdr = <1>;
344 nvidia,x4-is-ddr=<1>;
345 };
346 };
347
348 };
349
350 mipical {
351 status = "okay";
352 };
353
354 host1x {
355 nvdisplay@15200000 {
356 status = "okay";
357 nvidia,fb-bpp = <32>; /* bits per pixel */
358 nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
359 nvidia,fb-win = <0>;
360 nvidia,dc-ctrlnum = <0>;
361 nvidia,dc-or-node = "/host1x/dsi";
362 };
363
364 nvdisplay@15210000 {
365 status = "disabled";
366 nvidia,fb-bpp = <32>; /* bits per pixel */
367 nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
368 nvidia,fb-win = <3>;
369 nvidia,dc-ctrlnum = <1>;
370 nvidia,dc-or-node = "/host1x/sor1";
371 };
372
373 nvdisplay@15220000 {
374 status = "disabled";
375 nvidia,fb-bpp = <32>; /* bits per pixel */
376 nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
377 nvidia,fb-win = <3>;
378 nvidia,dc-ctrlnum = <2>;
379 };
380
381 dsi { /* dsi@15300000 */
382 status = "okay";
383 panel-s-wuxga-8-0 {
384 status = "okay";
385 };
386 };
387
388 sor {
389 status = "disabled";
390 };
391
392 sor1 {
393 status = "disabled";
394 };
395
396 dpaux@155c0000 {
397 status = "disabled";
398 };
399
400 dpaux@15040000 {
401 status = "disabled";
402 };
403 };
404
405 denver-pmu {
406 status = "disabled";
407 };
408};
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-virtual-clock.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-virtual-clock.dtsi
deleted file mode 100644
index 4f59e99f2..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-virtual-clock.dtsi
+++ /dev/null
@@ -1,103 +0,0 @@
1/*
2 * arch/arm64/boot/dts/tegra186-platforms/tegra186-sim-virtual-clock.dtsi
3 *
4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21/ {
22 kfuse@0x3830000 {
23 clocks = <&clk32k_in>;
24 clock-names = "kfuse";
25 };
26
27 host1x {
28 clocks = <&clk32k_in>, <&clk32k_in>;
29 clock-names = "host1x", "actmon";
30
31 nvcsi@150c0000 {
32 clocks = <&clk32k_in>, <&clk32k_in>;
33 clock-names = "nvcsi", "nvcsilp";
34 };
35
36 vi@15700000 {
37
38 clocks = <&clk32k_in>, <&clk32k_in>,
39 <&clk32k_in>;
40 clock-names = "vi", "nvcsi", "nvcsilp";
41 };
42
43 isp@15600000 {
44 clocks = <&clk32k_in>;
45 clock-names = "isp";
46 };
47
48 dsi {
49 clocks = <&clk32k_in>;
50 clock-names = "clk32k_in";
51 };
52
53 vic@15340000 {
54 clocks = <&clk32k_in>;
55 clock-names = "vic";
56 };
57
58 nvenc@154c0000 {
59 clocks = <&clk32k_in>;
60 clock-names = "nvenc";
61 };
62
63 nvdec@15480000 {
64 clocks = <&clk32k_in>, <&clk32k_in>;
65 clock-names = "nvdec", "kfuse";
66 };
67
68 nvjpg@15380000 {
69 clocks = <&clk32k_in>;
70 clock-names = "nvjpg";
71 };
72
73 tsec@15500000 {
74 clocks = <&clk32k_in>;
75 clock-names = "tsec";
76 };
77
78 tsecb@15100000 {
79 clocks = <&clk32k_in>;
80 clock-names = "tsecb";
81 };
82
83 se@15810000 {
84 clocks = <&clk32k_in>, <&clk32k_in>;
85 clock-names = "se", "entropy";
86 };
87
88 se@15820000 {
89 clocks = <&clk32k_in>, <&clk32k_in>;
90 clock-names = "se", "entropy";
91 };
92
93 se@15830000 {
94 clocks = <&clk32k_in>, <&clk32k_in>;
95 clock-names = "se", "entropy";
96 };
97
98 se@15840000 {
99 clocks = <&clk32k_in>, <&clk32k_in>;
100 clock-names = "se", "entropy";
101 };
102 };
103};
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34324618-private.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34324618-private.dtsi
deleted file mode 100644
index e924da012..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34324618-private.dtsi
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * tegra186-sim-cl34324618-private.dtsi: Dummy file for avoid mod GVS build
3 * break.
4 *
5 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539-private.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539-private.dtsi
deleted file mode 100644
index de37559f3..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539-private.dtsi
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * tegra186-sim-cl34563539-private.dtsi: Temp file to avoid mods GVS build break
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539.dts b/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539.dts
deleted file mode 100644
index 7705350d9..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539.dts
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * arch/arm64/boot/dts/tegra186-sim-cl34563539.dts
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 *
19 */
20
21/*
22 * DISCLAIMER: THIS FILE IS AUTO GENERATED. DO NOT MANUALLY EDIT THIS FILE!!!
23 */
24
25
26#include "tegra186-platforms/tegra186-sim-private.dts"
27#include "tegra186-platforms/tegra186-sim-virtual-clock.dtsi"
28
29/ {
30 /* chosen */
31};
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-sim-fpga.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-sim-fpga.dtsi
deleted file mode 100644
index 106b24d9f..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-sim-fpga.dtsi
+++ /dev/null
@@ -1,280 +0,0 @@
1/*
2 * tegra186-soc-sim-fpga.dtsi: Tegra186 soc dtsi for sim/FPGA
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16#include "tegra186-soc/tegra186-soc-base.dtsi"
17/ {
18 reserved-memory {
19 generic_carveout {
20 status = "okay";
21 };
22
23 aon-ivc {
24 status = "okay";
25 };
26 };
27
28 arm-pmu {
29 status = "disabled";
30 };
31
32 tegra-carveouts {
33 status = "okay";
34 };
35
36 timer {
37 status = "okay";
38 };
39
40 mc_sid@2c00000 {
41 status = "okay";
42 };
43
44 iommu@12000000 {
45 status = "okay";
46 };
47
48 mc {
49 status = "okay";
50 };
51
52
53 pmc@c360000 {
54 status = "okay";
55 };
56
57 host1x {
58 status = "okay";
59 ctx0 {
60 status = "okay";
61 };
62
63 ctx1 {
64 status = "okay";
65 };
66
67 ctx2 {
68 status = "okay";
69 };
70
71 ctx3 {
72 status = "okay";
73 };
74
75 ctx4 {
76 status = "okay";
77 };
78
79 ctx5 {
80 status = "okay";
81 };
82
83 ctx6 {
84 status = "okay";
85 };
86
87 ctx7 {
88 status = "okay";
89 };
90
91 nvcsi@150c0000 {
92 status = "okay";
93 };
94
95 vi@15700000 {
96 status = "okay";
97 };
98
99 isp@15600000 {
100 status = "okay";
101 };
102
103 dsi { /* dsi@15300000 */
104 status = "okay";
105 };
106
107 vic@15340000 {
108 status = "okay";
109 };
110
111 nvenc@154c0000 {
112 status = "okay";
113 };
114
115 nvdec@15480000 {
116 status = "okay";
117 };
118
119 nvjpg@15380000 {
120 status = "okay";
121 };
122
123 tsec@15500000 {
124 status = "okay";
125 };
126
127 tsecb@15100000 {
128 status = "okay";
129 };
130
131 se@15810000 {
132 status = "okay";
133 };
134
135 se@15820000 {
136 status = "okay";
137 };
138
139 se@15830000 {
140 status = "okay";
141 };
142
143 se@15840000 {
144 status = "okay";
145 };
146 };
147
148 gp10b {
149 status = "okay";
150 };
151
152 psci {
153 status = "okay";
154 };
155
156 interrupt-controller@3881000 {
157 status = "okay";
158 };
159
160 interrupt-controller@3000000 {
161 status = "okay";
162 };
163
164 timer@3020000 {
165 status = "okay";
166 };
167
168 clock@5000000 {
169 status = "okay";
170 };
171
172 ether_qos@2490000 {
173 status = "disabled";
174 };
175
176 ether_qos_virt_test@2490000 {
177 status = "disabled";
178 };
179
180 tegra-hsp@3c00000 {
181 status = "okay";
182 };
183
184 chipid@100000 {
185 status = "okay";
186 };
187
188 bpmp {
189 status = "okay";
190
191 bpmpthermal {
192 status = "okay";
193 };
194 };
195
196 dma@2600000 {
197 status = "okay";
198 };
199
200 spi@3270000 {
201 status = "okay";
202 };
203
204 serial@3100000 {
205 status = "okay";
206 clock-frequency = <408000000>;
207 };
208
209 pinmux@2430000 {
210 status = "okay";
211 };
212
213 gpio@2200000 {
214 status = "okay";
215 };
216
217 i2c@3160000 {
218 status = "okay";
219 };
220
221 i2c@3180000 {
222 status = "okay";
223 };
224
225 i2c@3190000 {
226 status = "okay";
227 };
228
229 bpmp_i2c {
230 status = "okay";
231 };
232
233 pcie-controller@10003000 {
234 status = "okay";
235
236 pci@1,0 {
237 status = "okay";
238 };
239
240 pci@2,0 {
241 status = "okay";
242 };
243
244 };
245
246 roc-flush@e080000 {
247 status = "okay";
248 };
249
250 clocks {
251 clk32k_in@0 {
252 status = "okay";
253 };
254 };
255
256 mttcan@c310000 {
257 status = "okay";
258 };
259
260 mttcan@c320000 {
261 status = "okay";
262 };
263
264 cpuidle {
265 compatible = "nvidia,tegra18x-cpuidle";
266 status = "okay";
267 };
268
269 cpufreq@e070000 {
270 status = "okay";
271 nvidia,enable-autocc3 = <0 1>, /* M_CLUSTER */
272 <1 1>; /* B_CLUSTER */
273 nvidia,autocc3-freq = <0 0>, /* M_CLUSTER */
274 <1 0>; /* B_CLUSTER */
275 };
276
277 efuse@3820000 {
278 status = "okay";
279 };
280};
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 02:57:15 -0400