diff options
| author | Vidya Sagar <vidyas@nvidia.com> | 2018-01-25 08:13:39 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-27 02:46:51 -0500 |
| commit | fbd2907cd0393343da9c07c746d30314b0c75bb4 (patch) | |
| tree | dfcec61d55be3c1061b5a43c1c07da0cf9980e5c /Documentation/devicetree | |
| parent | 05c7451400f36bcca05ee1c7ce69fbf3849f2cbf (diff) | |
PCI: tegra: program TSA prod value for C5 ctrl
programs hub specific TSA prod value for controller-5
Bug 200379391
Change-Id: I14ddb3515772b20e9fd175744142c4b49b3613e7
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1645989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie-ep.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie-ep.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie-ep.txt index fe4d6fc78..cfe4f5068 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie-ep.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie-ep.txt | |||
| @@ -76,6 +76,8 @@ Optional properties: | |||
| 76 | a) speed is Gen-2 and MPS is 256B | 76 | a) speed is Gen-2 and MPS is 256B |
| 77 | b) speed is >= Gen-3 with any MPS | 77 | b) speed is >= Gen-3 with any MPS |
| 78 | - nvidia,bar0-size: Size of BAR-0 through which memory gets exposed to host | 78 | - nvidia,bar0-size: Size of BAR-0 through which memory gets exposed to host |
| 79 | - "nvidia,tsa-config" : Add TSA configuration register address to configure MC | ||
| 80 | with production settings for PCIe. Note:- this is applicable only for C5 | ||
| 79 | 81 | ||
| 80 | Power supplies for Tegra194: | 82 | Power supplies for Tegra194: |
| 81 | //TODO | 83 | //TODO |
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt index 6633e1184..201cb8729 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt | |||
| @@ -131,6 +131,8 @@ Optional properties: | |||
| 131 | - nvidia,enable-power-down : Enables power down of respective controller and | 131 | - nvidia,enable-power-down : Enables power down of respective controller and |
| 132 | corresponding PLLs if they are not shared by any other entity | 132 | corresponding PLLs if they are not shared by any other entity |
| 133 | - "nvidia,pex-wake" : Add PEX_WAKE gpio number to provide wake support. | 133 | - "nvidia,pex-wake" : Add PEX_WAKE gpio number to provide wake support. |
| 134 | - "nvidia,tsa-config" : Add TSA configuration register address to configure MC | ||
| 135 | with production settings for PCIe. Note:- this is applicable only for C5 | ||
| 134 | 136 | ||
| 135 | Power supplies for Tegra194: | 137 | Power supplies for Tegra194: |
| 136 | //TODO | 138 | //TODO |
