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authorAchal Verma <achalv@nvidia.com>2019-09-24 04:09:05 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2019-12-03 08:09:08 -0500
commitef6da321424f0aa67bb2b2d153d5e147acf05886 (patch)
tree58fecb0ba0862bd9ebb2f7f77f6df19800500be6
parent36c404b67253c2deecc97ac113c2105efeadf5b0 (diff)
[ufs-profile] More ufs config.
Add lanes, pwr, in ufs sysfs configuration node. Bug 200537746 Change-Id: Ib0113c141bc17b66b3e67e0706e92785c21afdf5 Signed-off-by: Achal Verma <achalv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2252690 GVS: Gerrit_Virtual_Submit Reviewed-by: Dmitry Pervushin <dpervushin@nvidia.com> Reviewed-by: Hemant Pedanekar <hpedanekar@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/scsi/ufs/ufs-tegra.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/scsi/ufs/ufs-tegra.c b/drivers/scsi/ufs/ufs-tegra.c
index ca0f69595..d54b27b96 100644
--- a/drivers/scsi/ufs/ufs-tegra.c
+++ b/drivers/scsi/ufs/ufs-tegra.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Authors: 4 * Authors:
5 * VenkataJagadish.p <vjagadish@nvidia.com> 5 * VenkataJagadish.p <vjagadish@nvidia.com>
@@ -90,6 +90,12 @@ static int ufs_tegra_show_configuration(struct seq_file *s, void *data)
90 seq_printf(s, 90 seq_printf(s,
91 "HS Mode RX_Gear:gear_%u TX_Gear:gear_%u %s series\n", 91 "HS Mode RX_Gear:gear_%u TX_Gear:gear_%u %s series\n",
92 rx_gear, tx_gear, freq_series); 92 rx_gear, tx_gear, freq_series);
93 seq_printf(s,
94 "LANE_RX:%u LANE_TX:%u PWR_RX:%u PWR_TX:%u\n",
95 configured_params->lane_rx,
96 configured_params->lane_tx,
97 configured_params->pwr_rx,
98 configured_params->pwr_tx);
93 } else { 99 } else {
94 seq_printf(s, 100 seq_printf(s,
95 "PWM Mode RX_Gear:gear_%u TX_Gear:gear_%u\n", 101 "PWM Mode RX_Gear:gear_%u TX_Gear:gear_%u\n",