PCI: tegra: Set debounce only for PEX_L5_RST

First interrupt is not generated on PERST# gpio for C0 & C4 controllers
if debounce is set. Only PCIe C5 controller in Jetson-Xavier is configured
as endpoint, so set debounce only for PEX_L5_RST.

bug 200510849

Change-Id: I727b254908d7ce9452892e6b82f229b4ec361053
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102419
Tested-by: Rock Yang <rocky@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 12 insertions, 10 deletions

diff --git a/drivers/pci/ep/pcie-tegra-dw-ep.c b/drivers/pci/ep/pcie-tegra-dw-ep.c
index 517ad45c9..1a5fe7dc7 100644
--- a/drivers/pci/ep/pcie-tegra-dw-ep.c
+++ b/drivers/pci/ep/pcie-tegra-dw-ep.c
@@ -1712,16 +1712,18 @@ static int tegra_pcie_dw_ep_probe(struct platform_device *pdev)
                 dev_err(pcie->dev, "pex_rst_gpio direction input failed\n");
                 goto fail_thread;
         }
-        gpiod = gpio_to_desc(pcie->pex_rst_gpio);
-        if (!gpiod) {
-                dev_err(pcie->dev, "Unable to get gpio desc\n");
-                ret = -EINVAL;
-                goto fail_thread;
-        }
-        ret = gpiod_set_debounce(gpiod, PERST_DEBOUNCE_TIME);
-        if (ret < 0) {
-                dev_err(pcie->dev, "Unable to set gpio debounce time\n");
-                goto fail_thread;
+        if (pcie->cid == CTRL_5) {
+                gpiod = gpio_to_desc(pcie->pex_rst_gpio);
+                if (!gpiod) {
+                        dev_err(pcie->dev, "Unable to get gpio desc\n");
+                        ret = -EINVAL;
+                        goto fail_thread;
+                }
+                ret = gpiod_set_debounce(gpiod, PERST_DEBOUNCE_TIME);
+                if (ret < 0) {
+                        dev_err(pcie->dev, "Unable to set gpio debounce time\n");
+                        goto fail_thread;
+                }
         }
         irq = gpio_to_irq(pcie->pex_rst_gpio);
         if (irq < 0) {