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authorTejas Sonchhatra <tmanoj@nvidia.com>2013-10-04 07:30:04 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:06:49 -0400
commitf3155f3423e837668ba2a2eca426b2ba634d1122 (patch)
tree43d70355e8ce3adbf337af273d034fb53de37caf
parent3ddeef311a48b2821fad9e3b11735406bee19387 (diff)
video: tegra: dsi: Added dsi debug interface file
Refactoring register dumping code from driver to debug file. The debug file will allow dumping of dsi registers when panel is up. Change-Id: I2b766add5cc77ae2c812e76f790f45027c920773 Signed-off-by: Tejas Sonchhatra <tmanoj@nvidia.com> Reviewed-on: http://git-master/r/300417 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Animesh Kishore <ankishore@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat
-rw-r--r--drivers/video/tegra/dc/Makefile1
-rw-r--r--drivers/video/tegra/dc/dsi.c154
-rw-r--r--drivers/video/tegra/dc/dsi.h12
-rw-r--r--drivers/video/tegra/dc/dsi_debug.c171
4 files changed, 192 insertions, 146 deletions
diff --git a/drivers/video/tegra/dc/Makefile b/drivers/video/tegra/dc/Makefile
index 457972925..cef5fdd37 100644
--- a/drivers/video/tegra/dc/Makefile
+++ b/drivers/video/tegra/dc/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_TEGRA_NVHDCP) += nvhdcp.o
11obj-y += edid.o 11obj-y += edid.o
12obj-y += nvsd.o 12obj-y += nvsd.o
13obj-y += dsi.o 13obj-y += dsi.o
14obj-$(CONFIG_DEBUG_FS) += dsi_debug.o
14obj-y += dc_sysfs.o 15obj-y += dc_sysfs.o
15obj-y += dc_config.o 16obj-y += dc_config.o
16obj-y += sor.o 17obj-y += sor.o
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 4427a2a80..37d9f8caf 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -308,7 +308,7 @@ static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
308 struct tegra_dc_dsi_data *dsi, 308 struct tegra_dc_dsi_data *dsi,
309 int no_of_frames); 309 int no_of_frames);
310 310
311inline unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi, 311unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
312 u32 reg, int index) 312 u32 reg, int index)
313{ 313{
314 unsigned long ret; 314 unsigned long ret;
@@ -320,7 +320,7 @@ inline unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
320} 320}
321EXPORT_SYMBOL(tegra_dsi_controller_readl); 321EXPORT_SYMBOL(tegra_dsi_controller_readl);
322 322
323inline void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi, 323void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
324 u32 val, u32 reg, int index) 324 u32 val, u32 reg, int index)
325{ 325{
326 BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev)); 326 BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
@@ -329,7 +329,7 @@ inline void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
329} 329}
330EXPORT_SYMBOL(tegra_dsi_controller_writel); 330EXPORT_SYMBOL(tegra_dsi_controller_writel);
331 331
332inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg) 332unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
333{ 333{
334 unsigned long ret; 334 unsigned long ret;
335 BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev)); 335 BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
@@ -339,7 +339,7 @@ inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
339} 339}
340EXPORT_SYMBOL(tegra_dsi_readl); 340EXPORT_SYMBOL(tegra_dsi_readl);
341 341
342inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg) 342void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
343{ 343{
344 int i = 0; 344 int i = 0;
345 BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev)); 345 BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
@@ -364,150 +364,10 @@ inline void tegra_dsi_reset_assert(struct tegra_dc_dsi_data *dsi)
364 tegra_periph_reset_assert(dsi->dsi_clk[i]); 364 tegra_periph_reset_assert(dsi->dsi_clk[i]);
365} 365}
366 366
367static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi);
368static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi);
369static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi); 367static inline void tegra_dsi_lp_clk_enable(struct tegra_dc_dsi_data *dsi);
370static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi); 368static inline void tegra_dsi_lp_clk_disable(struct tegra_dc_dsi_data *dsi);
371 369
372#ifdef CONFIG_DEBUG_FS 370void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
373static int dbg_dsi_show(struct seq_file *s, void *unused)
374{
375 struct tegra_dc_dsi_data *dsi = s->private;
376 unsigned long i = 0, j = 0;
377 u32 col = 0;
378 u32 base[MAX_DSI_INSTANCE] = {TEGRA_DSI_BASE, TEGRA_DSIB_BASE};
379
380 if (!dsi->enabled) {
381 seq_printf(s, "DSI controller suspended\n");
382 return 0;
383 }
384
385 tegra_dc_io_start(dsi->dc);
386 tegra_dsi_clk_enable(dsi);
387
388 /* mem dd dump */
389 for (i = 0; i < dsi->max_instances; i++) {
390 for (col = 0, j = 0; j < 0x64; j++) {
391 if (col == 0)
392 seq_printf(s, "%08lX:", base[i] + 4*j);
393 seq_printf(s, "%c%08lX", col == 2 ? '-' : ' ',
394 tegra_dsi_controller_readl(dsi, j, i));
395 if (col == 3) {
396 seq_printf(s, "\n");
397 col = 0;
398 } else
399 col++;
400 }
401 seq_printf(s, "\n");
402 }
403
404#define DUMP_REG(a) seq_printf(s, "%-45s | %#05x | %#010lx |\n", \
405 #a, a, tegra_dsi_readl(dsi, a));
406
407 DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
408 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
409 DUMP_REG(DSI_CTXSW);
410 DUMP_REG(DSI_POWER_CONTROL);
411 DUMP_REG(DSI_INT_ENABLE);
412 DUMP_REG(DSI_HOST_DSI_CONTROL);
413 DUMP_REG(DSI_CONTROL);
414 DUMP_REG(DSI_SOL_DELAY);
415 DUMP_REG(DSI_MAX_THRESHOLD);
416 DUMP_REG(DSI_TRIGGER);
417 DUMP_REG(DSI_TX_CRC);
418 DUMP_REG(DSI_STATUS);
419 DUMP_REG(DSI_INIT_SEQ_CONTROL);
420 DUMP_REG(DSI_INIT_SEQ_DATA_0);
421 DUMP_REG(DSI_INIT_SEQ_DATA_1);
422 DUMP_REG(DSI_INIT_SEQ_DATA_2);
423 DUMP_REG(DSI_INIT_SEQ_DATA_3);
424 DUMP_REG(DSI_INIT_SEQ_DATA_4);
425 DUMP_REG(DSI_INIT_SEQ_DATA_5);
426 DUMP_REG(DSI_INIT_SEQ_DATA_6);
427 DUMP_REG(DSI_INIT_SEQ_DATA_7);
428 DUMP_REG(DSI_PKT_SEQ_0_LO);
429 DUMP_REG(DSI_PKT_SEQ_0_HI);
430 DUMP_REG(DSI_PKT_SEQ_1_LO);
431 DUMP_REG(DSI_PKT_SEQ_1_HI);
432 DUMP_REG(DSI_PKT_SEQ_2_LO);
433 DUMP_REG(DSI_PKT_SEQ_2_HI);
434 DUMP_REG(DSI_PKT_SEQ_3_LO);
435 DUMP_REG(DSI_PKT_SEQ_3_HI);
436 DUMP_REG(DSI_PKT_SEQ_4_LO);
437 DUMP_REG(DSI_PKT_SEQ_4_HI);
438 DUMP_REG(DSI_PKT_SEQ_5_LO);
439 DUMP_REG(DSI_PKT_SEQ_5_HI);
440 DUMP_REG(DSI_DCS_CMDS);
441 DUMP_REG(DSI_PKT_LEN_0_1);
442 DUMP_REG(DSI_PKT_LEN_2_3);
443 DUMP_REG(DSI_PKT_LEN_4_5);
444 DUMP_REG(DSI_PKT_LEN_6_7);
445 DUMP_REG(DSI_PHY_TIMING_0);
446 DUMP_REG(DSI_PHY_TIMING_1);
447 DUMP_REG(DSI_PHY_TIMING_2);
448 DUMP_REG(DSI_BTA_TIMING);
449 DUMP_REG(DSI_TIMEOUT_0);
450 DUMP_REG(DSI_TIMEOUT_1);
451 DUMP_REG(DSI_TO_TALLY);
452 DUMP_REG(DSI_PAD_CONTROL);
453 DUMP_REG(DSI_PAD_CONTROL_CD);
454 DUMP_REG(DSI_PAD_CD_STATUS);
455 DUMP_REG(DSI_VID_MODE_CONTROL);
456 DUMP_REG(DSI_PAD_CONTROL_0_VS1);
457 DUMP_REG(DSI_PAD_CONTROL_CD_VS1);
458 DUMP_REG(DSI_PAD_CD_STATUS_VS1);
459 DUMP_REG(DSI_PAD_CONTROL_1_VS1);
460 DUMP_REG(DSI_PAD_CONTROL_2_VS1);
461 DUMP_REG(DSI_PAD_CONTROL_3_VS1);
462 DUMP_REG(DSI_PAD_CONTROL_4_VS1);
463 DUMP_REG(DSI_GANGED_MODE_CONTROL);
464 DUMP_REG(DSI_GANGED_MODE_START);
465 DUMP_REG(DSI_GANGED_MODE_SIZE);
466#undef DUMP_REG
467
468 tegra_dsi_clk_disable(dsi);
469 tegra_dc_io_end(dsi->dc);
470
471 return 0;
472}
473
474static int dbg_dsi_open(struct inode *inode, struct file *file)
475{
476 return single_open(file, dbg_dsi_show, inode->i_private);
477}
478
479static const struct file_operations dbg_fops = {
480 .open = dbg_dsi_open,
481 .read = seq_read,
482 .llseek = seq_lseek,
483 .release = single_release,
484};
485
486static struct dentry *dsidir;
487
488static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
489{
490 struct dentry *retval;
491
492 dsidir = debugfs_create_dir("tegra_dsi", NULL);
493 if (!dsidir)
494 return;
495 retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
496 &dbg_fops);
497 if (!retval)
498 goto free_out;
499 return;
500free_out:
501 debugfs_remove_recursive(dsidir);
502 dsidir = NULL;
503 return;
504}
505#else
506static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
507{ }
508#endif
509
510static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
511{ 371{
512 int i = 0; 372 int i = 0;
513 for (i = 0; i < dsi->max_instances; i++) { 373 for (i = 0; i < dsi->max_instances; i++) {
@@ -516,7 +376,7 @@ static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
516 } 376 }
517} 377}
518 378
519static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi) 379void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
520{ 380{
521 int i = 0; 381 int i = 0;
522 for (i = 0; i < dsi->max_instances; i++) { 382 for (i = 0; i < dsi->max_instances; i++) {
@@ -3948,7 +3808,9 @@ static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3948{ 3808{
3949 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc); 3809 struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3950 3810
3811#ifdef CONFIG_DEBUG_FS
3951 tegra_dc_dsi_debug_create(dsi); 3812 tegra_dc_dsi_debug_create(dsi);
3813#endif
3952 3814
3953 if (dsi->info.dsi2lvds_bridge_enable) 3815 if (dsi->info.dsi2lvds_bridge_enable)
3954 dsi->out_ops = &tegra_dsi2lvds_ops; 3816 dsi->out_ops = &tegra_dsi2lvds_ops;
diff --git a/drivers/video/tegra/dc/dsi.h b/drivers/video/tegra/dc/dsi.h
index bec409949..5811426b0 100644
--- a/drivers/video/tegra/dc/dsi.h
+++ b/drivers/video/tegra/dc/dsi.h
@@ -423,6 +423,18 @@ extern struct tegra_dsi_out_ops tegra_dsi2edp_ops;
423#define tegra_dsi2edp_ops (*(struct tegra_dsi_out_ops *)NULL) 423#define tegra_dsi2edp_ops (*(struct tegra_dsi_out_ops *)NULL)
424#endif 424#endif
425 425
426#ifdef CONFIG_DEBUG_FS
427void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi);
428#endif
429void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi);
430void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi);
431unsigned long tegra_dsi_controller_readl(struct tegra_dc_dsi_data *dsi,
432 u32 reg, int index);
433unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg);
434void tegra_dsi_controller_writel(struct tegra_dc_dsi_data *dsi,
435 u32 val, u32 reg, int index);
436void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg);
437
426static inline void *tegra_dsi_get_outdata(struct tegra_dc_dsi_data *dsi) 438static inline void *tegra_dsi_get_outdata(struct tegra_dc_dsi_data *dsi)
427{ 439{
428 return dsi->out_data; 440 return dsi->out_data;
diff --git a/drivers/video/tegra/dc/dsi_debug.c b/drivers/video/tegra/dc/dsi_debug.c
new file mode 100644
index 000000000..e08a686b9
--- /dev/null
+++ b/drivers/video/tegra/dc/dsi_debug.c
@@ -0,0 +1,171 @@
1/*
2 * drivers/video/tegra/dc/dsi_debug.c
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION, All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/clk.h>
19#include <linux/moduleparam.h>
20#include <linux/export.h>
21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
23#include "dc_reg.h"
24#include "dc_priv.h"
25#include "dev.h"
26#include "dsi_regs.h"
27#include "dsi.h"
28/* HACK! This needs to come from DT */
29#include "../../../../arch/arm/mach-tegra/iomap.h"
30
31#ifdef CONFIG_DEBUG_FS
32
33static int dbg_dsi_show(struct seq_file *s, void *unused)
34{
35 struct tegra_dc_dsi_data *dsi = s->private;
36 unsigned long i = 0, j = 0;
37 u32 col = 0;
38 u32 base[MAX_DSI_INSTANCE] = {TEGRA_DSI_BASE, TEGRA_DSIB_BASE};
39
40 if (!dsi->enabled) {
41 seq_puts(s, "DSI controller suspended\n");
42 return 0;
43 }
44
45 tegra_dc_io_start(dsi->dc);
46 tegra_dsi_clk_enable(dsi);
47
48 /* mem dd dump */
49 for (i = 0; i < dsi->max_instances; i++) {
50 for (col = 0, j = 0; j < 0x64; j++) {
51 if (col == 0)
52 seq_printf(s, "%08lX:", base[i] + 4*j);
53 seq_printf(s, "%c%08lX", col == 2 ? '-' : ' ',
54 tegra_dsi_controller_readl(dsi, j, i));
55 if (col == 3) {
56 seq_puts(s, "\n");
57 col = 0;
58 } else
59 col++;
60 }
61 seq_puts(s, "\n");
62 }
63
64#define DUMP_REG(a) seq_printf(s, "%-45s | %#05x | %#010lx |\n", \
65 #a, a, tegra_dsi_readl(dsi, a));
66
67 DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
68 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
69 DUMP_REG(DSI_CTXSW);
70 DUMP_REG(DSI_POWER_CONTROL);
71 DUMP_REG(DSI_INT_ENABLE);
72 DUMP_REG(DSI_HOST_DSI_CONTROL);
73 DUMP_REG(DSI_CONTROL);
74 DUMP_REG(DSI_SOL_DELAY);
75 DUMP_REG(DSI_MAX_THRESHOLD);
76 DUMP_REG(DSI_TRIGGER);
77 DUMP_REG(DSI_TX_CRC);
78 DUMP_REG(DSI_STATUS);
79 DUMP_REG(DSI_INIT_SEQ_CONTROL);
80 DUMP_REG(DSI_INIT_SEQ_DATA_0);
81 DUMP_REG(DSI_INIT_SEQ_DATA_1);
82 DUMP_REG(DSI_INIT_SEQ_DATA_2);
83 DUMP_REG(DSI_INIT_SEQ_DATA_3);
84 DUMP_REG(DSI_INIT_SEQ_DATA_4);
85 DUMP_REG(DSI_INIT_SEQ_DATA_5);
86 DUMP_REG(DSI_INIT_SEQ_DATA_6);
87 DUMP_REG(DSI_INIT_SEQ_DATA_7);
88 DUMP_REG(DSI_PKT_SEQ_0_LO);
89 DUMP_REG(DSI_PKT_SEQ_0_HI);
90 DUMP_REG(DSI_PKT_SEQ_1_LO);
91 DUMP_REG(DSI_PKT_SEQ_1_HI);
92 DUMP_REG(DSI_PKT_SEQ_2_LO);
93 DUMP_REG(DSI_PKT_SEQ_2_HI);
94 DUMP_REG(DSI_PKT_SEQ_3_LO);
95 DUMP_REG(DSI_PKT_SEQ_3_HI);
96 DUMP_REG(DSI_PKT_SEQ_4_LO);
97 DUMP_REG(DSI_PKT_SEQ_4_HI);
98 DUMP_REG(DSI_PKT_SEQ_5_LO);
99 DUMP_REG(DSI_PKT_SEQ_5_HI);
100 DUMP_REG(DSI_DCS_CMDS);
101 DUMP_REG(DSI_PKT_LEN_0_1);
102 DUMP_REG(DSI_PKT_LEN_2_3);
103 DUMP_REG(DSI_PKT_LEN_4_5);
104 DUMP_REG(DSI_PKT_LEN_6_7);
105 DUMP_REG(DSI_PHY_TIMING_0);
106 DUMP_REG(DSI_PHY_TIMING_1);
107 DUMP_REG(DSI_PHY_TIMING_2);
108 DUMP_REG(DSI_BTA_TIMING);
109 DUMP_REG(DSI_TIMEOUT_0);
110 DUMP_REG(DSI_TIMEOUT_1);
111 DUMP_REG(DSI_TO_TALLY);
112 DUMP_REG(DSI_PAD_CONTROL);
113 DUMP_REG(DSI_PAD_CONTROL_CD);
114 DUMP_REG(DSI_PAD_CD_STATUS);
115 DUMP_REG(DSI_VID_MODE_CONTROL);
116 DUMP_REG(DSI_PAD_CONTROL_0_VS1);
117 DUMP_REG(DSI_PAD_CONTROL_CD_VS1);
118 DUMP_REG(DSI_PAD_CD_STATUS_VS1);
119 DUMP_REG(DSI_PAD_CONTROL_1_VS1);
120 DUMP_REG(DSI_PAD_CONTROL_2_VS1);
121 DUMP_REG(DSI_PAD_CONTROL_3_VS1);
122 DUMP_REG(DSI_PAD_CONTROL_4_VS1);
123 DUMP_REG(DSI_GANGED_MODE_CONTROL);
124 DUMP_REG(DSI_GANGED_MODE_START);
125 DUMP_REG(DSI_GANGED_MODE_SIZE);
126#undef DUMP_REG
127
128 tegra_dsi_clk_disable(dsi);
129 tegra_dc_io_end(dsi->dc);
130
131 return 0;
132}
133
134static int dbg_dsi_open(struct inode *inode, struct file *file)
135{
136 return single_open(file, dbg_dsi_show, inode->i_private);
137}
138
139static const struct file_operations dbg_fops = {
140 .open = dbg_dsi_open,
141 .read = seq_read,
142 .llseek = seq_lseek,
143 .release = single_release,
144};
145
146static struct dentry *dsidir;
147
148void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
149{
150 struct dentry *retval;
151
152 dsidir = debugfs_create_dir("tegra_dsi", NULL);
153 if (!dsidir)
154 return;
155 retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
156 &dbg_fops);
157 if (!retval)
158 goto free_out;
159 return;
160free_out:
161 debugfs_remove_recursive(dsidir);
162 dsidir = NULL;
163 return;
164}
165EXPORT_SYMBOL(tegra_dc_dsi_debug_create);
166#else
167void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
168{}
169EXPORT_SYMBOL(tegra_dc_dsi_debug_create);
170
171#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 04:48:33 -0500