dc: remove REF_TO_SYNC programming for nvdisp

H_REF_TO_SYNC and V_REF_TO_SYNC are legacy timing parameters
that don't apply to nvdisplay. This patch cleans up and fixes
our common mode handling logic accordingly:
1) Update tegra_dc_get_override_mode() so that it only reads
   the DC_DISP_REF_TO_SYNC register for T21x when querying the
   BL mode. This register doesn't even exist anymore on T186/T194.
2) Update the DP/HDMI mode filters so that they only enforce
   the V_FRONT_PORCH >= V_REF_TO_SYNC + 1 constraint for T21x.
3) Update tegra_dsi_wait_frame_end() so that it waits for
   V_REF_TO_SYNC additional lines only on T21x.
4) Fork off a separate mode check function for nvdisplay. This
   function contains the appropriate constraints as per the
   HW guidelines.
5) Update parse_modes() in of_dc so that it ignores the
   "nvidia,h-ref-to-sync" and "nvidia,v-ref-to-sync" properties
   on nvdisplay.
6) Completely stub out the tegra_dc_sor_disable_win_short_raster()
   and tegra_dc_sor_restore_win_and_raster() functions for nvdisplay.
   These functions are currently invoked as part of the SOR detach
   sequence, but make no sense for the most part, given the current
   T186/T194 SOR programming guidelines. The window detach and restore
   sequences are still needed, but this will be cleaned up in a
   follow-up change.

   As part of this SOR change, update the MSA source so that it's
   generated from the RG, instead of the OR. Beginning with T186,
   async FIFOs were added between the RG and OR to buffer MSA data
   coming directly from the RG via a new bus. We should be using
   this method instead.

Bug 200388676
JIRA TDS-2003

Change-Id: I115ee96c9510b477b90257c3510c11afbad51d23
Signed-off-by: Shu Zhong <shuz@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1659736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ujwal Patel <ujwalp@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 97 insertions, 62 deletions

diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index fb73e93ce..2fddad89f 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -3874,9 +3874,13 @@ static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
                 mode->rated_pclk = 0;
 
                 tegra_dc_get(dc);
-                val = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
-                mode->h_ref_to_sync = val & 0xffff;
-                mode->v_ref_to_sync = (val >> 16) & 0xffff;
+
+                /* {V,H}_REF_TO_SYNC do NOT exist on nvdisplay. */
+                if (!tegra_dc_is_nvdisplay()) {
+                        val = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
+                        mode->h_ref_to_sync = val & 0xffff;
+                        mode->v_ref_to_sync = (val >> 16) & 0xffff;
+                }
 
                 val = tegra_dc_readl(dc, DC_DISP_SYNC_WIDTH);
                 mode->h_sync_width = val & 0xffff;
@@ -4433,7 +4437,7 @@ static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
 void tegra_dc_set_act_vfp(struct tegra_dc *dc, int vfp)
 {
         WARN_ON(!mutex_is_locked(&dc->lock));
-        WARN_ON(vfp < dc->mode.v_ref_to_sync + 1);
+        WARN_ON(!tegra_dc_is_nvdisplay() && vfp < dc->mode.v_ref_to_sync + 1);
         /* It's very unlikely that active vfp will need to
          * be changed outside of vrr context */
         WARN_ON(!dc->out->vrr || !dc->out->vrr->capability);
diff --git a/drivers/video/tegra/dc/dp.c b/drivers/video/tegra/dc/dp.c
index afc04056a..0f02b74a8 100644
--- a/drivers/video/tegra/dc/dp.c
+++ b/drivers/video/tegra/dc/dp.c
@@ -2922,10 +2922,12 @@ static bool tegra_dp_mode_filter(const struct tegra_dc *dc,
                 return false;
 
         /*
-         * Work around for modes that fail the constraint:
+         * Workaround for modes that fail the constraint:
          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
+         *
+         * This constraint does not apply to nvdisplay.
          */
-        if (mode->lower_margin == 1) {
+        if (!tegra_dc_is_nvdisplay() && mode->lower_margin == 1) {
                 mode->lower_margin++;
                 mode->upper_margin--;
                 mode->vmode |= FB_VMODE_ADJUSTED;
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 91b04d3e1..a75c79f85 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -1998,7 +1998,8 @@ static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
                 frame_period);
 
         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
-        udelay(mode.v_ref_to_sync * line_period);
+        if (!tegra_dc_is_nvdisplay())
+                udelay(mode.v_ref_to_sync * line_period);
 
         return timeout;
 }
diff --git a/drivers/video/tegra/dc/hdmi2.0.c b/drivers/video/tegra/dc/hdmi2.0.c
index 05394137f..b0961a033 100644
--- a/drivers/video/tegra/dc/hdmi2.0.c
+++ b/drivers/video/tegra/dc/hdmi2.0.c
@@ -367,10 +367,12 @@ static bool tegra_hdmi_fb_mode_filter(const struct tegra_dc *dc,
                 return false;
 
         /*
-         * Work around for modes that fail the constraint:
+         * Workaround for modes that fail the constraint:
          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
+         *
+         * This constraint does not apply to nvdisplay.
          */
-        if (mode->lower_margin == 1) {
+        if (!tegra_dc_is_nvdisplay() && mode->lower_margin == 1) {
                 mode->lower_margin++;
                 mode->upper_margin--;
                 mode->vmode |= FB_VMODE_ADJUSTED;
diff --git a/drivers/video/tegra/dc/mode.c b/drivers/video/tegra/dc/mode.c
index 0998dc83e..72532300c 100644
--- a/drivers/video/tegra/dc/mode.c
+++ b/drivers/video/tegra/dc/mode.c
@@ -368,32 +368,22 @@ static bool check_yuv_timings(struct tegra_dc_mode *mode, bool verbose)
         return true;
 }
 
-static bool check_mode_timings(const struct tegra_dc *dc,
+static bool check_t21x_mode_timings(const struct tegra_dc *dc,
                                struct tegra_dc_mode *mode, bool verbose)
 {
-#if defined(CONFIG_TEGRA_HDMI2_0)
         if ((mode->vmode & FB_VMODE_Y420) ||
-            (mode->vmode & FB_VMODE_Y420_ONLY)) {
+                (mode->vmode & FB_VMODE_Y420_ONLY))
                 mode->v_ref_to_sync = 1;
-        } else {
+        else
                 calc_ref_to_sync(mode);
-        }
+
         mode->h_ref_to_sync = 1;
-#else
-        if (dc->out->type == TEGRA_DC_OUT_HDMI) {
-                        /* HDMI controller requires h_ref=1, v_ref=1 */
-                mode->h_ref_to_sync = 1;
-                mode->v_ref_to_sync = 1;
-        } else {
-                calc_ref_to_sync(mode);
-        }
-#endif
 
         if (dc->out->type == TEGRA_DC_OUT_DSI && dc->out->vrr) {
                 mode->h_ref_to_sync =
-                        dc->out->modes[dc->out->n_modes-1].h_ref_to_sync;
+                        dc->out->modes[dc->out->n_modes - 1].h_ref_to_sync;
                 mode->v_ref_to_sync =
-                        dc->out->modes[dc->out->n_modes-1].v_ref_to_sync;
+                        dc->out->modes[dc->out->n_modes - 1].v_ref_to_sync;
         }
 
         if (dc->out->type == TEGRA_DC_OUT_DP) {
@@ -408,16 +398,69 @@ static bool check_mode_timings(const struct tegra_dc *dc,
                 return false;
         }
 
+        return true;
+}
+
+static bool check_nvdisp_mode_timings(const struct tegra_dc *dc,
+                                struct tegra_dc_mode *mode, bool verbose)
+{
+        int h_total, v_total;
+
+        /*
+         * Constraint 1: V_SYNC_WIDTH  >= 1
+         *               H_SYNC_WIDTH  >= 1
+         *               V_FRONT_PORCH >= 1
+         *               H_FRONT_PORCH >= 1
+         */
+        CHK(mode->v_sync_width < 1 || mode->h_sync_width < 1 ||
+                mode->v_front_porch < 1 || mode->h_front_porch < 1,
+                "{V,H}_SYNC_WIDTH >= 1, {V,H}_FRONT_PORCH >= 1\n");
+
+        /*
+         * Constraint 2: H_DISP_ACTIVE >= 8
+         *               V_DISP_ACTIVE >= 4
+         */
+        CHK(mode->h_active < 8 || mode->v_active < 4,
+                "H_DISP_ACTIVE >= 8, V_DISP_ACTIVE >= 4\n");
+
+        /*
+         * Constraint 3: H_TOTAL < 32768
+         *               V_TOTAL < 32768
+         */
+        h_total = mode->h_sync_width + mode->h_back_porch + mode->h_active +
+                mode->h_front_porch;
+        v_total = mode->v_sync_width + mode->v_back_porch + mode->v_active +
+                mode->v_front_porch;
+        CHK(h_total >= 32768 || v_total >= 32768,
+                "H_TOTAL < 32768, V_TOTAL < 32768\n");
+
+        /* Constraint 4: H_BLANK >= 25 */
+        CHK(h_total - mode->h_active < 25,
+                "H_BLANK >= 25\n");
+
+        return true;
+}
+
+static bool check_mode_timings(const struct tegra_dc *dc,
+                                struct tegra_dc_mode *mode, bool verbose)
+{
+        bool check;
+
         if (!check_yuv_timings(mode, verbose))
                 return false;
 
+        if (tegra_dc_is_nvdisplay())
+                check = check_nvdisp_mode_timings(dc, mode, verbose);
+        else
+                check = check_t21x_mode_timings(dc, mode, verbose);
+
         if (verbose)
                 dev_dbg(&dc->ndev->dev,
                         "Using mode %dx%d pclk=%d href=%d vref=%d\n",
                         mode->h_active, mode->v_active, mode->pclk,
                         mode->h_ref_to_sync, mode->v_ref_to_sync);
 
-        return true;
+        return check;
 }
 
 bool check_fb_videomode_timings(const struct tegra_dc *dc,
diff --git a/drivers/video/tegra/dc/of_dc.c b/drivers/video/tegra/dc/of_dc.c
index c0e500e14..86cdffefe 100644
--- a/drivers/video/tegra/dc/of_dc.c
+++ b/drivers/video/tegra/dc/of_dc.c
@@ -1128,24 +1128,28 @@ static int parse_modes(struct tegra_dc_out *default_out,
         const struct tegra_dc_out_pin *pins = default_out->out_pins;
         int i;
 
+        /* {V,H}_REF_TO_SYNC do NOT exist on nvdisplay. */
+        if (!tegra_dc_is_nvdisplay()) {
+                if (!of_property_read_u32(np, "nvidia,h-ref-to-sync", &temp)) {
+                        modes->h_ref_to_sync = temp;
+                } else {
+                        OF_DC_LOG("of h_ref_to_sync %d\n", temp);
+                        goto parse_modes_fail;
+                }
+                if (!of_property_read_u32(np, "nvidia,v-ref-to-sync", &temp)) {
+                        modes->v_ref_to_sync = temp;
+                } else {
+                        OF_DC_LOG("of v_ref_to_sync %d\n", temp);
+                        goto parse_modes_fail;
+                }
+        }
+
         if (!of_property_read_u32(np, "clock-frequency", &temp)) {
                 modes->pclk = temp;
                 OF_DC_LOG("of pclk %d\n", temp);
         } else {
                 goto parse_modes_fail;
         }
-        if (!of_property_read_u32(np, "nvidia,h-ref-to-sync", &temp)) {
-                modes->h_ref_to_sync = temp;
-        } else {
-                OF_DC_LOG("of h_ref_to_sync %d\n", temp);
-                goto parse_modes_fail;
-        }
-        if (!of_property_read_u32(np, "nvidia,v-ref-to-sync", &temp)) {
-                modes->v_ref_to_sync = temp;
-        } else {
-                OF_DC_LOG("of v_ref_to_sync %d\n", temp);
-                goto parse_modes_fail;
-        }
         if (!of_property_read_u32(np, "hsync-len", &temp)) {
                 modes->h_sync_width = temp;
         } else {
diff --git a/drivers/video/tegra/dc/sor.c b/drivers/video/tegra/dc/sor.c
index b099fa892..59687bc95 100644
--- a/drivers/video/tegra/dc/sor.c
+++ b/drivers/video/tegra/dc/sor.c
@@ -149,24 +149,13 @@ static struct tegra_dc_mode min_mode = {
         .h_sync_width = 1,
         .v_sync_width = 1,
         .h_back_porch = 20,
-        /* V back porch for T21x is 0 and for Nvdisplay is 2 .
-         * Its populated  in tegra_dc_populate_min_mode.
-         */
-        .v_back_porch = 2,
+        .v_back_porch = 0,
         .h_active = 16,
         .v_active = 16,
         .h_front_porch = 1,
         .v_front_porch = 2,
 };
 
-static void tegra_dc_populate_min_mode(void)
-{
-        if (tegra_dc_is_nvdisplay())
-                min_mode.v_back_porch = 2;
-        else
-                min_mode.v_back_porch = 0;
-}
-
 unsigned long
 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor,
                                 u32 reg, u32 mask, u32 exp_val,
@@ -883,8 +872,6 @@ struct tegra_dc_sor_data *tegra_dc_sor_init(struct tegra_dc *dc,
                 tegra_sor_fpga_settings(dc, sor);
         init_rwsem(&sor->reset_lock);
 
-        tegra_dc_populate_min_mode();
-
         return sor;
 
 err_rst: __maybe_unused
@@ -1747,7 +1734,7 @@ tegra_dc_sor_disable_win_short_raster(struct tegra_dc *dc, int *dc_reg_ctx)
 {
         int selected_windows, i;
 
-        if (tegra_platform_is_vdk())
+        if (tegra_dc_is_nvdisplay())
                 return;
 
         selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
@@ -1796,7 +1783,7 @@ tegra_dc_sor_restore_win_and_raster(struct tegra_dc *dc, int *dc_reg_ctx)
 {
         int selected_windows, i;
 
-        if (tegra_platform_is_vdk())
+        if (tegra_dc_is_nvdisplay())
                 return;
 
         selected_windows = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
@@ -1988,14 +1975,6 @@ void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, bool is_int)
 
         tegra_sor_writel(sor, NV_SOR_DP_SPARE(sor->portnum), reg_val);
 
-        if (tegra_dc_is_nvdisplay()) {
-                if (sor->dc->out->type == TEGRA_DC_OUT_DP)
-                        tegra_sor_write_field(sor,
-                                NV_SOR_DP_SPARE(sor->portnum),
-                                NV_SOR_DP_SPARE_MSA_SRC_MASK,
-                                NV_SOR_DP_SPARE_MSA_SRC_SOR);
-        }
-
         if (sor->dc->out->type == TEGRA_DC_OUT_HDMI) {
                 if (tegra_dc_is_nvdisplay())
                         tegra_sor_write_field(sor,