inject-vm-err: CBB error handler

Add support to handle control back bone errors.

- This change adds a sample handler for cbb error.
  It is a minimal handler that just dumps error
  information to the console. This can be used as
  a reference to implement an elaborate error
  handler.

Bug 2580803

Change-Id: I2fbbc994854611a54276068ee90f1d2cffeeb948
(cherry picked from commit ea898756f7b2e4aff8f89546f3b69fc4e97fd300)
Signed-off-by: Potharaju Ravi Teja <pteja@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2279874
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Dmitry Pervushin <dpervushin@nvidia.com>
Reviewed-by: Rohit Upadhyay <rupadhyay@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 147 insertions, 5 deletions

diff --git a/drivers/virt/tegra/vm_err.c b/drivers/virt/tegra/vm_err.c
index b2f17501d..26443f136 100644
--- a/drivers/virt/tegra/vm_err.c
+++ b/drivers/virt/tegra/vm_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -388,6 +388,8 @@ static void shared_structs_check(struct device *dev)
                 sizeof(struct async_metadata_t));
         dev_info(dev, "async_bridge_err size 0x%lx\n",
                 sizeof(struct async_bridge_err_t));
+        dev_info(dev, "async_cbb_err size 0x%lx\n",
+                sizeof(struct async_cbb_err_t));
         dev_info(dev, "async_smmu_err size 0x%lx\n",
                 sizeof(struct async_smmu_err_t));
         dev_info(dev, "async_mc_err size 0x%lx\n",
@@ -399,10 +401,11 @@ static void shared_structs_check(struct device *dev)
         /* Ensure common structures shared by HV and Linux are in sync */
         BUILD_BUG_ON(sizeof(struct async_metadata_t) != 0x10);
         BUILD_BUG_ON(sizeof(struct async_bridge_err_t) != 0x74);
+        BUILD_BUG_ON(sizeof(struct async_cbb_err_t) != 0x259);
         BUILD_BUG_ON(sizeof(struct async_smmu_err_t) != 0x1C);
         BUILD_BUG_ON(sizeof(struct async_mc_err_t) != 0x24);
         BUILD_BUG_ON(sizeof(struct sync_data_abort_t) != 0x11B);
-        BUILD_BUG_ON(sizeof(struct err_data_t) != 0x127);
+        BUILD_BUG_ON(sizeof(struct err_data_t) != 0x265);
 }
 
 static int vm_err_handler_init(struct platform_device *pdev)
diff --git a/drivers/virt/tegra/vm_err_sample_handler.c b/drivers/virt/tegra/vm_err_sample_handler.c
index 5876474d3..69f7c7b67 100644
--- a/drivers/virt/tegra/vm_err_sample_handler.c
+++ b/drivers/virt/tegra/vm_err_sample_handler.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -71,6 +71,99 @@ static void print_bridge_error(const struct err_data_t * const err_data)
         pr_crit("--------------------------------------\n");
 }
 
+static void print_cache(uint32_t cache)
+{
+        if ((cache & 0x3) == 0x0) {
+                pr_crit("\t Cache\t\t\t: 0x%x--Non-cacheable/Non-Bufferable)\n",
+                        cache);
+                return;
+        }
+        if ((cache & 0x3) == 0x1) {
+                pr_crit("\t  Cache\t\t\t: 0x%x -- Device\n",
+                        cache);
+                return;
+        }
+
+        switch (cache) {
+        case 0x2:
+                pr_crit("\t  Cache\t\t\t: 0x%x -- Cacheable/Non-Bufferable\n",
+                        cache);
+                break;
+        case 0x3:
+                pr_crit("\t  Cache\t\t\t: 0x%x -- Cacheable/Bufferable\n",
+                        cache);
+                break;
+        default:
+                pr_crit("\t  Cache\t\t\t: 0x%x -- Cacheable\n",
+                        cache);
+        }
+}
+
+static void print_prot(uint32_t prot)
+{
+        char *data_str;
+        char *secure_str;
+        char *priv_str;
+
+        data_str = (prot & 0x4) ? "Instruction" : "Data";
+        secure_str = (prot & 0x2) ? "Non-Secure" : "Secure";
+        priv_str = (prot & 0x1) ? "Privileged" : "Unprivileged";
+
+        pr_crit("\t  Protection\t\t: 0x%x -- %s, %s, %s Access\n",
+                prot, priv_str, secure_str, data_str);
+}
+
+static void print_cbb_error(const struct err_data_t * const err_data)
+{
+        const struct async_cbb_err_t * const cbb_err_data =
+                &err_data->async_cbb_err;
+
+        pr_crit("Control Back Bone(CBB) error details\n");
+        pr_crit("--------------------------------------\n");
+        pr_crit("Error:%s\n", cbb_err_data->cbb_name);
+        pr_crit("\tError Logger\t\t: %d\n", cbb_err_data->error_logger);
+        pr_crit("\tErrLog0\t\t\t: 0x%x\n", cbb_err_data->errlog0);
+        pr_crit("\t  Transaction Type\t: %s\n", cbb_err_data->transaction_type);
+        pr_crit("\t  Error Code\t\t: %s\n", cbb_err_data->error_code);
+        pr_crit("\t  Error Source\t\t: %s\n",
+                cbb_err_data->error_source);
+        pr_crit("\t  Error Description\t: %s\n",
+                cbb_err_data->error_description);
+        pr_crit("\t  Packet header Lock\t: %d\n",
+                        cbb_err_data->packet_header_lock);
+        pr_crit("\t  Packet header Len1\t: %d\n",
+                        cbb_err_data->packet_header_len1);
+
+        if (cbb_err_data->header_format)
+                pr_crit("\t  NOC protocol version\t: %s\n", "version >= 2.7");
+        else
+                pr_crit("\t  NOC protocol version\t: %s\n", "version < 2.7");
+        pr_crit("\tErrLog1\t\t\t: 0x%x\n", cbb_err_data->errlog1);
+        pr_crit("\tErrLog2\t\t\t: 0x%x\n", cbb_err_data->errlog2);
+        pr_crit("\t  RouteId\t\t: 0x%llx\n", cbb_err_data->route_id);
+        pr_crit("\t  InitFlow\t\t: %s\n", cbb_err_data->initflow);
+        pr_crit("\t  Targflow\t\t: %s\n", cbb_err_data->targflow);
+        pr_crit("\t  TargSubRange\t\t: %d\n", cbb_err_data->targ_subrange);
+        pr_crit("\t  SeqId\t\t\t: %d\n", cbb_err_data->seqid);
+        pr_crit("\tErrLog3\t\t\t: 0x%x\n", cbb_err_data->errlog3);
+        pr_crit("\tErrLog4\t\t\t: 0x%x\n", cbb_err_data->errlog4);
+        pr_crit("\t  Address\t\t: 0x%llx\n", cbb_err_data->address);
+        pr_crit("\tErrLog5\t\t\t: 0x%x\n", cbb_err_data->errlog5);
+        pr_crit("\t  Master ID\t\t: %s\n", cbb_err_data->master_id);
+        pr_crit("\t  Non-Modify\t\t: 0x%x\n", cbb_err_data->non_mod);
+        pr_crit("\t  AXI ID\t\t: 0x%x\n", cbb_err_data->axi_id);
+        pr_crit("\t  Security Group(GRPSEC): 0x%x\n",
+                        cbb_err_data->security_group);
+
+        print_cache(cbb_err_data->cache);
+        print_prot(cbb_err_data->protection);
+
+        pr_crit("\t  FALCONSEC\t\t: 0x%x\n", cbb_err_data->falconsec);
+        pr_crit("\t  Virtual Queuing Channel(VQC): 0x%x\n",
+                cbb_err_data->virtual_q_channel);
+        pr_crit("--------------------------------------\n");
+}
+
 static void print_smmu_error(const struct err_data_t * const err_data,
                                 const enum err_reason reason)
 {
@@ -152,6 +245,12 @@ static bool handle_async_err_details(const struct err_data_t * const err_data)
                 enter_bad_mode = false;
                 break;
 
+        case REASON_ASYNC_CBB:
+                print_cbb_error(err_data);
+                /* CBB error may not be fatal */
+                enter_bad_mode = false;
+                break;
+
         case REASON_ASYNC_SMMU_CB:
                 print_smmu_error(err_data, err_data->err_reason);
                 /* SMMU context bank error may not be fatal */
@@ -231,6 +330,11 @@ static bool handle_peer_err_details(const struct err_data_t * const err_data)
                 enter_bad_mode = false;
                 break;
 
+        case REASON_ASYNC_CBB:
+                print_cbb_error(err_data);
+                enter_bad_mode = false;
+                break;
+
         case REASON_ASYNC_SMMU_CB:
         case REASON_ASYNC_SMMU_GLOBAL:
                 print_smmu_error(err_data, err_data->err_reason);
diff --git a/include/linux/errinfo.h b/include/linux/errinfo.h
index 641b17fa7..e75c2b308 100644
--- a/include/linux/errinfo.h
+++ b/include/linux/errinfo.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * NVIDIA CORPORATION and its licensors retain all intellectual property
  * and proprietary rights in and to this software, related documentation
@@ -18,6 +18,7 @@ enum err_reason {
         REASON_ASYNC_SMMU_GLOBAL,
         REASON_ASYNC_BRIDGE,
         REASON_ASYNC_MC,
+        REASON_ASYNC_CBB,
         REASON_SYNC_INSTR_ABORT,
         REASON_SYNC_DATA_ABORT,
         REASON_SYNC_OTHER,
@@ -53,6 +54,38 @@ struct __attribute__((__packed__)) async_bridge_err_t {
         unsigned int    cache;
 };
 
+struct __attribute__((__packed__)) async_cbb_err_t {
+        char            cbb_name[NAME_SIZE];
+        unsigned int    error_logger;
+        unsigned int    errlog0;
+        char            transaction_type[NAME_SIZE];
+        char            error_code[NAME_SIZE];
+        char            error_source[NAME_SIZE];
+        char            error_description[NAME_SIZE];
+        bool            header_format;
+        unsigned int    packet_header_lock;
+        unsigned int    packet_header_len1;
+        unsigned int    errlog1;
+        unsigned int    errlog2;
+        uint64_t        route_id;
+        char            initflow[NAME_SIZE];
+        char            targflow[NAME_SIZE];
+        unsigned int    targ_subrange;
+        unsigned int    seqid;
+        unsigned int    errlog3;
+        unsigned int    errlog4;
+        uint64_t        address;
+        unsigned int    errlog5;
+        char            master_id[NAME_SIZE];
+        unsigned int    non_mod;
+        unsigned int    axi_id;
+        unsigned int    security_group;
+        uint32_t        cache;
+        uint32_t        protection;
+        unsigned int    falconsec;
+        unsigned int    virtual_q_channel;
+};
+
 struct __attribute__((__packed__)) async_smmu_err_t {
         unsigned int    stream_id;
         unsigned int    cb_id;
@@ -93,6 +126,7 @@ struct __attribute__((__packed__)) err_data_t {
                 struct async_bridge_err_t       async_bridge_err;
                 struct async_smmu_err_t         async_smmu_err;
                 struct async_mc_err_t           async_mc_err;
+                struct async_cbb_err_t          async_cbb_err;
                 /* Synchronous */
                 struct sync_data_abort_t        sync_data_abort;
         };
diff --git a/include/linux/vm_err.h b/include/linux/vm_err.h
index a891265ce..31e3fca79 100644
--- a/include/linux/vm_err.h
+++ b/include/linux/vm_err.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2019-2020 NVIDIA CORPORATION.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -38,6 +38,7 @@ static const char * const tegra_hv_err_reason_desc[] = {
         "SMMU Global",
         "Bridge",
         "Memory Controller",
+        "Central Back Bone",
         "Instruction Abort",
         "Data Abort",
         "Other synchronous exception",