diff options
| author | ADIGUPTA <adigupta@nvidia.com> | 2021-10-25 05:37:23 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2022-02-02 09:24:20 -0500 |
| commit | 61b6f004d9893c90a4d61fe35878948844cfe9e3 (patch) | |
| tree | e38968e8df355a8552d0bb7db83b369cad580dab | |
| parent | 0b4dd54af468cc6a74f042c6ea93a2f4c9864a4e (diff) | |
tegra: cache: fix dcache flush retry
Presently we have number of retries as 10 to flush cache,
each flush operation takes around 95-100 us
Increased number of retries to 20, and
enabled debug version of flush code which
profiles latency, executing the flush instruction.
Bug 200782744
Change-Id: Ie32c17bacdb9d091e9e21a8384727a6479d83b47
Signed-off-by: Aditya Gupta <adigupta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2648815
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rohit Upadhyay <rupadhyay@nvidia.com>
GVS: Gerrit_Virtual_Submit
| -rw-r--r-- | drivers/platform/tegra/t19x_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/platform/tegra/t19x_cache.c b/drivers/platform/tegra/t19x_cache.c index 794adec28..6448b2f49 100644 --- a/drivers/platform/tegra/t19x_cache.c +++ b/drivers/platform/tegra/t19x_cache.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
| @@ -143,7 +143,7 @@ int t19x_flush_dcache_all(void) | |||
| 143 | #else | 143 | #else |
| 144 | u64 id_afr0; | 144 | u64 id_afr0; |
| 145 | u64 ret; | 145 | u64 ret; |
| 146 | u64 retry = 10; | 146 | u64 retry = 20; |
| 147 | 147 | ||
| 148 | asm volatile ("mrs %0, ID_AFR0_EL1" : "=r"(id_afr0)); | 148 | asm volatile ("mrs %0, ID_AFR0_EL1" : "=r"(id_afr0)); |
| 149 | /* check if dcache flush through mts is supported */ | 149 | /* check if dcache flush through mts is supported */ |