dt-bindings: define sids for virtualization

Add TEGRA_SID_VI_VM2 and rename TEGRA_SID_RCE_1X to TEGRA_SID_RCE_VM2.

Jira CAMASIL-184

Change-Id: I289fc9e82f5202ce8c6ca0326efe6e0fdc95b876
Signed-off-by: Mika Liljeberg <mliljeberg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770561
Reviewed-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-by: Kalle Jokiniemi <kjokiniemi@nvidia.com>
Reviewed-by: Deepak Kamurthy <dkamurthy@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/include/dt-bindings/memory/tegra194-swgroup.h b/include/dt-bindings/memory/tegra194-swgroup.h
index ad3cc6635..8b490213f 100644
--- a/include/dt-bindings/memory/tegra194-swgroup.h
+++ b/include/dt-bindings/memory/tegra194-swgroup.h
@@ -18,7 +18,7 @@
  * This is the t19x specific component of the new SID dt-binding.
  */
 #define TEGRA_SID_RCE           0x2a    /* 42 */
-#define TEGRA_SID_RCE_1X        0x2b    /* 43 */
+#define TEGRA_SID_RCE_VM2       0x2b    /* 43 */
 
 #define TEGRA_SID_RCE_RM        0x2F    /* 47 */
 #define TEGRA_SID_VIFALC        0x30    /* 48 */
@@ -43,3 +43,4 @@
 
 #define TEGRA_SID_NVDEC1        0x5C    /* 92 */
 
+#define TEGRA_SID_VI_VM2        0x64    /* 100 */