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authorVenkat Reddy Talla <vreddytalla@nvidia.com>2016-09-09 10:04:26 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-09-19 11:14:36 -0400
commit1666f1964a3fc345f6daa96fb9ea112dc256b98b (patch)
tree47211a3a576205a03c8228c2a050306c0e1f4e17
parent5c7ae255f4c11a40d6924800e59c30a6330eb321 (diff)
ARM64: dts: delete SIM dts and dtsi files
SIM dts files and dtsi include files moved to new repo $TOP/hardware/nvidia/platform/t18x/sim, deleting sim dts and dtsi files from kernel/t18x repo. Bug 200217137 Change-Id: I7fc9ccc67e417a5f69602c2fc1d5387789707a94 Signed-off-by: Venkat Reddy Talla <vreddytalla@nvidia.com> Reviewed-on: http://git-master/r/1217977 GVS: Gerrit_Virtual_Submit Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi684
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-hdmi.dtsi186
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-private.dts408
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/tegra186-sim-virtual-clock.dtsi103
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34324618-private.dtsi16
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539-private.dtsi15
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-sim-cl34563539.dts31
-rw-r--r--arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-sim-fpga.dtsi280
8 files changed, 0 insertions, 1723 deletions
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi
deleted file mode 100644
index 4c7ac1019..000000000
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-platforms/panel-sim.dtsi
+++ /dev/null
@@ -1,684 +0,0 @@
1/*
2 * arch/arm/boot/dts/panel-sim.dtsi
3 *
4 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
19 */
20#include <dt-bindings/display/tegra-dc.h>
21#include <dt-bindings/display/tegra-panel.h>
22
23/ {
24 host1x {
25 sor {
26 panel-nvidia-sim {
27 compatible = "nvidia,sim-panel";
28 nvidia,tx-pu-disable = <1>;
29 disp-default-out {
30 nvidia,out-type = <TEGRA_DC_OUT_FAKE_DP>;
31 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
32 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
33 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
34 nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
35 TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
36 TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
37 TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
38 nvidia,out-depth = <18>;
39 nvidia,out-parent-clk = "pll_d_out0";
40 nvidia,out-xres = <128>;
41 nvidia,out-yres = <96>;
42 };
43 display-timings {
44 128x96-32 {
45 clock-frequency = <27000000>;
46 hactive = <128>;
47 vactive = <96>;
48 hfront-porch = <8>;
49 hback-porch = <16>;
50 hsync-len = <8>;
51 vfront-porch = <3>;
52 vback-porch = <3>;
53 vsync-len = <4>;
54 nvidia,h-ref-to-sync = <1>;
55 nvidia,v-ref-to-sync = <1>;
56 };
57 };
58 };
59
60 dp-ufpga-panel {
61 compatible = "nvidia,dp-ufpga-panel";
62 nvidia,tx-pu-disable = <1>;
63 disp-default-out {
64 nvidia,out-type = <TEGRA_DC_OUT_DP>;
65 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
66 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
67 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
68 nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
69 TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
70 TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
71 TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
72 nvidia,out-depth = <18>;
73 nvidia,out-parent-clk = "pll_d_out0";
74 nvidia,out-xres = <720>;
75 nvidia,out-yres = <480>;
76 };
77 display-timings {
78 720x480-32 {
79 clock-frequency = <27000000>;
80 hactive = <720>;
81 vactive = <480>;
82 hfront-porch = <48>;
83 hback-porch = <80>;
84 hsync-len = <32>;
85 vfront-porch = <24>;
86 vback-porch = <126>;
87 vsync-len = <10>;
88 nvidia,h-ref-to-sync = <1>;
89 nvidia,v-ref-to-sync = <1>;
90 };
91 };
92 dp-lt-settings {
93 lt-setting@0 {
94 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
95 nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
96 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
97 nvidia,tx-pu = <0>;
98 nvidia,load-adj = <0x3>;
99 };
100 lt-setting@1 {
101 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
102 nvidia,lane-preemphasis = <PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0 PRE_EMPHASIS_L0>;
103 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
104 nvidia,tx-pu = <0>;
105 nvidia,load-adj = <0x4>;
106 };
107 lt-setting@2 {
108 nvidia,drive-current = <DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0 DRIVE_CURRENT_L0>;
109 nvidia,lane-preemphasis = <PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1 PRE_EMPHASIS_L1>;
110 nvidia,post-cursor = <POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0 POST_CURSOR2_L0>;
111 nvidia,tx-pu = <0>;
112 nvidia,load-adj = <0x6>;
113 };
114 };
115 };
116 };
117
118 sor1 {
119 panel-nvidia-sim {
120 compatible = "nvidia,sim-panel";
121 nvidia,tx-pu-disable = <1>;
122 disp-default-out {
123 nvidia,out-type = <TEGRA_DC_OUT_FAKE_DP>;
124 nvidia,out-align = <TEGRA_DC_ALIGN_MSB>;
125 nvidia,out-order = <TEGRA_DC_ORDER_RED_BLUE>;
126 nvidia,out-flags = <TEGRA_DC_OUT_CONTINUOUS_MODE>;
127 nvidia,out-pins = <TEGRA_DC_OUT_PIN_H_SYNC TEGRA_DC_OUT_PIN_POL_LOW
128 TEGRA_DC_OUT_PIN_V_SYNC TEGRA_DC_OUT_PIN_POL_LOW
129 TEGRA_DC_OUT_PIN_PIXEL_CLOCK TEGRA_DC_OUT_PIN_POL_LOW
130 TEGRA_DC_OUT_PIN_DATA_ENABLE TEGRA_DC_OUT_PIN_POL_HIGH>;
131 nvidia,out-depth = <18>;
132 nvidia,out-parent-clk = "pll_d_out0";
133 nvidia,out-xres = <128>;
134 nvidia,out-yres = <96>;
135 };
136 display-timings {
137 128x96-32 {
138 clock-frequency = <27000000>;
139 hactive = <128>;
140 vactive = <96>;
141 hfront-porch = <8>;
142 hback-porch = <16>;
143 hsync-len = <8>;
144 vfront-porch = <3>;
145 vback-porch = <3>;
146 vsync-len = <4>;
147 nvidia,h-ref-to-sync = <1>;
148 nvidia,v-ref-to-sync = <1>;
149 };
150 420x280-32 {
151 clock-frequency = <27000000>;
152 hactive = <420>;
153 vactive = <280>;