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| author | Sri Sai Ram Tangirala <stangirala@nvidia.com> | 2018-06-04 06:58:34 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-18 08:27:06 -0400 |
| commit | 01664b8d955cd1c5567fc5cdd6451be8a6340f52 (patch) | |
| tree | 77188d37c9b36f4320d7f4b1ceebcf6a8f753c63 | |
| parent | 91f342f336d71b1b15ec5ed3b1ef0edbc4006482 (diff) | |
Documentation: ufs: enable scramble bit
Add details for the dt property 'nvidia,enable-scramble' which enables
the scrambling functionality for ufs.
Bug 200385100
Change-Id: I4eb43fbb1e294d083d3ec20d0f442f2723ea8fe7
Signed-off-by: Sri Sai Ram Tangirala <stangirala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1739116
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| -rw-r--r-- | Documentation/devicetree/bindings/ufs/ufshcd-tegra.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-tegra.txt b/Documentation/devicetree/bindings/ufs/ufshcd-tegra.txt index 61f46754d..e51f8de58 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-tegra.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-tegra.txt | |||
| @@ -21,6 +21,9 @@ Optional properties: | |||
| 21 | - nvidia,configure-uphy-pll3 : Provides an option to configure uphy_pll3 for | 21 | - nvidia,configure-uphy-pll3 : Provides an option to configure uphy_pll3 for |
| 22 | ufs rate_a and rate_b modes. | 22 | ufs rate_a and rate_b modes. |
| 23 | 23 | ||
| 24 | - nvidia,enable-scramble : Enables scramble functionality. | ||
| 25 | It is required to enable scramble functionality, which is used for | ||
| 26 | encryption. | ||
| 24 | - nvidia,enable-rx-calib : Enables rx calibration functionality. | 27 | - nvidia,enable-rx-calib : Enables rx calibration functionality. |
| 25 | It is required for UFS High Speed modes. | 28 | It is required for UFS High Speed modes. |
| 26 | - nvidia,enable-x2-config : Enables 2 lane register programming support. | 29 | - nvidia,enable-x2-config : Enables 2 lane register programming support. |
